1; RUN: llc -mtriple=arm-eabi -mcpu=cortex-r52 -debug-only=machine-scheduler %s -o - 2>&1 | FileCheck %s --check-prefix=CHECK-R52 2; RUN: llc -mtriple=arm-eabi -mcpu=cortex-r52plus -debug-only=machine-scheduler %s -o - 2>&1 | FileCheck %s --check-prefix=CHECK-R52 3; REQUIRES: asserts 4 5; source_filename = "sched-2.c" 6target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" 7 8define dso_local i32 @f(i32 %a, i32 %b, i32 %c, i32 %d) local_unnamed_addr { 9entry: 10 %add = add nsw i32 %b, %a 11 %add1 = add nsw i32 %d, %c 12 %div = sdiv i32 %add, %add1 13 ret i32 %div 14} 15 16; Cortex-R52 model describes it as dual-issue with two integer ALUs 17; It should be able to issue the two additions in the same cycle. 18; CHECK-R52: MI Scheduling 19; CHECK-R52: Cycle: 14 20; CHECK-R52: Scheduling SU(5) %5:gpr = nsw ADDrr %3:gpr, %2:gpr, 14, $noreg, $noreg 21; CHECK-R52: Scheduling SU(4) %4:gpr = nsw ADDrr %1:gpr, %0:gpr, 14, $noreg, $noreg 22; CHECK-R52: Cycle: 15 23