xref: /llvm-project/llvm/test/CodeGen/ARM/pr36577.ll (revision bed1c7f061aa12417aa081e334afdba45767b938)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple armv6t2 %s -o - | FileCheck %s
3; RUN: llc -mtriple thumbv6t2 %s -o - | FileCheck %s --check-prefix=CHECK-T2
4; RUN: llc -mtriple armv7 %s -o - | FileCheck %s
5; RUN: llc -mtriple thumbv7 %s -o - | FileCheck %s --check-prefix=CHECK-T2
6; RUN: llc -mtriple thumbv7m %s -o - | FileCheck %s --check-prefix=CHECK-T2
7; RUN: llc -mtriple thumbv8m.main %s -o - | FileCheck %s --check-prefix=CHECK-T2
8
9@a = common dso_local local_unnamed_addr global i16 0, align 2
10
11define dso_local arm_aapcscc ptr @pr36577() {
12; CHECK-LABEL: pr36577:
13; CHECK:       @ %bb.0: @ %entry
14; CHECK-NEXT:    movw r0, :lower16:a
15; CHECK-NEXT:    mvn r1, #7
16; CHECK-NEXT:    movt r0, :upper16:a
17; CHECK-NEXT:    ldrh r0, [r0]
18; CHECK-NEXT:    mvn r0, r0, lsr #7
19; CHECK-NEXT:    orr r0, r1, r0, lsl #2
20; CHECK-NEXT:    bx lr
21;
22; CHECK-T2-LABEL: pr36577:
23; CHECK-T2:       @ %bb.0: @ %entry
24; CHECK-T2-NEXT:    movw r0, :lower16:a
25; CHECK-T2-NEXT:    mvn r1, #7
26; CHECK-T2-NEXT:    movt r0, :upper16:a
27; CHECK-T2-NEXT:    ldrh r0, [r0]
28; CHECK-T2-NEXT:    mvn.w r0, r0, lsr #7
29; CHECK-T2-NEXT:    orr.w r0, r1, r0, lsl #2
30; CHECK-T2-NEXT:    bx lr
31entry:
32  %0 = load i16, ptr @a, align 2
33  %1 = lshr i16 %0, 7
34  %2 = and i16 %1, 1
35  %3 = zext i16 %2 to i32
36  %4 = xor i32 %3, -1
37  %add.ptr = getelementptr inbounds ptr, ptr null, i32 %4
38  ret ptr %add.ptr
39}
40
41