xref: /llvm-project/llvm/test/CodeGen/ARM/pr35103.ll (revision 2e8111d4c4f8950ec012108dc98edc9cb934d7fa)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
2; RUN: llc -O2 -mtriple arm < %s | FileCheck %s
3
4; Function Attrs: norecurse nounwind readnone
5define i32 @foo(i32 %vreg0, i32 %vreg1, i32 %vreg2, i32 %vreg3, i32 %vreg4) local_unnamed_addr {
6; CHECK-LABEL: foo:
7; CHECK:       @ %bb.0: @ %entry
8; CHECK-NEXT:    push {r11, lr}
9; CHECK-NEXT:    adds r2, r2, r0
10; CHECK-NEXT:    mov r12, #0
11; CHECK-NEXT:    adc lr, r12, #0
12; CHECK-NEXT:    adds r0, r2, r0
13; CHECK-NEXT:    ldr r2, [sp, #8]
14; CHECK-NEXT:    adc r0, r12, #0
15; CHECK-NEXT:    adds r1, r3, r1
16; CHECK-NEXT:    adcs r1, r2, #0
17; CHECK-NEXT:    adc r0, r0, lr
18; CHECK-NEXT:    pop {r11, lr}
19; CHECK-NEXT:    mov pc, lr
20entry:
21  %conv = zext i32 %vreg2 to i64
22  %conv1 = zext i32 %vreg0 to i64
23  %add2 = add nuw nsw i64 %conv, %conv1
24  %shr = lshr i64 %add2, 32
25  %conv4 = trunc i64 %shr to i32
26  %conv5 = and i64 %add2, 4294967295
27  %add8 = add nuw nsw i64 %conv5, %conv1
28  %shr9 = lshr i64 %add8, 32
29  %conv10 = trunc i64 %shr9 to i32
30  %add11 = add nuw nsw i32 %conv10, %conv4
31  %conv12 = zext i32 %vreg3 to i64
32  %conv14 = zext i32 %vreg1 to i64
33  %add15 = add nuw nsw i64 %conv12, %conv14
34  %shr16 = lshr i64 %add15, 32
35  %conv19 = zext i32 %vreg4 to i64
36  %add20 = add nuw nsw i64 %shr16, %conv19
37  %shr22 = lshr i64 %add20, 32
38  %conv23 = trunc i64 %shr22 to i32
39  %add24 = add nuw nsw i32 %add11, %conv23
40  ret i32 %add24
41
42; The interesting bit is the next instruction which looks
43; like is computing a dead r1 but is actually computing a carry
44; for the final adc.
45
46}
47