xref: /llvm-project/llvm/test/CodeGen/ARM/popcnt.ll (revision ea2984287d91b96f5e2cc0aa66d146d6dbd1d1bb) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
3; Implement ctpop with vcnt
4
5define <8 x i8> @vcnt8(ptr %A) nounwind {
6; CHECK-LABEL: vcnt8:
7; CHECK:       @ %bb.0:
8; CHECK-NEXT:    vldr d16, [r0]
9; CHECK-NEXT:    vcnt.8 d16, d16
10; CHECK-NEXT:    vmov r0, r1, d16
11; CHECK-NEXT:    mov pc, lr
12	%tmp1 = load <8 x i8>, ptr %A
13	%tmp2 = call <8 x i8> @llvm.ctpop.v8i8(<8 x i8> %tmp1)
14	ret <8 x i8> %tmp2
15}
16
17define <16 x i8> @vcntQ8(ptr %A) nounwind {
18; CHECK-LABEL: vcntQ8:
19; CHECK:       @ %bb.0:
20; CHECK-NEXT:    vld1.64 {d16, d17}, [r0]
21; CHECK-NEXT:    vcnt.8 q8, q8
22; CHECK-NEXT:    vmov r0, r1, d16
23; CHECK-NEXT:    vmov r2, r3, d17
24; CHECK-NEXT:    mov pc, lr
25	%tmp1 = load <16 x i8>, ptr %A
26	%tmp2 = call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %tmp1)
27	ret <16 x i8> %tmp2
28}
29
30define <4 x i16> @vcnt16(ptr %A) nounwind {
31; CHECK-LABEL: vcnt16:
32; CHECK:       @ %bb.0:
33; CHECK-NEXT:    vldr d16, [r0]
34; CHECK-NEXT:    vcnt.8 d16, d16
35; CHECK-NEXT:    vpaddl.u8 d16, d16
36; CHECK-NEXT:    vmov r0, r1, d16
37; CHECK-NEXT:    mov pc, lr
38	%tmp1 = load <4 x i16>, ptr %A
39	%tmp2 = call <4 x i16> @llvm.ctpop.v4i16(<4 x i16> %tmp1)
40	ret <4 x i16> %tmp2
41}
42
43define <8 x i16> @vcntQ16(ptr %A) nounwind {
44; CHECK-LABEL: vcntQ16:
45; CHECK:       @ %bb.0:
46; CHECK-NEXT:    vld1.64 {d16, d17}, [r0]
47; CHECK-NEXT:    vcnt.8 q8, q8
48; CHECK-NEXT:    vpaddl.u8 q8, q8
49; CHECK-NEXT:    vmov r0, r1, d16
50; CHECK-NEXT:    vmov r2, r3, d17
51; CHECK-NEXT:    mov pc, lr
52	%tmp1 = load <8 x i16>, ptr %A
53	%tmp2 = call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %tmp1)
54	ret <8 x i16> %tmp2
55}
56
57define <2 x i32> @vcnt32(ptr %A) nounwind {
58; CHECK-LABEL: vcnt32:
59; CHECK:       @ %bb.0:
60; CHECK-NEXT:    vldr d16, [r0]
61; CHECK-NEXT:    vcnt.8 d16, d16
62; CHECK-NEXT:    vpaddl.u8 d16, d16
63; CHECK-NEXT:    vpaddl.u16 d16, d16
64; CHECK-NEXT:    vmov r0, r1, d16
65; CHECK-NEXT:    mov pc, lr
66	%tmp1 = load <2 x i32>, ptr %A
67	%tmp2 = call <2 x i32> @llvm.ctpop.v2i32(<2 x i32> %tmp1)
68	ret <2 x i32> %tmp2
69}
70
71define <4 x i32> @vcntQ32(ptr %A) nounwind {
72; CHECK-LABEL: vcntQ32:
73; CHECK:       @ %bb.0:
74; CHECK-NEXT:    vld1.64 {d16, d17}, [r0]
75; CHECK-NEXT:    vcnt.8 q8, q8
76; CHECK-NEXT:    vpaddl.u8 q8, q8
77; CHECK-NEXT:    vpaddl.u16 q8, q8
78; CHECK-NEXT:    vmov r0, r1, d16
79; CHECK-NEXT:    vmov r2, r3, d17
80; CHECK-NEXT:    mov pc, lr
81	%tmp1 = load <4 x i32>, ptr %A
82	%tmp2 = call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %tmp1)
83	ret <4 x i32> %tmp2
84}
85
86define <1 x i64> @vcnt64(ptr %A) nounwind {
87; CHECK-LABEL: vcnt64:
88; CHECK:       @ %bb.0:
89; CHECK-NEXT:    vldr d16, [r0]
90; CHECK-NEXT:    vcnt.8 d16, d16
91; CHECK-NEXT:    vpaddl.u8 d16, d16
92; CHECK-NEXT:    vpaddl.u16 d16, d16
93; CHECK-NEXT:    vpaddl.u32 d16, d16
94; CHECK-NEXT:    vmov r0, r1, d16
95; CHECK-NEXT:    mov pc, lr
96	%tmp1 = load <1 x i64>, ptr %A
97	%tmp2 = call <1 x i64> @llvm.ctpop.v1i64(<1 x i64> %tmp1)
98	ret <1 x i64> %tmp2
99}
100
101define <2 x i64> @vcntQ64(ptr %A) nounwind {
102; CHECK-LABEL: vcntQ64:
103; CHECK:       @ %bb.0:
104; CHECK-NEXT:    vld1.64 {d16, d17}, [r0]
105; CHECK-NEXT:    vcnt.8 q8, q8
106; CHECK-NEXT:    vpaddl.u8 q8, q8
107; CHECK-NEXT:    vpaddl.u16 q8, q8
108; CHECK-NEXT:    vpaddl.u32 q8, q8
109; CHECK-NEXT:    vmov r0, r1, d16
110; CHECK-NEXT:    vmov r2, r3, d17
111; CHECK-NEXT:    mov pc, lr
112	%tmp1 = load <2 x i64>, ptr %A
113	%tmp2 = call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %tmp1)
114	ret <2 x i64> %tmp2
115}
116
117declare <8 x i8>  @llvm.ctpop.v8i8(<8 x i8>) nounwind readnone
118declare <16 x i8> @llvm.ctpop.v16i8(<16 x i8>) nounwind readnone
119declare <4 x i16> @llvm.ctpop.v4i16(<4 x i16>) nounwind readnone
120declare <8 x i16> @llvm.ctpop.v8i16(<8 x i16>) nounwind readnone
121declare <2 x i32> @llvm.ctpop.v2i32(<2 x i32>) nounwind readnone
122declare <4 x i32> @llvm.ctpop.v4i32(<4 x i32>) nounwind readnone
123declare <1 x i64> @llvm.ctpop.v1i64(<1 x i64>) nounwind readnone
124declare <2 x i64> @llvm.ctpop.v2i64(<2 x i64>) nounwind readnone
125
126define <8 x i8> @vclz8(ptr %A) nounwind {
127; CHECK-LABEL: vclz8:
128; CHECK:       @ %bb.0:
129; CHECK-NEXT:    vldr d16, [r0]
130; CHECK-NEXT:    vclz.i8 d16, d16
131; CHECK-NEXT:    vmov r0, r1, d16
132; CHECK-NEXT:    mov pc, lr
133	%tmp1 = load <8 x i8>, ptr %A
134	%tmp2 = call <8 x i8> @llvm.ctlz.v8i8(<8 x i8> %tmp1, i1 0)
135	ret <8 x i8> %tmp2
136}
137
138define <4 x i16> @vclz16(ptr %A) nounwind {
139; CHECK-LABEL: vclz16:
140; CHECK:       @ %bb.0:
141; CHECK-NEXT:    vldr d16, [r0]
142; CHECK-NEXT:    vclz.i16 d16, d16
143; CHECK-NEXT:    vmov r0, r1, d16
144; CHECK-NEXT:    mov pc, lr
145	%tmp1 = load <4 x i16>, ptr %A
146	%tmp2 = call <4 x i16> @llvm.ctlz.v4i16(<4 x i16> %tmp1, i1 0)
147	ret <4 x i16> %tmp2
148}
149
150define <2 x i32> @vclz32(ptr %A) nounwind {
151; CHECK-LABEL: vclz32:
152; CHECK:       @ %bb.0:
153; CHECK-NEXT:    vldr d16, [r0]
154; CHECK-NEXT:    vclz.i32 d16, d16
155; CHECK-NEXT:    vmov r0, r1, d16
156; CHECK-NEXT:    mov pc, lr
157	%tmp1 = load <2 x i32>, ptr %A
158	%tmp2 = call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> %tmp1, i1 0)
159	ret <2 x i32> %tmp2
160}
161
162define <16 x i8> @vclzQ8(ptr %A) nounwind {
163; CHECK-LABEL: vclzQ8:
164; CHECK:       @ %bb.0:
165; CHECK-NEXT:    vld1.64 {d16, d17}, [r0]
166; CHECK-NEXT:    vclz.i8 q8, q8
167; CHECK-NEXT:    vmov r0, r1, d16
168; CHECK-NEXT:    vmov r2, r3, d17
169; CHECK-NEXT:    mov pc, lr
170	%tmp1 = load <16 x i8>, ptr %A
171	%tmp2 = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %tmp1, i1 0)
172	ret <16 x i8> %tmp2
173}
174
175define <8 x i16> @vclzQ16(ptr %A) nounwind {
176; CHECK-LABEL: vclzQ16:
177; CHECK:       @ %bb.0:
178; CHECK-NEXT:    vld1.64 {d16, d17}, [r0]
179; CHECK-NEXT:    vclz.i16 q8, q8
180; CHECK-NEXT:    vmov r0, r1, d16
181; CHECK-NEXT:    vmov r2, r3, d17
182; CHECK-NEXT:    mov pc, lr
183	%tmp1 = load <8 x i16>, ptr %A
184	%tmp2 = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %tmp1, i1 0)
185	ret <8 x i16> %tmp2
186}
187
188define <4 x i32> @vclzQ32(ptr %A) nounwind {
189; CHECK-LABEL: vclzQ32:
190; CHECK:       @ %bb.0:
191; CHECK-NEXT:    vld1.64 {d16, d17}, [r0]
192; CHECK-NEXT:    vclz.i32 q8, q8
193; CHECK-NEXT:    vmov r0, r1, d16
194; CHECK-NEXT:    vmov r2, r3, d17
195; CHECK-NEXT:    mov pc, lr
196	%tmp1 = load <4 x i32>, ptr %A
197	%tmp2 = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %tmp1, i1 0)
198	ret <4 x i32> %tmp2
199}
200
201declare <8 x i8>  @llvm.ctlz.v8i8(<8 x i8>, i1) nounwind readnone
202declare <4 x i16> @llvm.ctlz.v4i16(<4 x i16>, i1) nounwind readnone
203declare <2 x i32> @llvm.ctlz.v2i32(<2 x i32>, i1) nounwind readnone
204
205declare <16 x i8> @llvm.ctlz.v16i8(<16 x i8>, i1) nounwind readnone
206declare <8 x i16> @llvm.ctlz.v8i16(<8 x i16>, i1) nounwind readnone
207declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32>, i1) nounwind readnone
208
209define <8 x i8> @vclss8(ptr %A) nounwind {
210; CHECK-LABEL: vclss8:
211; CHECK:       @ %bb.0:
212; CHECK-NEXT:    vldr d16, [r0]
213; CHECK-NEXT:    vcls.s8 d16, d16
214; CHECK-NEXT:    vmov r0, r1, d16
215; CHECK-NEXT:    mov pc, lr
216	%tmp1 = load <8 x i8>, ptr %A
217	%tmp2 = call <8 x i8> @llvm.arm.neon.vcls.v8i8(<8 x i8> %tmp1)
218	ret <8 x i8> %tmp2
219}
220
221define <4 x i16> @vclss16(ptr %A) nounwind {
222; CHECK-LABEL: vclss16:
223; CHECK:       @ %bb.0:
224; CHECK-NEXT:    vldr d16, [r0]
225; CHECK-NEXT:    vcls.s16 d16, d16
226; CHECK-NEXT:    vmov r0, r1, d16
227; CHECK-NEXT:    mov pc, lr
228	%tmp1 = load <4 x i16>, ptr %A
229	%tmp2 = call <4 x i16> @llvm.arm.neon.vcls.v4i16(<4 x i16> %tmp1)
230	ret <4 x i16> %tmp2
231}
232
233define <2 x i32> @vclss32(ptr %A) nounwind {
234; CHECK-LABEL: vclss32:
235; CHECK:       @ %bb.0:
236; CHECK-NEXT:    vldr d16, [r0]
237; CHECK-NEXT:    vcls.s32 d16, d16
238; CHECK-NEXT:    vmov r0, r1, d16
239; CHECK-NEXT:    mov pc, lr
240	%tmp1 = load <2 x i32>, ptr %A
241	%tmp2 = call <2 x i32> @llvm.arm.neon.vcls.v2i32(<2 x i32> %tmp1)
242	ret <2 x i32> %tmp2
243}
244
245define <16 x i8> @vclsQs8(ptr %A) nounwind {
246; CHECK-LABEL: vclsQs8:
247; CHECK:       @ %bb.0:
248; CHECK-NEXT:    vld1.64 {d16, d17}, [r0]
249; CHECK-NEXT:    vcls.s8 q8, q8
250; CHECK-NEXT:    vmov r0, r1, d16
251; CHECK-NEXT:    vmov r2, r3, d17
252; CHECK-NEXT:    mov pc, lr
253	%tmp1 = load <16 x i8>, ptr %A
254	%tmp2 = call <16 x i8> @llvm.arm.neon.vcls.v16i8(<16 x i8> %tmp1)
255	ret <16 x i8> %tmp2
256}
257
258define <8 x i16> @vclsQs16(ptr %A) nounwind {
259; CHECK-LABEL: vclsQs16:
260; CHECK:       @ %bb.0:
261; CHECK-NEXT:    vld1.64 {d16, d17}, [r0]
262; CHECK-NEXT:    vcls.s16 q8, q8
263; CHECK-NEXT:    vmov r0, r1, d16
264; CHECK-NEXT:    vmov r2, r3, d17
265; CHECK-NEXT:    mov pc, lr
266	%tmp1 = load <8 x i16>, ptr %A
267	%tmp2 = call <8 x i16> @llvm.arm.neon.vcls.v8i16(<8 x i16> %tmp1)
268	ret <8 x i16> %tmp2
269}
270
271define <4 x i32> @vclsQs32(ptr %A) nounwind {
272; CHECK-LABEL: vclsQs32:
273; CHECK:       @ %bb.0:
274; CHECK-NEXT:    vld1.64 {d16, d17}, [r0]
275; CHECK-NEXT:    vcls.s32 q8, q8
276; CHECK-NEXT:    vmov r0, r1, d16
277; CHECK-NEXT:    vmov r2, r3, d17
278; CHECK-NEXT:    mov pc, lr
279	%tmp1 = load <4 x i32>, ptr %A
280	%tmp2 = call <4 x i32> @llvm.arm.neon.vcls.v4i32(<4 x i32> %tmp1)
281	ret <4 x i32> %tmp2
282}
283
284define i32 @ctpop8(i8 %x) nounwind readnone {
285; CHECK-LABEL: ctpop8:
286; CHECK:       @ %bb.0:
287; CHECK-NEXT:    mov r1, #85
288; CHECK-NEXT:    and r1, r1, r0, lsr #1
289; CHECK-NEXT:    sub r0, r0, r1
290; CHECK-NEXT:    mov r1, #51
291; CHECK-NEXT:    and r1, r1, r0, lsr #2
292; CHECK-NEXT:    and r0, r0, #51
293; CHECK-NEXT:    add r0, r0, r1
294; CHECK-NEXT:    add r0, r0, r0, lsr #4
295; CHECK-NEXT:    and r0, r0, #15
296; CHECK-NEXT:    mov pc, lr
297  %count = tail call i8 @llvm.ctpop.i8(i8 %x)
298  %conv = zext i8 %count to i32
299  ret i32 %conv
300}
301
302define i32 @ctpop16(i16 %x) nounwind readnone {
303; CHECK-LABEL: ctpop16:
304; CHECK:       @ %bb.0:
305; CHECK-NEXT:    mov r1, #85
306; CHECK-NEXT:    orr r1, r1, #21760
307; CHECK-NEXT:    and r1, r1, r0, lsr #1
308; CHECK-NEXT:    sub r0, r0, r1
309; CHECK-NEXT:    mov r1, #51
310; CHECK-NEXT:    orr r1, r1, #13056
311; CHECK-NEXT:    and r2, r0, r1
312; CHECK-NEXT:    and r0, r1, r0, lsr #2
313; CHECK-NEXT:    add r0, r2, r0
314; CHECK-NEXT:    add r0, r0, r0, lsr #4
315; CHECK-NEXT:    and r1, r0, #3840
316; CHECK-NEXT:    and r0, r0, #15
317; CHECK-NEXT:    add r0, r0, r1, lsr #8
318; CHECK-NEXT:    mov pc, lr
319  %count = tail call i16 @llvm.ctpop.i16(i16 %x)
320  %conv = zext i16 %count to i32
321  ret i32 %conv
322}
323
324define i32 @ctpop32(i32 %x) nounwind readnone {
325; CHECK-LABEL: ctpop32:
326; CHECK:       @ %bb.0:
327; CHECK-NEXT:    ldr r1, .LCPI22_0
328; CHECK-NEXT:    ldr r2, .LCPI22_3
329; CHECK-NEXT:    and r1, r1, r0, lsr #1
330; CHECK-NEXT:    ldr r12, .LCPI22_1
331; CHECK-NEXT:    sub r0, r0, r1
332; CHECK-NEXT:    ldr r3, .LCPI22_2
333; CHECK-NEXT:    and r1, r0, r2
334; CHECK-NEXT:    and r0, r2, r0, lsr #2
335; CHECK-NEXT:    add r0, r1, r0
336; CHECK-NEXT:    add r0, r0, r0, lsr #4
337; CHECK-NEXT:    and r0, r0, r12
338; CHECK-NEXT:    mul r1, r0, r3
339; CHECK-NEXT:    lsr r0, r1, #24
340; CHECK-NEXT:    mov pc, lr
341; CHECK-NEXT:    .p2align 2
342; CHECK-NEXT:  @ %bb.1:
343; CHECK-NEXT:  .LCPI22_0:
344; CHECK-NEXT:    .long 1431655765 @ 0x55555555
345; CHECK-NEXT:  .LCPI22_1:
346; CHECK-NEXT:    .long 252645135 @ 0xf0f0f0f
347; CHECK-NEXT:  .LCPI22_2:
348; CHECK-NEXT:    .long 16843009 @ 0x1010101
349; CHECK-NEXT:  .LCPI22_3:
350; CHECK-NEXT:    .long 858993459 @ 0x33333333
351  %count = tail call i32 @llvm.ctpop.i32(i32 %x)
352  ret i32 %count
353}
354
355define i32 @ctpop64(i64 %x) nounwind readnone {
356; CHECK-LABEL: ctpop64:
357; CHECK:       @ %bb.0:
358; CHECK-NEXT:    .save {r4, lr}
359; CHECK-NEXT:    push {r4, lr}
360; CHECK-NEXT:    ldr r2, .LCPI23_0
361; CHECK-NEXT:    ldr r3, .LCPI23_3
362; CHECK-NEXT:    and r4, r2, r0, lsr #1
363; CHECK-NEXT:    and r2, r2, r1, lsr #1
364; CHECK-NEXT:    sub r0, r0, r4
365; CHECK-NEXT:    sub r1, r1, r2
366; CHECK-NEXT:    and r4, r0, r3
367; CHECK-NEXT:    and r2, r1, r3
368; CHECK-NEXT:    and r0, r3, r0, lsr #2
369; CHECK-NEXT:    and r1, r3, r1, lsr #2
370; CHECK-NEXT:    add r0, r4, r0
371; CHECK-NEXT:    ldr lr, .LCPI23_1
372; CHECK-NEXT:    add r1, r2, r1
373; CHECK-NEXT:    ldr r12, .LCPI23_2
374; CHECK-NEXT:    add r0, r0, r0, lsr #4
375; CHECK-NEXT:    and r0, r0, lr
376; CHECK-NEXT:    add r1, r1, r1, lsr #4
377; CHECK-NEXT:    mul r2, r0, r12
378; CHECK-NEXT:    and r0, r1, lr
379; CHECK-NEXT:    mul r1, r0, r12
380; CHECK-NEXT:    lsr r0, r2, #24
381; CHECK-NEXT:    add r0, r0, r1, lsr #24
382; CHECK-NEXT:    pop {r4, lr}
383; CHECK-NEXT:    mov pc, lr
384; CHECK-NEXT:    .p2align 2
385; CHECK-NEXT:  @ %bb.1:
386; CHECK-NEXT:  .LCPI23_0:
387; CHECK-NEXT:    .long 1431655765 @ 0x55555555
388; CHECK-NEXT:  .LCPI23_1:
389; CHECK-NEXT:    .long 252645135 @ 0xf0f0f0f
390; CHECK-NEXT:  .LCPI23_2:
391; CHECK-NEXT:    .long 16843009 @ 0x1010101
392; CHECK-NEXT:  .LCPI23_3:
393; CHECK-NEXT:    .long 858993459 @ 0x33333333
394  %count = tail call i64 @llvm.ctpop.i64(i64 %x)
395  %conv = trunc i64 %count to i32
396  ret i32 %conv
397}
398
399define i32 @ctpop_eq_one(i64 %x) nounwind readnone {
400; CHECK-LABEL: ctpop_eq_one:
401; CHECK:       @ %bb.0:
402; CHECK-NEXT:    subs r2, r0, #1
403; CHECK-NEXT:    sbc r3, r1, #0
404; CHECK-NEXT:    eor r12, r1, r3
405; CHECK-NEXT:    eor r1, r0, r2
406; CHECK-NEXT:    subs r1, r2, r1
407; CHECK-NEXT:    mov r0, #0
408; CHECK-NEXT:    sbcs r1, r3, r12
409; CHECK-NEXT:    movlo r0, #1
410; CHECK-NEXT:    mov pc, lr
411  %count = tail call i64 @llvm.ctpop.i64(i64 %x)
412  %cmp = icmp eq i64 %count, 1
413  %conv = zext i1 %cmp to i32
414  ret i32 %conv
415}
416
417declare i8 @llvm.ctpop.i8(i8) nounwind readnone
418declare i16 @llvm.ctpop.i16(i16) nounwind readnone
419declare i32 @llvm.ctpop.i32(i32) nounwind readnone
420declare i64 @llvm.ctpop.i64(i64) nounwind readnone
421
422declare <8 x i8>  @llvm.arm.neon.vcls.v8i8(<8 x i8>) nounwind readnone
423declare <4 x i16> @llvm.arm.neon.vcls.v4i16(<4 x i16>) nounwind readnone
424declare <2 x i32> @llvm.arm.neon.vcls.v2i32(<2 x i32>) nounwind readnone
425
426declare <16 x i8> @llvm.arm.neon.vcls.v16i8(<16 x i8>) nounwind readnone
427declare <8 x i16> @llvm.arm.neon.vcls.v8i16(<8 x i16>) nounwind readnone
428declare <4 x i32> @llvm.arm.neon.vcls.v4i32(<4 x i32>) nounwind readnone
429