1# RUN: llc -o /dev/null %s -mtriple=arm-eabi -mcpu=swift -run-pass machine-scheduler -enable-misched -verify-misched \ 2# RUN: -debug-only=machine-scheduler 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK_SWIFT 3# RUN: llc -o /dev/null %s -mtriple=arm-eabi -mcpu=cortex-a9 -run-pass machine-scheduler -enable-misched -verify-misched \ 4# RUN: -debug-only=machine-scheduler 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK_A9 5# RUN: llc -o /dev/null %s -mtriple=arm-eabi -mcpu=cortex-r52 -run-pass machine-scheduler -enable-misched -verify-misched \ 6# RUN: -debug-only=machine-scheduler 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK_R52 7# RUN: llc -o /dev/null %s -mtriple=arm-eabi -mcpu=cortex-r52plus -run-pass machine-scheduler -enable-misched -verify-misched \ 8# RUN: -debug-only=machine-scheduler 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK_R52 9# REQUIRES: asserts 10--- | 11 ; ModuleID = 'foo.ll' 12 source_filename = "foo.ll" 13 target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 14 target triple = "arm---eabi" 15 16 define i64 @foo(i16 signext %a, i16 signext %b) { 17 entry: 18 %d = mul nsw i16 %a, %a 19 %e = mul nsw i16 %b, %b 20 %f = add nuw nsw i16 %e, %d 21 %c = zext i16 %f to i32 22 %mul8 = mul nsw i32 %c, %c 23 %mul9 = mul nsw i32 %mul8, %mul8 24 %add10 = add nuw nsw i32 %mul9, %mul8 25 %conv1130 = zext i32 %add10 to i64 26 %mul12 = mul nuw nsw i64 %conv1130, %conv1130 27 %mul13 = mul nsw i64 %mul12, %mul12 28 %add14 = add nuw nsw i64 %mul13, %mul12 29 ret i64 %add14 30 } 31 32# CHECK: ********** MI Scheduling ********** 33# CHECK: SU(2): %2:gpr = SMULBB %1:gpr, %1:gpr, 14, $noreg 34# CHECK_A9: Latency : 2 35# CHECK_SWIFT: Latency : 4 36# CHECK_R52: Latency : 4 37# 38# CHECK: SU(3): %3:gprnopc = SMLABB %0:gprnopc, %0:gprnopc, %2:gpr, 14, $noreg 39# CHECK_A9: Latency : 2 40# CHECK_SWIFT: Latency : 4 41# CHECK_R52: Latency : 4 42# 43# CHECK: SU(4): %4:gprnopc = UXTH %3:gprnopc, 0, 14, $noreg 44# CHECK_A9: Latency : 1 45# CHECK_SWIFT: Latency : 1 46# CHECK_R52: Latency : 3 47# 48# CHECK: SU(5): %5:gprnopc = MUL %4:gprnopc, %4:gprnopc, 14, $noreg, $noreg 49# CHECK_A9: Latency : 2 50# CHECK_SWIFT: Latency : 4 51# CHECK_R52: Latency : 4 52# 53# CHECK: SU(6): %6:gprnopc = MLA %5:gprnopc, %5:gprnopc, %5:gprnopc, 14, $noreg, $noreg 54# CHECK_A9: Latency : 2 55# CHECK_SWIFT: Latency : 4 56# CHECK_R52: Latency : 4 57# 58# CHECK: SU(7): %7:gprnopc, %8:gprnopc = UMULL %6:gprnopc, %6:gprnopc, 14, $noreg, $noreg 59# CHECK_A9: Latency : 3 60# CHECK_SWIFT: Latency : 5 61# CHECK_R52: Latency : 4 62# 63# CHECK: SU(11): %13:gpr, %14:gprnopc = UMLAL %6:gprnopc, %6:gprnopc, %13:gpr(tied-def 0), %14:gprnopc(tied-def 1), 14, $noreg, $noreg 64# CHECK_SWIFT: Latency : 7 65# CHECK_A9: Latency : 3 66# CHECK_R52: Latency : 4 67# CHECK: ** ScheduleDAGMILive::schedule picking next node 68... 69--- 70name: foo 71alignment: 4 72exposesReturnsTwice: false 73legalized: false 74regBankSelected: false 75selected: false 76tracksRegLiveness: true 77registers: 78 - { id: 0, class: gprnopc } 79 - { id: 1, class: gpr } 80 - { id: 2, class: gpr } 81 - { id: 3, class: gprnopc } 82 - { id: 4, class: gprnopc } 83 - { id: 5, class: gprnopc } 84 - { id: 6, class: gprnopc } 85 - { id: 7, class: gprnopc } 86 - { id: 8, class: gprnopc } 87 - { id: 9, class: gpr } 88 - { id: 10, class: gprnopc } 89 - { id: 11, class: gprnopc } 90 - { id: 12, class: gprnopc } 91 - { id: 13, class: gpr } 92 - { id: 14, class: gprnopc } 93liveins: 94 - { reg: '$r0', virtual-reg: '%0' } 95 - { reg: '$r1', virtual-reg: '%1' } 96frameInfo: 97 isFrameAddressTaken: false 98 isReturnAddressTaken: false 99 hasStackMap: false 100 hasPatchPoint: false 101 stackSize: 0 102 offsetAdjustment: 0 103 maxAlignment: 0 104 adjustsStack: false 105 hasCalls: false 106 maxCallFrameSize: 0 107 hasOpaqueSPAdjustment: false 108 hasVAStart: false 109 hasMustTailInVarArgFunc: false 110body: | 111 bb.0.entry: 112 liveins: $r0, $r1 113 114 %1 = COPY $r1 115 %0 = COPY $r0 116 %2 = SMULBB %1, %1, 14, $noreg 117 %3 = SMLABB %0, %0, %2, 14, $noreg 118 %4 = UXTH %3, 0, 14, $noreg 119 %5 = MUL %4, %4, 14, $noreg, $noreg 120 %6 = MLA %5, %5, %5, 14, $noreg, $noreg 121 %7, %8 = UMULL %6, %6, 14, $noreg, $noreg 122 %13, %10 = UMULL %7, %7, 14, $noreg, $noreg 123 %11 = MLA %7, %8, %10, 14, $noreg, $noreg 124 %14 = MLA %7, %8, %11, 14, $noreg, $noreg 125 %13, %14 = UMLAL %6, %6, %13, %14, 14, $noreg, $noreg 126 $r0 = COPY %13 127 $r1 = COPY %14 128 BX_RET 14, $noreg, implicit $r0, implicit $r1 129 130... 131