1; REQUIRES: asserts 2; RUN: llc < %s -mtriple=arm-eabi -mcpu=cortex-a9 -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > \ 3; RUN: /dev/null | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK_A9 4; RUN: llc < %s -mtriple=arm-eabi -mcpu=swift -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > \ 5; RUN: /dev/null | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK_SWIFT 6; RUN: llc < %s -mtriple=arm-eabi -mcpu=cortex-r52 -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > \ 7; RUN: /dev/null | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK_R52 8; RUN: llc < %s -mtriple=arm-eabi -mcpu=cortex-r52plus -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > \ 9; RUN: /dev/null | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK_R52 10; 11; Check the latency of instructions for processors with sched-models 12; 13; Function Attrs: norecurse nounwind readnone 14define i32 @foo(float %a, float %b, float %c, i32 %d) local_unnamed_addr #0 { 15entry: 16; 17; CHECK: ********** MI Scheduling ********** 18; CHECK_A9: VADDS 19; CHECK_SWIFT: VADDfd 20; CHECK_R52: VADDS 21; CHECK_A9: Latency : 5 22; CHECK_SWIFT: Latency : 4 23; CHECK_R52: Latency : 6 24; 25; CHECK_A9: VMULS 26; CHECK_SWIFT: VMULfd 27; CHECK_R52: VMULS 28; CHECK_SWIFT: Latency : 4 29; CHECK_A9: Latency : 6 30; CHECK_R52: Latency : 6 31; 32; CHECK: VDIVS 33; CHECK_SWIFT: Latency : 17 34; CHECK_A9: Latency : 16 35; CHECK_R52: Latency : 7 36; 37; CHECK: VCVTDS 38; CHECK_SWIFT: Latency : 4 39; CHECK_A9: Latency : 5 40; CHECK_R52: Latency : 6 41; 42; CHECK: VADDD 43; CHECK_SWIFT: Latency : 6 44; CHECK_A9: Latency : 5 45; CHECK_R52: Latency : 6 46; 47; CHECK: VMULD 48; CHECK_SWIFT: Latency : 6 49; CHECK_A9: Latency : 7 50; CHECK_R52: Latency : 6 51; 52; CHECK: VDIVD 53; CHECK_SWIFT: Latency : 32 54; CHECK_A9: Latency : 26 55; CHECK_R52: Latency : 17 56; 57; CHECK: VTOSIZD 58; CHECK_SWIFT: Latency : 4 59; CHECK_A9: Latency : 5 60; CHECK_R52: Latency : 6 61; 62 %add = fadd float %a, %b 63 %mul = fmul float %add, %add 64 %div = fdiv float %mul, %b 65 %conv1 = fpext float %div to double 66 %add3 = fadd double %conv1, %conv1 67 %mul4 = fmul double %add3, %add3 68 %div5 = fdiv double %mul4, %conv1 69 %conv6 = fptosi double %div5 to i32 70 ret i32 %conv6 71} 72