xref: /llvm-project/llvm/test/CodeGen/ARM/load_store_opt_kill.mir (revision 7efabe5c7de46fe190638741c6ee81ae13255e38) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=armv7-none-eabi -verify-machineinstrs -run-pass arm-ldst-opt %s -o - | FileCheck %s
3---
4name:            f
5# Make sure the load into $r0 doesn't clobber the base register before the second load uses it.
6body:             |
7  bb.0:
8    liveins: $r0, $r3
9    ; CHECK-LABEL: name: f
10    ; CHECK: $r3 = LDRi12 $r0, 12, 14 /* CC::al */, $noreg
11    ; CHECK: $r0 = LDRi12 $r0, 8, 14 /* CC::al */, $noreg
12    $r0, $r3 = LDRD $r0, $noreg, 8, 14, $noreg
13...
14