xref: /llvm-project/llvm/test/CodeGen/ARM/ldr_ext.ll (revision bed1c7f061aa12417aa081e334afdba45767b938)
1; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s
2
3define i32 @test1(ptr %t1) nounwind {
4; CHECK: ldrb
5    %tmp.u = load i8, ptr %t1
6    %tmp1.s = zext i8 %tmp.u to i32
7    ret i32 %tmp1.s
8}
9
10define i32 @test2(ptr %t1) nounwind {
11; CHECK: ldrh
12    %tmp.u = load i16, ptr %t1
13    %tmp1.s = zext i16 %tmp.u to i32
14    ret i32 %tmp1.s
15}
16
17define i32 @test3(ptr %t0) nounwind {
18; CHECK: ldrsb
19    %tmp.s = load i8, ptr %t0
20    %tmp1.s = sext i8 %tmp.s to i32
21    ret i32 %tmp1.s
22}
23
24define i32 @test4(ptr %t0) nounwind {
25; CHECK: ldrsh
26    %tmp.s = load i16, ptr %t0
27    %tmp1.s = sext i16 %tmp.s to i32
28    ret i32 %tmp1.s
29}
30
31define i32 @test5() nounwind {
32; CHECK: mov r0, #0
33; CHECK: ldrsh
34    %tmp.s = load i16, ptr null
35    %tmp1.s = sext i16 %tmp.s to i32
36    ret i32 %tmp1.s
37}
38