1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=arm-eabi | FileCheck %s -check-prefix=LE 3; RUN: llc < %s -mtriple=armeb-eabi | FileCheck %s -check-prefix=BE 4 5define void @i24_or(ptr %a) { 6; LE-LABEL: i24_or: 7; LE: @ %bb.0: 8; LE-NEXT: ldrh r1, [r0] 9; LE-NEXT: orr r1, r1, #384 10; LE-NEXT: strh r1, [r0] 11; LE-NEXT: mov pc, lr 12; 13; BE-LABEL: i24_or: 14; BE: @ %bb.0: 15; BE-NEXT: ldrh r1, [r0] 16; BE-NEXT: ldrb r2, [r0, #2] 17; BE-NEXT: orr r1, r2, r1, lsl #8 18; BE-NEXT: orr r1, r1, #384 19; BE-NEXT: strb r1, [r0, #2] 20; BE-NEXT: lsr r1, r1, #8 21; BE-NEXT: strh r1, [r0] 22; BE-NEXT: mov pc, lr 23 %aa = load i24, ptr %a, align 1 24 %b = or i24 %aa, 384 25 store i24 %b, ptr %a, align 1 26 ret void 27} 28 29define void @i24_and_or(ptr %a) { 30; LE-LABEL: i24_and_or: 31; LE: @ %bb.0: 32; LE-NEXT: ldrh r1, [r0] 33; LE-NEXT: orr r1, r1, #384 34; LE-NEXT: bic r1, r1, #127 35; LE-NEXT: strh r1, [r0] 36; LE-NEXT: mov pc, lr 37; 38; BE-LABEL: i24_and_or: 39; BE: @ %bb.0: 40; BE-NEXT: mov r1, #128 41; BE-NEXT: strb r1, [r0, #2] 42; BE-NEXT: ldrh r1, [r0] 43; BE-NEXT: orr r1, r1, #1 44; BE-NEXT: strh r1, [r0] 45; BE-NEXT: mov pc, lr 46 %b = load i24, ptr %a, align 1 47 %c = and i24 %b, -128 48 %d = or i24 %c, 384 49 store i24 %d, ptr %a, align 1 50 ret void 51} 52 53define void @i24_insert_bit(ptr %a, i1 zeroext %bit) { 54; LE-LABEL: i24_insert_bit: 55; LE: @ %bb.0: 56; LE-NEXT: mov r3, #255 57; LE-NEXT: ldrh r2, [r0] 58; LE-NEXT: orr r3, r3, #57088 59; LE-NEXT: and r2, r2, r3 60; LE-NEXT: orr r1, r2, r1, lsl #13 61; LE-NEXT: strh r1, [r0] 62; LE-NEXT: mov pc, lr 63; 64; BE-LABEL: i24_insert_bit: 65; BE: @ %bb.0: 66; BE-NEXT: ldrh r2, [r0] 67; BE-NEXT: mov r3, #57088 68; BE-NEXT: orr r3, r3, #16711680 69; BE-NEXT: and r2, r3, r2, lsl #8 70; BE-NEXT: orr r1, r2, r1, lsl #13 71; BE-NEXT: lsr r1, r1, #8 72; BE-NEXT: strh r1, [r0] 73; BE-NEXT: mov pc, lr 74 %extbit = zext i1 %bit to i24 75 %b = load i24, ptr %a, align 1 76 %extbit.shl = shl nuw nsw i24 %extbit, 13 77 %c = and i24 %b, -8193 78 %d = or i24 %c, %extbit.shl 79 store i24 %d, ptr %a, align 1 80 ret void 81} 82 83define void @i56_or(ptr %a) { 84; LE-LABEL: i56_or: 85; LE: @ %bb.0: 86; LE-NEXT: ldr r1, [r0] 87; LE-NEXT: orr r1, r1, #384 88; LE-NEXT: str r1, [r0] 89; LE-NEXT: mov pc, lr 90; 91; BE-LABEL: i56_or: 92; BE: @ %bb.0: 93; BE-NEXT: mov r1, r0 94; BE-NEXT: ldr r0, [r0] 95; BE-NEXT: ldrh r2, [r1, #4]! 96; BE-NEXT: ldrb r3, [r1, #2] 97; BE-NEXT: orr r2, r3, r2, lsl #8 98; BE-NEXT: orr r0, r2, r0, lsl #24 99; BE-NEXT: orr r0, r0, #384 100; BE-NEXT: strb r0, [r1, #2] 101; BE-NEXT: lsr r0, r0, #8 102; BE-NEXT: strh r0, [r1] 103; BE-NEXT: mov pc, lr 104 %aa = load i56, ptr %a 105 %b = or i56 %aa, 384 106 store i56 %b, ptr %a 107 ret void 108} 109 110define void @i56_and_or(ptr %a) { 111; LE-LABEL: i56_and_or: 112; LE: @ %bb.0: 113; LE-NEXT: ldr r1, [r0] 114; LE-NEXT: orr r1, r1, #384 115; LE-NEXT: bic r1, r1, #127 116; LE-NEXT: str r1, [r0] 117; LE-NEXT: mov pc, lr 118; 119; BE-LABEL: i56_and_or: 120; BE: @ %bb.0: 121; BE-NEXT: ldrh r1, [r0, #4]! 122; BE-NEXT: mov r2, #128 123; BE-NEXT: orr r1, r1, #1 124; BE-NEXT: strb r2, [r0, #2] 125; BE-NEXT: strh r1, [r0] 126; BE-NEXT: mov pc, lr 127 128 %b = load i56, ptr %a, align 1 129 %c = and i56 %b, -128 130 %d = or i56 %c, 384 131 store i56 %d, ptr %a, align 1 132 ret void 133} 134 135define void @i56_insert_bit(ptr %a, i1 zeroext %bit) { 136; LE-LABEL: i56_insert_bit: 137; LE: @ %bb.0: 138; LE-NEXT: ldr r2, [r0] 139; LE-NEXT: bic r2, r2, #8192 140; LE-NEXT: orr r1, r2, r1, lsl #13 141; LE-NEXT: str r1, [r0] 142; LE-NEXT: mov pc, lr 143; 144; BE-LABEL: i56_insert_bit: 145; BE: @ %bb.0: 146; BE-NEXT: ldrh r2, [r0, #4]! 147; BE-NEXT: mov r3, #57088 148; BE-NEXT: orr r3, r3, #16711680 149; BE-NEXT: and r2, r3, r2, lsl #8 150; BE-NEXT: orr r1, r2, r1, lsl #13 151; BE-NEXT: lsr r1, r1, #8 152; BE-NEXT: strh r1, [r0] 153; BE-NEXT: mov pc, lr 154 %extbit = zext i1 %bit to i56 155 %b = load i56, ptr %a, align 1 156 %extbit.shl = shl nuw nsw i56 %extbit, 13 157 %c = and i56 %b, -8193 158 %d = or i56 %c, %extbit.shl 159 store i56 %d, ptr %a, align 1 160 ret void 161} 162 163