xref: /llvm-project/llvm/test/CodeGen/ARM/ifcvt1.ll (revision e0ed0333f0fed2e73f805afd58b61176a87aa3ad)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s -check-prefix=A8
3; RUN: llc -mtriple=arm-eabi -mcpu=swift %s -o - | FileCheck %s -check-prefix=SWIFT
4
5define i32 @t1(i32 %a, i32 %b) {
6; A8-LABEL: t1:
7; A8:       @ %bb.0: @ %common.ret
8; A8-NEXT:    mov r2, #1
9; A8-NEXT:    cmp r0, #0
10; A8-NEXT:    mvneq r2, #0
11; A8-NEXT:    add r0, r1, r2
12; A8-NEXT:    bx lr
13;
14; SWIFT-LABEL: t1:
15; SWIFT:       @ %bb.0: @ %common.ret
16; SWIFT-NEXT:    cmp r0, #0
17; SWIFT-NEXT:    mov r0, #1
18; SWIFT-NEXT:    mvneq r0, #0
19; SWIFT-NEXT:    add r0, r1, r0
20; SWIFT-NEXT:    bx lr
21	%tmp2 = icmp eq i32 %a, 0
22	br i1 %tmp2, label %cond_false, label %cond_true
23
24cond_true:
25	%tmp5 = add i32 %b, 1
26	ret i32 %tmp5
27
28cond_false:
29	%tmp7 = add i32 %b, -1
30	ret i32 %tmp7
31}
32