1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=armv7 %s -o - | FileCheck %s 3 4; Optimize expanded SRL/SHL used as an input of 5; SETCC comparing it with zero by removing rotation. 6; 7; See https://bugs.llvm.org/show_bug.cgi?id=50197 8define i64 @opt_setcc_lt_power_of_2(i64 %a) nounwind { 9; CHECK-LABEL: opt_setcc_lt_power_of_2: 10; CHECK: @ %bb.0: 11; CHECK-NEXT: .LBB0_1: @ %loop 12; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 13; CHECK-NEXT: adds r0, r0, #1 14; CHECK-NEXT: adc r1, r1, #0 15; CHECK-NEXT: orrs r2, r1, r0, lsr #16 16; CHECK-NEXT: bne .LBB0_1 17; CHECK-NEXT: @ %bb.2: @ %exit 18; CHECK-NEXT: bx lr 19 br label %loop 20 21loop: 22 %phi.a = phi i64 [ %a, %0 ], [ %inc, %loop ] 23 %inc = add i64 %phi.a, 1 24 %cmp = icmp ult i64 %inc, 65536 25 br i1 %cmp, label %exit, label %loop 26 27exit: 28 ret i64 %inc 29} 30 31define i1 @opt_setcc_srl_eq_zero(i64 %a) nounwind { 32; CHECK-LABEL: opt_setcc_srl_eq_zero: 33; CHECK: @ %bb.0: 34; CHECK-NEXT: orr r0, r1, r0, lsr #17 35; CHECK-NEXT: clz r0, r0 36; CHECK-NEXT: lsr r0, r0, #5 37; CHECK-NEXT: bx lr 38 %srl = lshr i64 %a, 17 39 %cmp = icmp eq i64 %srl, 0 40 ret i1 %cmp 41} 42 43define i1 @opt_setcc_srl_ne_zero(i64 %a) nounwind { 44; CHECK-LABEL: opt_setcc_srl_ne_zero: 45; CHECK: @ %bb.0: 46; CHECK-NEXT: orrs r0, r1, r0, lsr #17 47; CHECK-NEXT: movwne r0, #1 48; CHECK-NEXT: bx lr 49 %srl = lshr i64 %a, 17 50 %cmp = icmp ne i64 %srl, 0 51 ret i1 %cmp 52} 53 54define i1 @opt_setcc_shl_eq_zero(i64 %a) nounwind { 55; CHECK-LABEL: opt_setcc_shl_eq_zero: 56; CHECK: @ %bb.0: 57; CHECK-NEXT: orr r0, r0, r1, lsl #17 58; CHECK-NEXT: clz r0, r0 59; CHECK-NEXT: lsr r0, r0, #5 60; CHECK-NEXT: bx lr 61 %shl = shl i64 %a, 17 62 %cmp = icmp eq i64 %shl, 0 63 ret i1 %cmp 64} 65 66define i1 @opt_setcc_shl_ne_zero(i64 %a) nounwind { 67; CHECK-LABEL: opt_setcc_shl_ne_zero: 68; CHECK: @ %bb.0: 69; CHECK-NEXT: orrs r0, r0, r1, lsl #17 70; CHECK-NEXT: movwne r0, #1 71; CHECK-NEXT: bx lr 72 %shl = shl i64 %a, 17 73 %cmp = icmp ne i64 %shl, 0 74 ret i1 %cmp 75} 76 77; Negative test: optimization should not be applied if shift has multiple users. 78define i1 @opt_setcc_shl_eq_zero_multiple_shl_users(i64 %a) nounwind { 79; CHECK-LABEL: opt_setcc_shl_eq_zero_multiple_shl_users: 80; CHECK: @ %bb.0: 81; CHECK-NEXT: push {r4, r5, r11, lr} 82; CHECK-NEXT: mov r4, r0 83; CHECK-NEXT: lsl r0, r1, #17 84; CHECK-NEXT: orr r5, r0, r4, lsr #15 85; CHECK-NEXT: lsl r0, r4, #17 86; CHECK-NEXT: mov r1, r5 87; CHECK-NEXT: bl use 88; CHECK-NEXT: orr r0, r5, r4, lsl #17 89; CHECK-NEXT: clz r0, r0 90; CHECK-NEXT: lsr r0, r0, #5 91; CHECK-NEXT: pop {r4, r5, r11, pc} 92 %shl = shl i64 %a, 17 93 %cmp = icmp eq i64 %shl, 0 94 call void @use(i64 %shl) 95 ret i1 %cmp 96} 97 98; Check that optimization is applied to DAG having appropriate shape 99; even if there were no actual shift's expansion. 100define i1 @opt_setcc_expanded_shl_correct_shifts(i32 %a, i32 %b) nounwind { 101; CHECK-LABEL: opt_setcc_expanded_shl_correct_shifts: 102; CHECK: @ %bb.0: 103; CHECK-NEXT: orr r0, r1, r0, lsl #17 104; CHECK-NEXT: clz r0, r0 105; CHECK-NEXT: lsr r0, r0, #5 106; CHECK-NEXT: bx lr 107 %shl.a = shl i32 %a, 17 108 %srl.b = lshr i32 %b, 15 109 %or.0 = or i32 %shl.a, %srl.b 110 %shl.b = shl i32 %b, 17 111 %or.1 = or i32 %or.0, %shl.b 112 %cmp = icmp eq i32 %or.1, 0 113 ret i1 %cmp 114} 115 116; Negative test: optimization should not be applied as 117; constants used in shifts do not match. 118define i1 @opt_setcc_expanded_shl_wrong_shifts(i32 %a, i32 %b) nounwind { 119; CHECK-LABEL: opt_setcc_expanded_shl_wrong_shifts: 120; CHECK: @ %bb.0: 121; CHECK-NEXT: lsl r0, r0, #17 122; CHECK-NEXT: orr r0, r0, r1, lsr #15 123; CHECK-NEXT: orr r0, r0, r1, lsl #18 124; CHECK-NEXT: clz r0, r0 125; CHECK-NEXT: lsr r0, r0, #5 126; CHECK-NEXT: bx lr 127 %shl.a = shl i32 %a, 17 128 %srl.b = lshr i32 %b, 15 129 %or.0 = or i32 %shl.a, %srl.b 130 %shl.b = shl i32 %b, 18 131 %or.1 = or i32 %or.0, %shl.b 132 %cmp = icmp eq i32 %or.1, 0 133 ret i1 %cmp 134} 135 136define i1 @opt_setcc_shl_ne_zero_i128(i128 %a) nounwind { 137; CHECK-LABEL: opt_setcc_shl_ne_zero_i128: 138; CHECK: @ %bb.0: 139; CHECK-NEXT: orr r0, r2, r0 140; CHECK-NEXT: orr r0, r1, r0 141; CHECK-NEXT: orr r1, r0, r3 142; CHECK-NEXT: lsl r1, r1, #17 143; CHECK-NEXT: orrs r0, r1, r0, lsr #15 144; CHECK-NEXT: movwne r0, #1 145; CHECK-NEXT: bx lr 146 %shl = shl i128 %a, 17 147 %cmp = icmp ne i128 %shl, 0 148 ret i1 %cmp 149} 150 151declare void @use(i64 %a) 152