1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=armv7a-none-eabihf -mattr=+neon | FileCheck %s --check-prefixes=CHECK,CHECK-NEON 3; RUN: llc < %s -mtriple=armv8a-none-eabihf -mattr=+neon,+fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-FP16 4 5; i32 saturate 6 7define <2 x i32> @stest_f64i32(<2 x double> %x) { 8; CHECK-LABEL: stest_f64i32: 9; CHECK: @ %bb.0: @ %entry 10; CHECK-NEXT: .save {r4, r5, r11, lr} 11; CHECK-NEXT: push {r4, r5, r11, lr} 12; CHECK-NEXT: .vsave {d8, d9} 13; CHECK-NEXT: vpush {d8, d9} 14; CHECK-NEXT: vorr q4, q0, q0 15; CHECK-NEXT: vmov r0, r1, d9 16; CHECK-NEXT: bl __aeabi_d2lz 17; CHECK-NEXT: mov r4, r0 18; CHECK-NEXT: mov r5, r1 19; CHECK-NEXT: vmov r0, r1, d8 20; CHECK-NEXT: vmov.32 d9[0], r4 21; CHECK-NEXT: bl __aeabi_d2lz 22; CHECK-NEXT: vmov.32 d8[0], r0 23; CHECK-NEXT: mvn r3, #-2147483648 24; CHECK-NEXT: subs r4, r4, r3 25; CHECK-NEXT: adr r2, .LCPI0_0 26; CHECK-NEXT: vmov.32 d9[1], r5 27; CHECK-NEXT: sbcs r5, r5, #0 28; CHECK-NEXT: mov r5, #0 29; CHECK-NEXT: mvn r4, #0 30; CHECK-NEXT: movwlt r5, #1 31; CHECK-NEXT: cmp r5, #0 32; CHECK-NEXT: mvnne r5, #0 33; CHECK-NEXT: subs r0, r0, r3 34; CHECK-NEXT: sbcs r0, r1, #0 35; CHECK-NEXT: vmov.32 d8[1], r1 36; CHECK-NEXT: mov r0, #0 37; CHECK-NEXT: vmov.i32 q10, #0x80000000 38; CHECK-NEXT: movwlt r0, #1 39; CHECK-NEXT: cmp r0, #0 40; CHECK-NEXT: vdup.32 d19, r5 41; CHECK-NEXT: mvnne r0, #0 42; CHECK-NEXT: vld1.64 {d16, d17}, [r2:128] 43; CHECK-NEXT: mov r2, #0 44; CHECK-NEXT: vdup.32 d18, r0 45; CHECK-NEXT: vbit q8, q4, q9 46; CHECK-NEXT: vmov r0, r1, d17 47; CHECK-NEXT: vmov r3, r5, d16 48; CHECK-NEXT: rsbs r0, r0, #-2147483648 49; CHECK-NEXT: sbcs r0, r4, r1 50; CHECK-NEXT: mov r0, #0 51; CHECK-NEXT: movwlt r0, #1 52; CHECK-NEXT: cmp r0, #0 53; CHECK-NEXT: mvnne r0, #0 54; CHECK-NEXT: rsbs r1, r3, #-2147483648 55; CHECK-NEXT: sbcs r1, r4, r5 56; CHECK-NEXT: vdup.32 d19, r0 57; CHECK-NEXT: movwlt r2, #1 58; CHECK-NEXT: cmp r2, #0 59; CHECK-NEXT: mvnne r2, #0 60; CHECK-NEXT: vdup.32 d18, r2 61; CHECK-NEXT: vbif q8, q10, q9 62; CHECK-NEXT: vmovn.i64 d0, q8 63; CHECK-NEXT: vpop {d8, d9} 64; CHECK-NEXT: pop {r4, r5, r11, pc} 65; CHECK-NEXT: .p2align 4 66; CHECK-NEXT: @ %bb.1: 67; CHECK-NEXT: .LCPI0_0: 68; CHECK-NEXT: .long 2147483647 @ 0x7fffffff 69; CHECK-NEXT: .long 0 @ 0x0 70; CHECK-NEXT: .long 2147483647 @ 0x7fffffff 71; CHECK-NEXT: .long 0 @ 0x0 72entry: 73 %conv = fptosi <2 x double> %x to <2 x i64> 74 %0 = icmp slt <2 x i64> %conv, <i64 2147483647, i64 2147483647> 75 %spec.store.select = select <2 x i1> %0, <2 x i64> %conv, <2 x i64> <i64 2147483647, i64 2147483647> 76 %1 = icmp sgt <2 x i64> %spec.store.select, <i64 -2147483648, i64 -2147483648> 77 %spec.store.select7 = select <2 x i1> %1, <2 x i64> %spec.store.select, <2 x i64> <i64 -2147483648, i64 -2147483648> 78 %conv6 = trunc <2 x i64> %spec.store.select7 to <2 x i32> 79 ret <2 x i32> %conv6 80} 81 82define <2 x i32> @utest_f64i32(<2 x double> %x) { 83; CHECK-LABEL: utest_f64i32: 84; CHECK: @ %bb.0: @ %entry 85; CHECK-NEXT: .save {r4, r5, r11, lr} 86; CHECK-NEXT: push {r4, r5, r11, lr} 87; CHECK-NEXT: .vsave {d8, d9} 88; CHECK-NEXT: vpush {d8, d9} 89; CHECK-NEXT: vorr q4, q0, q0 90; CHECK-NEXT: vmov r0, r1, d9 91; CHECK-NEXT: bl __aeabi_d2ulz 92; CHECK-NEXT: mov r4, r0 93; CHECK-NEXT: mov r5, r1 94; CHECK-NEXT: vmov r0, r1, d8 95; CHECK-NEXT: vmov.32 d9[0], r4 96; CHECK-NEXT: bl __aeabi_d2ulz 97; CHECK-NEXT: mvn r3, #0 98; CHECK-NEXT: subs r4, r4, r3 99; CHECK-NEXT: sbcs r5, r5, #0 100; CHECK-NEXT: vmov.32 d8[0], r0 101; CHECK-NEXT: mov r5, #0 102; CHECK-NEXT: mov r2, #0 103; CHECK-NEXT: movwlo r5, #1 104; CHECK-NEXT: cmp r5, #0 105; CHECK-NEXT: mvnne r5, #0 106; CHECK-NEXT: subs r0, r0, r3 107; CHECK-NEXT: sbcs r0, r1, #0 108; CHECK-NEXT: vdup.32 d17, r5 109; CHECK-NEXT: movwlo r2, #1 110; CHECK-NEXT: cmp r2, #0 111; CHECK-NEXT: mvnne r2, #0 112; CHECK-NEXT: vdup.32 d16, r2 113; CHECK-NEXT: vand q9, q4, q8 114; CHECK-NEXT: vorn q8, q9, q8 115; CHECK-NEXT: vmovn.i64 d0, q8 116; CHECK-NEXT: vpop {d8, d9} 117; CHECK-NEXT: pop {r4, r5, r11, pc} 118entry: 119 %conv = fptoui <2 x double> %x to <2 x i64> 120 %0 = icmp ult <2 x i64> %conv, <i64 4294967295, i64 4294967295> 121 %spec.store.select = select <2 x i1> %0, <2 x i64> %conv, <2 x i64> <i64 4294967295, i64 4294967295> 122 %conv6 = trunc <2 x i64> %spec.store.select to <2 x i32> 123 ret <2 x i32> %conv6 124} 125 126define <2 x i32> @ustest_f64i32(<2 x double> %x) { 127; CHECK-LABEL: ustest_f64i32: 128; CHECK: @ %bb.0: @ %entry 129; CHECK-NEXT: .save {r4, r5, r11, lr} 130; CHECK-NEXT: push {r4, r5, r11, lr} 131; CHECK-NEXT: .vsave {d8, d9} 132; CHECK-NEXT: vpush {d8, d9} 133; CHECK-NEXT: vorr q4, q0, q0 134; CHECK-NEXT: vmov r0, r1, d9 135; CHECK-NEXT: bl __aeabi_d2lz 136; CHECK-NEXT: mov r4, r0 137; CHECK-NEXT: mov r5, r1 138; CHECK-NEXT: vmov r0, r1, d8 139; CHECK-NEXT: vmov.32 d9[0], r4 140; CHECK-NEXT: bl __aeabi_d2lz 141; CHECK-NEXT: vmov.32 d8[0], r0 142; CHECK-NEXT: mvn r3, #0 143; CHECK-NEXT: subs r4, r4, r3 144; CHECK-NEXT: vmov.i64 q9, #0xffffffff 145; CHECK-NEXT: vmov.32 d9[1], r5 146; CHECK-NEXT: sbcs r5, r5, #0 147; CHECK-NEXT: mov r5, #0 148; CHECK-NEXT: mov r2, #0 149; CHECK-NEXT: movwlt r5, #1 150; CHECK-NEXT: cmp r5, #0 151; CHECK-NEXT: mvnne r5, #0 152; CHECK-NEXT: subs r0, r0, r3 153; CHECK-NEXT: sbcs r0, r1, #0 154; CHECK-NEXT: vmov.32 d8[1], r1 155; CHECK-NEXT: mov r0, #0 156; CHECK-NEXT: movwlt r0, #1 157; CHECK-NEXT: cmp r0, #0 158; CHECK-NEXT: vdup.32 d17, r5 159; CHECK-NEXT: mvnne r0, #0 160; CHECK-NEXT: vdup.32 d16, r0 161; CHECK-NEXT: vbsl q8, q4, q9 162; CHECK-NEXT: vmov r0, r1, d17 163; CHECK-NEXT: vmov r3, r5, d16 164; CHECK-NEXT: rsbs r0, r0, #0 165; CHECK-NEXT: rscs r0, r1, #0 166; CHECK-NEXT: mov r0, #0 167; CHECK-NEXT: movwlt r0, #1 168; CHECK-NEXT: cmp r0, #0 169; CHECK-NEXT: mvnne r0, #0 170; CHECK-NEXT: rsbs r1, r3, #0 171; CHECK-NEXT: rscs r1, r5, #0 172; CHECK-NEXT: vmov.32 d19[0], r0 173; CHECK-NEXT: movwlt r2, #1 174; CHECK-NEXT: cmp r2, #0 175; CHECK-NEXT: mvnne r2, #0 176; CHECK-NEXT: vmov.32 d18[0], r2 177; CHECK-NEXT: vand q8, q8, q9 178; CHECK-NEXT: vmovn.i64 d0, q8 179; CHECK-NEXT: vpop {d8, d9} 180; CHECK-NEXT: pop {r4, r5, r11, pc} 181entry: 182 %conv = fptosi <2 x double> %x to <2 x i64> 183 %0 = icmp slt <2 x i64> %conv, <i64 4294967295, i64 4294967295> 184 %spec.store.select = select <2 x i1> %0, <2 x i64> %conv, <2 x i64> <i64 4294967295, i64 4294967295> 185 %1 = icmp sgt <2 x i64> %spec.store.select, zeroinitializer 186 %spec.store.select7 = select <2 x i1> %1, <2 x i64> %spec.store.select, <2 x i64> zeroinitializer 187 %conv6 = trunc <2 x i64> %spec.store.select7 to <2 x i32> 188 ret <2 x i32> %conv6 189} 190 191define <4 x i32> @stest_f32i32(<4 x float> %x) { 192; CHECK-LABEL: stest_f32i32: 193; CHECK: @ %bb.0: @ %entry 194; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr} 195; CHECK-NEXT: push {r4, r5, r6, r7, r8, r9, r10, r11, lr} 196; CHECK-NEXT: .pad #4 197; CHECK-NEXT: sub sp, sp, #4 198; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13} 199; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13} 200; CHECK-NEXT: vorr q4, q0, q0 201; CHECK-NEXT: vmov r0, s19 202; CHECK-NEXT: bl __aeabi_f2lz 203; CHECK-NEXT: mov r6, r0 204; CHECK-NEXT: vmov r0, s18 205; CHECK-NEXT: mov r7, r1 206; CHECK-NEXT: adr r1, .LCPI3_0 207; CHECK-NEXT: vld1.64 {d10, d11}, [r1:128] 208; CHECK-NEXT: vmov r5, s17 209; CHECK-NEXT: mov r4, #0 210; CHECK-NEXT: mvn r9, #-2147483648 211; CHECK-NEXT: vmov.32 d13[0], r6 212; CHECK-NEXT: bl __aeabi_f2lz 213; CHECK-NEXT: subs r2, r6, r9 214; CHECK-NEXT: vmov.32 d12[0], r0 215; CHECK-NEXT: sbcs r2, r7, #0 216; CHECK-NEXT: vmov r8, s16 217; CHECK-NEXT: mov r2, #0 218; CHECK-NEXT: vmov.32 d13[1], r7 219; CHECK-NEXT: movwlt r2, #1 220; CHECK-NEXT: cmp r2, #0 221; CHECK-NEXT: mvnne r2, #0 222; CHECK-NEXT: subs r0, r0, r9 223; CHECK-NEXT: sbcs r0, r1, #0 224; CHECK-NEXT: vdup.32 d17, r2 225; CHECK-NEXT: mov r0, #0 226; CHECK-NEXT: vmov.32 d12[1], r1 227; CHECK-NEXT: movwlt r0, #1 228; CHECK-NEXT: cmp r0, #0 229; CHECK-NEXT: mvnne r0, #0 230; CHECK-NEXT: vdup.32 d16, r0 231; CHECK-NEXT: mov r0, r5 232; CHECK-NEXT: vorr q4, q8, q8 233; CHECK-NEXT: vbsl q4, q6, q5 234; CHECK-NEXT: bl __aeabi_f2lz 235; CHECK-NEXT: vmov.32 d13[0], r0 236; CHECK-NEXT: subs r0, r0, r9 237; CHECK-NEXT: sbcs r0, r1, #0 238; CHECK-NEXT: mov r6, #0 239; CHECK-NEXT: movwlt r6, #1 240; CHECK-NEXT: cmp r6, #0 241; CHECK-NEXT: mov r0, r8 242; CHECK-NEXT: vmov r11, r10, d8 243; CHECK-NEXT: vmov.32 d13[1], r1 244; CHECK-NEXT: mvnne r6, #0 245; CHECK-NEXT: vmov r5, r7, d9 246; CHECK-NEXT: bl __aeabi_f2lz 247; CHECK-NEXT: vmov.32 d12[0], r0 248; CHECK-NEXT: subs r0, r0, r9 249; CHECK-NEXT: sbcs r0, r1, #0 250; CHECK-NEXT: mov r0, #0 251; CHECK-NEXT: vdup.32 d17, r6 252; CHECK-NEXT: movwlt r0, #1 253; CHECK-NEXT: cmp r0, #0 254; CHECK-NEXT: mvnne r0, #0 255; CHECK-NEXT: vmov.32 d12[1], r1 256; CHECK-NEXT: rsbs r3, r11, #-2147483648 257; CHECK-NEXT: vdup.32 d16, r0 258; CHECK-NEXT: mvn r0, #0 259; CHECK-NEXT: vbsl q8, q6, q5 260; CHECK-NEXT: adr r1, .LCPI3_1 261; CHECK-NEXT: vld1.64 {d18, d19}, [r1:128] 262; CHECK-NEXT: sbcs r3, r0, r10 263; CHECK-NEXT: mov r3, #0 264; CHECK-NEXT: vmov r1, r2, d17 265; CHECK-NEXT: movwlt r3, #1 266; CHECK-NEXT: cmp r3, #0 267; CHECK-NEXT: mvnne r3, #0 268; CHECK-NEXT: rsbs r6, r5, #-2147483648 269; CHECK-NEXT: vmov r6, r5, d16 270; CHECK-NEXT: sbcs r7, r0, r7 271; CHECK-NEXT: mov r7, #0 272; CHECK-NEXT: movwlt r7, #1 273; CHECK-NEXT: cmp r7, #0 274; CHECK-NEXT: mvnne r7, #0 275; CHECK-NEXT: vdup.32 d23, r7 276; CHECK-NEXT: vdup.32 d22, r3 277; CHECK-NEXT: vbsl q11, q4, q9 278; CHECK-NEXT: vmovn.i64 d1, q11 279; CHECK-NEXT: rsbs r1, r1, #-2147483648 280; CHECK-NEXT: sbcs r1, r0, r2 281; CHECK-NEXT: mov r1, #0 282; CHECK-NEXT: movwlt r1, #1 283; CHECK-NEXT: cmp r1, #0 284; CHECK-NEXT: mvnne r1, #0 285; CHECK-NEXT: rsbs r2, r6, #-2147483648 286; CHECK-NEXT: sbcs r0, r0, r5 287; CHECK-NEXT: vdup.32 d21, r1 288; CHECK-NEXT: movwlt r4, #1 289; CHECK-NEXT: cmp r4, #0 290; CHECK-NEXT: mvnne r4, #0 291; CHECK-NEXT: vdup.32 d20, r4 292; CHECK-NEXT: vbif q8, q9, q10 293; CHECK-NEXT: vmovn.i64 d0, q8 294; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13} 295; CHECK-NEXT: add sp, sp, #4 296; CHECK-NEXT: pop {r4, r5, r6, r7, r8, r9, r10, r11, pc} 297; CHECK-NEXT: .p2align 4 298; CHECK-NEXT: @ %bb.1: 299; CHECK-NEXT: .LCPI3_0: 300; CHECK-NEXT: .long 2147483647 @ 0x7fffffff 301; CHECK-NEXT: .long 0 @ 0x0 302; CHECK-NEXT: .long 2147483647 @ 0x7fffffff 303; CHECK-NEXT: .long 0 @ 0x0 304; CHECK-NEXT: .LCPI3_1: 305; CHECK-NEXT: .long 2147483648 @ 0x80000000 306; CHECK-NEXT: .long 4294967295 @ 0xffffffff 307; CHECK-NEXT: .long 2147483648 @ 0x80000000 308; CHECK-NEXT: .long 4294967295 @ 0xffffffff 309entry: 310 %conv = fptosi <4 x float> %x to <4 x i64> 311 %0 = icmp slt <4 x i64> %conv, <i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647> 312 %spec.store.select = select <4 x i1> %0, <4 x i64> %conv, <4 x i64> <i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647> 313 %1 = icmp sgt <4 x i64> %spec.store.select, <i64 -2147483648, i64 -2147483648, i64 -2147483648, i64 -2147483648> 314 %spec.store.select7 = select <4 x i1> %1, <4 x i64> %spec.store.select, <4 x i64> <i64 -2147483648, i64 -2147483648, i64 -2147483648, i64 -2147483648> 315 %conv6 = trunc <4 x i64> %spec.store.select7 to <4 x i32> 316 ret <4 x i32> %conv6 317} 318 319define <4 x i32> @utest_f32i32(<4 x float> %x) { 320; CHECK-LABEL: utest_f32i32: 321; CHECK: @ %bb.0: @ %entry 322; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, lr} 323; CHECK-NEXT: push {r4, r5, r6, r7, r8, r9, r10, lr} 324; CHECK-NEXT: .vsave {d8, d9, d10, d11} 325; CHECK-NEXT: vpush {d8, d9, d10, d11} 326; CHECK-NEXT: vorr q4, q0, q0 327; CHECK-NEXT: vmov r0, s17 328; CHECK-NEXT: bl __aeabi_f2ulz 329; CHECK-NEXT: mov r10, r0 330; CHECK-NEXT: vmov r0, s16 331; CHECK-NEXT: mov r8, r1 332; CHECK-NEXT: vmov r5, s19 333; CHECK-NEXT: vmov r7, s18 334; CHECK-NEXT: vmov.32 d9[0], r10 335; CHECK-NEXT: bl __aeabi_f2ulz 336; CHECK-NEXT: mov r6, r0 337; CHECK-NEXT: vmov.32 d8[0], r0 338; CHECK-NEXT: mov r0, r5 339; CHECK-NEXT: mov r9, r1 340; CHECK-NEXT: bl __aeabi_f2ulz 341; CHECK-NEXT: mov r5, r0 342; CHECK-NEXT: vmov.32 d11[0], r0 343; CHECK-NEXT: mov r0, r7 344; CHECK-NEXT: mov r4, r1 345; CHECK-NEXT: bl __aeabi_f2ulz 346; CHECK-NEXT: mvn r3, #0 347; CHECK-NEXT: vmov.32 d10[0], r0 348; CHECK-NEXT: subs r0, r0, r3 349; CHECK-NEXT: mov r2, #0 350; CHECK-NEXT: sbcs r0, r1, #0 351; CHECK-NEXT: mov r0, #0 352; CHECK-NEXT: movwlo r0, #1 353; CHECK-NEXT: cmp r0, #0 354; CHECK-NEXT: mvnne r0, #0 355; CHECK-NEXT: subs r1, r5, r3 356; CHECK-NEXT: sbcs r1, r4, #0 357; CHECK-NEXT: mov r1, #0 358; CHECK-NEXT: movwlo r1, #1 359; CHECK-NEXT: cmp r1, #0 360; CHECK-NEXT: mvnne r1, #0 361; CHECK-NEXT: subs r7, r10, r3 362; CHECK-NEXT: sbcs r7, r8, #0 363; CHECK-NEXT: vdup.32 d19, r1 364; CHECK-NEXT: mov r7, #0 365; CHECK-NEXT: vdup.32 d18, r0 366; CHECK-NEXT: movwlo r7, #1 367; CHECK-NEXT: cmp r7, #0 368; CHECK-NEXT: mvnne r7, #0 369; CHECK-NEXT: subs r3, r6, r3 370; CHECK-NEXT: sbcs r3, r9, #0 371; CHECK-NEXT: vdup.32 d17, r7 372; CHECK-NEXT: movwlo r2, #1 373; CHECK-NEXT: cmp r2, #0 374; CHECK-NEXT: mvnne r2, #0 375; CHECK-NEXT: vand q10, q5, q9 376; CHECK-NEXT: vdup.32 d16, r2 377; CHECK-NEXT: vand q11, q4, q8 378; CHECK-NEXT: vorn q9, q10, q9 379; CHECK-NEXT: vorn q8, q11, q8 380; CHECK-NEXT: vmovn.i64 d1, q9 381; CHECK-NEXT: vmovn.i64 d0, q8 382; CHECK-NEXT: vpop {d8, d9, d10, d11} 383; CHECK-NEXT: pop {r4, r5, r6, r7, r8, r9, r10, pc} 384entry: 385 %conv = fptoui <4 x float> %x to <4 x i64> 386 %0 = icmp ult <4 x i64> %conv, <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295> 387 %spec.store.select = select <4 x i1> %0, <4 x i64> %conv, <4 x i64> <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295> 388 %conv6 = trunc <4 x i64> %spec.store.select to <4 x i32> 389 ret <4 x i32> %conv6 390} 391 392define <4 x i32> @ustest_f32i32(<4 x float> %x) { 393; CHECK-LABEL: ustest_f32i32: 394; CHECK: @ %bb.0: @ %entry 395; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, lr} 396; CHECK-NEXT: push {r4, r5, r6, r7, r8, r9, r10, lr} 397; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13} 398; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13} 399; CHECK-NEXT: vorr q4, q0, q0 400; CHECK-NEXT: vmov r0, s19 401; CHECK-NEXT: bl __aeabi_f2lz 402; CHECK-NEXT: mov r6, r0 403; CHECK-NEXT: vmov r0, s18 404; CHECK-NEXT: mov r7, r1 405; CHECK-NEXT: vmov r5, s17 406; CHECK-NEXT: vmov r8, s16 407; CHECK-NEXT: vmov.32 d9[0], r6 408; CHECK-NEXT: bl __aeabi_f2lz 409; CHECK-NEXT: mvn r9, #0 410; CHECK-NEXT: subs r2, r6, r9 411; CHECK-NEXT: sbcs r2, r7, #0 412; CHECK-NEXT: vmov.32 d8[0], r0 413; CHECK-NEXT: mov r2, #0 414; CHECK-NEXT: vmov.i64 q5, #0xffffffff 415; CHECK-NEXT: movwlt r2, #1 416; CHECK-NEXT: cmp r2, #0 417; CHECK-NEXT: mvnne r2, #0 418; CHECK-NEXT: subs r0, r0, r9 419; CHECK-NEXT: sbcs r0, r1, #0 420; CHECK-NEXT: vmov.32 d9[1], r7 421; CHECK-NEXT: mov r0, #0 422; CHECK-NEXT: mov r4, #0 423; CHECK-NEXT: movwlt r0, #1 424; CHECK-NEXT: cmp r0, #0 425; CHECK-NEXT: vmov.32 d8[1], r1 426; CHECK-NEXT: mvnne r0, #0 427; CHECK-NEXT: vdup.32 d17, r2 428; CHECK-NEXT: vdup.32 d16, r0 429; CHECK-NEXT: mov r0, r5 430; CHECK-NEXT: vbif q4, q5, q8 431; CHECK-NEXT: bl __aeabi_f2lz 432; CHECK-NEXT: mov r5, r0 433; CHECK-NEXT: vmov.32 d13[0], r0 434; CHECK-NEXT: mov r0, r8 435; CHECK-NEXT: mov r6, r1 436; CHECK-NEXT: vmov r7, r10, d8 437; CHECK-NEXT: bl __aeabi_f2lz 438; CHECK-NEXT: subs r2, r5, r9 439; CHECK-NEXT: vmov.32 d12[0], r0 440; CHECK-NEXT: sbcs r2, r6, #0 441; CHECK-NEXT: mov r2, #0 442; CHECK-NEXT: vmov.32 d13[1], r6 443; CHECK-NEXT: movwlt r2, #1 444; CHECK-NEXT: cmp r2, #0 445; CHECK-NEXT: mvnne r2, #0 446; CHECK-NEXT: subs r0, r0, r9 447; CHECK-NEXT: sbcs r0, r1, #0 448; CHECK-NEXT: vdup.32 d17, r2 449; CHECK-NEXT: mov r0, #0 450; CHECK-NEXT: vmov.32 d12[1], r1 451; CHECK-NEXT: movwlt r0, #1 452; CHECK-NEXT: cmp r0, #0 453; CHECK-NEXT: mvnne r0, #0 454; CHECK-NEXT: vmov r2, r3, d9 455; CHECK-NEXT: vdup.32 d16, r0 456; CHECK-NEXT: rsbs r7, r7, #0 457; CHECK-NEXT: vbsl q8, q6, q5 458; CHECK-NEXT: rscs r7, r10, #0 459; CHECK-NEXT: mov r7, #0 460; CHECK-NEXT: movwlt r7, #1 461; CHECK-NEXT: cmp r7, #0 462; CHECK-NEXT: vmov r0, r1, d17 463; CHECK-NEXT: mvnne r7, #0 464; CHECK-NEXT: vmov r6, r5, d16 465; CHECK-NEXT: rsbs r0, r0, #0 466; CHECK-NEXT: rscs r0, r1, #0 467; CHECK-NEXT: mov r0, #0 468; CHECK-NEXT: movwlt r0, #1 469; CHECK-NEXT: cmp r0, #0 470; CHECK-NEXT: mvnne r0, #0 471; CHECK-NEXT: rsbs r1, r2, #0 472; CHECK-NEXT: rscs r1, r3, #0 473; CHECK-NEXT: vmov.32 d19[0], r0 474; CHECK-NEXT: mov r1, #0 475; CHECK-NEXT: movwlt r1, #1 476; CHECK-NEXT: cmp r1, #0 477; CHECK-NEXT: mvnne r1, #0 478; CHECK-NEXT: rsbs r0, r6, #0 479; CHECK-NEXT: rscs r0, r5, #0 480; CHECK-NEXT: vmov.32 d21[0], r1 481; CHECK-NEXT: movwlt r4, #1 482; CHECK-NEXT: cmp r4, #0 483; CHECK-NEXT: vmov.32 d20[0], r7 484; CHECK-NEXT: mvnne r4, #0 485; CHECK-NEXT: vmov.32 d18[0], r4 486; CHECK-NEXT: vand q10, q4, q10 487; CHECK-NEXT: vand q8, q8, q9 488; CHECK-NEXT: vmovn.i64 d1, q10 489; CHECK-NEXT: vmovn.i64 d0, q8 490; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13} 491; CHECK-NEXT: pop {r4, r5, r6, r7, r8, r9, r10, pc} 492entry: 493 %conv = fptosi <4 x float> %x to <4 x i64> 494 %0 = icmp slt <4 x i64> %conv, <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295> 495 %spec.store.select = select <4 x i1> %0, <4 x i64> %conv, <4 x i64> <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295> 496 %1 = icmp sgt <4 x i64> %spec.store.select, zeroinitializer 497 %spec.store.select7 = select <4 x i1> %1, <4 x i64> %spec.store.select, <4 x i64> zeroinitializer 498 %conv6 = trunc <4 x i64> %spec.store.select7 to <4 x i32> 499 ret <4 x i32> %conv6 500} 501 502define <4 x i32> @stest_f16i32(<4 x half> %x) { 503; CHECK-NEON-LABEL: stest_f16i32: 504; CHECK-NEON: @ %bb.0: @ %entry 505; CHECK-NEON-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr} 506; CHECK-NEON-NEXT: push {r4, r5, r6, r7, r8, r9, r10, r11, lr} 507; CHECK-NEON-NEXT: .pad #4 508; CHECK-NEON-NEXT: sub sp, sp, #4 509; CHECK-NEON-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} 510; CHECK-NEON-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} 511; CHECK-NEON-NEXT: vmov r0, s2 512; CHECK-NEON-NEXT: vmov.f32 s16, s3 513; CHECK-NEON-NEXT: vmov.f32 s18, s1 514; CHECK-NEON-NEXT: vmov.f32 s20, s0 515; CHECK-NEON-NEXT: bl __aeabi_h2f 516; CHECK-NEON-NEXT: bl __aeabi_f2lz 517; CHECK-NEON-NEXT: mov r6, r0 518; CHECK-NEON-NEXT: vmov r0, s16 519; CHECK-NEON-NEXT: mov r5, r1 520; CHECK-NEON-NEXT: bl __aeabi_h2f 521; CHECK-NEON-NEXT: bl __aeabi_f2lz 522; CHECK-NEON-NEXT: vmov r2, s18 523; CHECK-NEON-NEXT: adr r3, .LCPI6_0 524; CHECK-NEON-NEXT: vld1.64 {d8, d9}, [r3:128] 525; CHECK-NEON-NEXT: mvn r9, #-2147483648 526; CHECK-NEON-NEXT: subs r3, r6, r9 527; CHECK-NEON-NEXT: mov r4, #0 528; CHECK-NEON-NEXT: sbcs r3, r5, #0 529; CHECK-NEON-NEXT: vmov.32 d15[0], r0 530; CHECK-NEON-NEXT: movwlt r4, #1 531; CHECK-NEON-NEXT: cmp r4, #0 532; CHECK-NEON-NEXT: mvnne r4, #0 533; CHECK-NEON-NEXT: subs r0, r0, r9 534; CHECK-NEON-NEXT: sbcs r0, r1, #0 535; CHECK-NEON-NEXT: vmov.32 d14[0], r6 536; CHECK-NEON-NEXT: mov r0, #0 537; CHECK-NEON-NEXT: vmov r8, s20 538; CHECK-NEON-NEXT: movwlt r0, #1 539; CHECK-NEON-NEXT: cmp r0, #0 540; CHECK-NEON-NEXT: mvnne r0, #0 541; CHECK-NEON-NEXT: vmov.32 d15[1], r1 542; CHECK-NEON-NEXT: mov r7, #0 543; CHECK-NEON-NEXT: vdup.32 d11, r0 544; CHECK-NEON-NEXT: vmov.32 d14[1], r5 545; CHECK-NEON-NEXT: mov r0, r2 546; CHECK-NEON-NEXT: bl __aeabi_h2f 547; CHECK-NEON-NEXT: vdup.32 d10, r4 548; CHECK-NEON-NEXT: bl __aeabi_f2lz 549; CHECK-NEON-NEXT: vmov.32 d13[0], r0 550; CHECK-NEON-NEXT: subs r0, r0, r9 551; CHECK-NEON-NEXT: vbsl q5, q7, q4 552; CHECK-NEON-NEXT: sbcs r0, r1, #0 553; CHECK-NEON-NEXT: mov r6, #0 554; CHECK-NEON-NEXT: mov r0, r8 555; CHECK-NEON-NEXT: movwlt r6, #1 556; CHECK-NEON-NEXT: cmp r6, #0 557; CHECK-NEON-NEXT: vmov r11, r10, d10 558; CHECK-NEON-NEXT: vmov.32 d13[1], r1 559; CHECK-NEON-NEXT: mvnne r6, #0 560; CHECK-NEON-NEXT: vmov r5, r4, d11 561; CHECK-NEON-NEXT: bl __aeabi_h2f 562; CHECK-NEON-NEXT: bl __aeabi_f2lz 563; CHECK-NEON-NEXT: vmov.32 d12[0], r0 564; CHECK-NEON-NEXT: subs r0, r0, r9 565; CHECK-NEON-NEXT: sbcs r0, r1, #0 566; CHECK-NEON-NEXT: mov r0, #0 567; CHECK-NEON-NEXT: vdup.32 d17, r6 568; CHECK-NEON-NEXT: movwlt r0, #1 569; CHECK-NEON-NEXT: cmp r0, #0 570; CHECK-NEON-NEXT: mvnne r0, #0 571; CHECK-NEON-NEXT: vmov.32 d12[1], r1 572; CHECK-NEON-NEXT: rsbs r3, r11, #-2147483648 573; CHECK-NEON-NEXT: vdup.32 d16, r0 574; CHECK-NEON-NEXT: mvn r0, #0 575; CHECK-NEON-NEXT: vbsl q8, q6, q4 576; CHECK-NEON-NEXT: adr r1, .LCPI6_1 577; CHECK-NEON-NEXT: vld1.64 {d18, d19}, [r1:128] 578; CHECK-NEON-NEXT: sbcs r3, r0, r10 579; CHECK-NEON-NEXT: mov r3, #0 580; CHECK-NEON-NEXT: vmov r1, r2, d17 581; CHECK-NEON-NEXT: movwlt r3, #1 582; CHECK-NEON-NEXT: cmp r3, #0 583; CHECK-NEON-NEXT: mvnne r3, #0 584; CHECK-NEON-NEXT: rsbs r6, r5, #-2147483648 585; CHECK-NEON-NEXT: sbcs r6, r0, r4 586; CHECK-NEON-NEXT: vmov r5, r4, d16 587; CHECK-NEON-NEXT: mov r6, #0 588; CHECK-NEON-NEXT: movwlt r6, #1 589; CHECK-NEON-NEXT: cmp r6, #0 590; CHECK-NEON-NEXT: mvnne r6, #0 591; CHECK-NEON-NEXT: vdup.32 d23, r6 592; CHECK-NEON-NEXT: vdup.32 d22, r3 593; CHECK-NEON-NEXT: vbsl q11, q5, q9 594; CHECK-NEON-NEXT: vmovn.i64 d1, q11 595; CHECK-NEON-NEXT: rsbs r1, r1, #-2147483648 596; CHECK-NEON-NEXT: sbcs r1, r0, r2 597; CHECK-NEON-NEXT: mov r1, #0 598; CHECK-NEON-NEXT: movwlt r1, #1 599; CHECK-NEON-NEXT: cmp r1, #0 600; CHECK-NEON-NEXT: mvnne r1, #0 601; CHECK-NEON-NEXT: rsbs r2, r5, #-2147483648 602; CHECK-NEON-NEXT: sbcs r0, r0, r4 603; CHECK-NEON-NEXT: vdup.32 d21, r1 604; CHECK-NEON-NEXT: movwlt r7, #1 605; CHECK-NEON-NEXT: cmp r7, #0 606; CHECK-NEON-NEXT: mvnne r7, #0 607; CHECK-NEON-NEXT: vdup.32 d20, r7 608; CHECK-NEON-NEXT: vbif q8, q9, q10 609; CHECK-NEON-NEXT: vmovn.i64 d0, q8 610; CHECK-NEON-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15} 611; CHECK-NEON-NEXT: add sp, sp, #4 612; CHECK-NEON-NEXT: pop {r4, r5, r6, r7, r8, r9, r10, r11, pc} 613; CHECK-NEON-NEXT: .p2align 4 614; CHECK-NEON-NEXT: @ %bb.1: 615; CHECK-NEON-NEXT: .LCPI6_0: 616; CHECK-NEON-NEXT: .long 2147483647 @ 0x7fffffff 617; CHECK-NEON-NEXT: .long 0 @ 0x0 618; CHECK-NEON-NEXT: .long 2147483647 @ 0x7fffffff 619; CHECK-NEON-NEXT: .long 0 @ 0x0 620; CHECK-NEON-NEXT: .LCPI6_1: 621; CHECK-NEON-NEXT: .long 2147483648 @ 0x80000000 622; CHECK-NEON-NEXT: .long 4294967295 @ 0xffffffff 623; CHECK-NEON-NEXT: .long 2147483648 @ 0x80000000 624; CHECK-NEON-NEXT: .long 4294967295 @ 0xffffffff 625; 626; CHECK-FP16-LABEL: stest_f16i32: 627; CHECK-FP16: @ %bb.0: @ %entry 628; CHECK-FP16-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, lr} 629; CHECK-FP16-NEXT: push {r4, r5, r6, r7, r8, r9, r10, lr} 630; CHECK-FP16-NEXT: .vsave {d8, d9, d10, d11, d12, d13} 631; CHECK-FP16-NEXT: vpush {d8, d9, d10, d11, d12, d13} 632; CHECK-FP16-NEXT: vmov.u16 r0, d0[3] 633; CHECK-FP16-NEXT: vorr d8, d0, d0 634; CHECK-FP16-NEXT: vmov.u16 r8, d0[0] 635; CHECK-FP16-NEXT: vmov.u16 r9, d0[1] 636; CHECK-FP16-NEXT: vmov s0, r0 637; CHECK-FP16-NEXT: bl __fixhfdi 638; CHECK-FP16-NEXT: mov r4, r0 639; CHECK-FP16-NEXT: vmov.u16 r0, d8[2] 640; CHECK-FP16-NEXT: mov r5, r1 641; CHECK-FP16-NEXT: vmov.32 d9[0], r4 642; CHECK-FP16-NEXT: vmov s0, r0 643; CHECK-FP16-NEXT: bl __fixhfdi 644; CHECK-FP16-NEXT: adr r2, .LCPI6_0 645; CHECK-FP16-NEXT: mvn r10, #-2147483648 646; CHECK-FP16-NEXT: vld1.64 {d10, d11}, [r2:128] 647; CHECK-FP16-NEXT: subs r2, r4, r10 648; CHECK-FP16-NEXT: sbcs r2, r5, #0 649; CHECK-FP16-NEXT: vmov s0, r9 650; CHECK-FP16-NEXT: mov r2, #0 651; CHECK-FP16-NEXT: vmov.32 d8[0], r0 652; CHECK-FP16-NEXT: movwlt r2, #1 653; CHECK-FP16-NEXT: cmp r2, #0 654; CHECK-FP16-NEXT: mvnne r2, #0 655; CHECK-FP16-NEXT: subs r0, r0, r10 656; CHECK-FP16-NEXT: sbcs r0, r1, #0 657; CHECK-FP16-NEXT: vmov.32 d9[1], r5 658; CHECK-FP16-NEXT: mov r0, #0 659; CHECK-FP16-NEXT: mov r6, #0 660; CHECK-FP16-NEXT: movwlt r0, #1 661; CHECK-FP16-NEXT: cmp r0, #0 662; CHECK-FP16-NEXT: vmov.32 d8[1], r1 663; CHECK-FP16-NEXT: mvnne r0, #0 664; CHECK-FP16-NEXT: vdup.32 d17, r2 665; CHECK-FP16-NEXT: vdup.32 d16, r0 666; CHECK-FP16-NEXT: vbif q4, q5, q8 667; CHECK-FP16-NEXT: bl __fixhfdi 668; CHECK-FP16-NEXT: vmov.32 d13[0], r0 669; CHECK-FP16-NEXT: subs r0, r0, r10 670; CHECK-FP16-NEXT: vmov s0, r8 671; CHECK-FP16-NEXT: sbcs r0, r1, #0 672; CHECK-FP16-NEXT: mov r7, #0 673; CHECK-FP16-NEXT: vmov r9, r8, d8 674; CHECK-FP16-NEXT: movwlt r7, #1 675; CHECK-FP16-NEXT: cmp r7, #0 676; CHECK-FP16-NEXT: vmov.32 d13[1], r1 677; CHECK-FP16-NEXT: vmov r5, r4, d9 678; CHECK-FP16-NEXT: mvnne r7, #0 679; CHECK-FP16-NEXT: bl __fixhfdi 680; CHECK-FP16-NEXT: vmov.32 d12[0], r0 681; CHECK-FP16-NEXT: subs r0, r0, r10 682; CHECK-FP16-NEXT: sbcs r0, r1, #0 683; CHECK-FP16-NEXT: mov r0, #0 684; CHECK-FP16-NEXT: vdup.32 d17, r7 685; CHECK-FP16-NEXT: movwlt r0, #1 686; CHECK-FP16-NEXT: cmp r0, #0 687; CHECK-FP16-NEXT: mvnne r0, #0 688; CHECK-FP16-NEXT: vmov.32 d12[1], r1 689; CHECK-FP16-NEXT: rsbs r3, r9, #-2147483648 690; CHECK-FP16-NEXT: vdup.32 d16, r0 691; CHECK-FP16-NEXT: mvn r0, #0 692; CHECK-FP16-NEXT: vbsl q8, q6, q5 693; CHECK-FP16-NEXT: adr r1, .LCPI6_1 694; CHECK-FP16-NEXT: vld1.64 {d18, d19}, [r1:128] 695; CHECK-FP16-NEXT: sbcs r3, r0, r8 696; CHECK-FP16-NEXT: mov r3, #0 697; CHECK-FP16-NEXT: vmov r1, r2, d17 698; CHECK-FP16-NEXT: movwlt r3, #1 699; CHECK-FP16-NEXT: cmp r3, #0 700; CHECK-FP16-NEXT: mvnne r3, #0 701; CHECK-FP16-NEXT: rsbs r7, r5, #-2147483648 702; CHECK-FP16-NEXT: sbcs r7, r0, r4 703; CHECK-FP16-NEXT: vmov r5, r4, d16 704; CHECK-FP16-NEXT: mov r7, #0 705; CHECK-FP16-NEXT: movwlt r7, #1 706; CHECK-FP16-NEXT: cmp r7, #0 707; CHECK-FP16-NEXT: mvnne r7, #0 708; CHECK-FP16-NEXT: vdup.32 d23, r7 709; CHECK-FP16-NEXT: vdup.32 d22, r3 710; CHECK-FP16-NEXT: vbsl q11, q4, q9 711; CHECK-FP16-NEXT: vmovn.i64 d1, q11 712; CHECK-FP16-NEXT: rsbs r1, r1, #-2147483648 713; CHECK-FP16-NEXT: sbcs r1, r0, r2 714; CHECK-FP16-NEXT: mov r1, #0 715; CHECK-FP16-NEXT: movwlt r1, #1 716; CHECK-FP16-NEXT: cmp r1, #0 717; CHECK-FP16-NEXT: mvnne r1, #0 718; CHECK-FP16-NEXT: rsbs r2, r5, #-2147483648 719; CHECK-FP16-NEXT: sbcs r0, r0, r4 720; CHECK-FP16-NEXT: vdup.32 d21, r1 721; CHECK-FP16-NEXT: movwlt r6, #1 722; CHECK-FP16-NEXT: cmp r6, #0 723; CHECK-FP16-NEXT: mvnne r6, #0 724; CHECK-FP16-NEXT: vdup.32 d20, r6 725; CHECK-FP16-NEXT: vbif q8, q9, q10 726; CHECK-FP16-NEXT: vmovn.i64 d0, q8 727; CHECK-FP16-NEXT: vpop {d8, d9, d10, d11, d12, d13} 728; CHECK-FP16-NEXT: pop {r4, r5, r6, r7, r8, r9, r10, pc} 729; CHECK-FP16-NEXT: .p2align 4 730; CHECK-FP16-NEXT: @ %bb.1: 731; CHECK-FP16-NEXT: .LCPI6_0: 732; CHECK-FP16-NEXT: .long 2147483647 @ 0x7fffffff 733; CHECK-FP16-NEXT: .long 0 @ 0x0 734; CHECK-FP16-NEXT: .long 2147483647 @ 0x7fffffff 735; CHECK-FP16-NEXT: .long 0 @ 0x0 736; CHECK-FP16-NEXT: .LCPI6_1: 737; CHECK-FP16-NEXT: .long 2147483648 @ 0x80000000 738; CHECK-FP16-NEXT: .long 4294967295 @ 0xffffffff 739; CHECK-FP16-NEXT: .long 2147483648 @ 0x80000000 740; CHECK-FP16-NEXT: .long 4294967295 @ 0xffffffff 741entry: 742 %conv = fptosi <4 x half> %x to <4 x i64> 743 %0 = icmp slt <4 x i64> %conv, <i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647> 744 %spec.store.select = select <4 x i1> %0, <4 x i64> %conv, <4 x i64> <i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647> 745 %1 = icmp sgt <4 x i64> %spec.store.select, <i64 -2147483648, i64 -2147483648, i64 -2147483648, i64 -2147483648> 746 %spec.store.select7 = select <4 x i1> %1, <4 x i64> %spec.store.select, <4 x i64> <i64 -2147483648, i64 -2147483648, i64 -2147483648, i64 -2147483648> 747 %conv6 = trunc <4 x i64> %spec.store.select7 to <4 x i32> 748 ret <4 x i32> %conv6 749} 750 751define <4 x i32> @utesth_f16i32(<4 x half> %x) { 752; CHECK-NEON-LABEL: utesth_f16i32: 753; CHECK-NEON: @ %bb.0: @ %entry 754; CHECK-NEON-NEXT: .save {r4, r5, r6, r7, r8, r9, r11, lr} 755; CHECK-NEON-NEXT: push {r4, r5, r6, r7, r8, r9, r11, lr} 756; CHECK-NEON-NEXT: .vsave {d12, d13} 757; CHECK-NEON-NEXT: vpush {d12, d13} 758; CHECK-NEON-NEXT: .vsave {d8, d9, d10} 759; CHECK-NEON-NEXT: vpush {d8, d9, d10} 760; CHECK-NEON-NEXT: vmov r0, s3 761; CHECK-NEON-NEXT: vmov.f32 s16, s2 762; CHECK-NEON-NEXT: vmov.f32 s18, s1 763; CHECK-NEON-NEXT: vmov.f32 s20, s0 764; CHECK-NEON-NEXT: bl __aeabi_h2f 765; CHECK-NEON-NEXT: bl __aeabi_f2ulz 766; CHECK-NEON-NEXT: mov r4, r0 767; CHECK-NEON-NEXT: vmov r0, s18 768; CHECK-NEON-NEXT: mov r8, r1 769; CHECK-NEON-NEXT: bl __aeabi_h2f 770; CHECK-NEON-NEXT: bl __aeabi_f2ulz 771; CHECK-NEON-NEXT: mov r6, r0 772; CHECK-NEON-NEXT: vmov.32 d13[0], r0 773; CHECK-NEON-NEXT: vmov r0, s20 774; CHECK-NEON-NEXT: mov r9, r1 775; CHECK-NEON-NEXT: bl __aeabi_h2f 776; CHECK-NEON-NEXT: bl __aeabi_f2ulz 777; CHECK-NEON-NEXT: mov r5, r0 778; CHECK-NEON-NEXT: vmov.32 d12[0], r0 779; CHECK-NEON-NEXT: vmov r0, s16 780; CHECK-NEON-NEXT: mov r7, r1 781; CHECK-NEON-NEXT: bl __aeabi_h2f 782; CHECK-NEON-NEXT: vmov.32 d9[0], r4 783; CHECK-NEON-NEXT: bl __aeabi_f2ulz 784; CHECK-NEON-NEXT: mvn r3, #0 785; CHECK-NEON-NEXT: vmov.32 d8[0], r0 786; CHECK-NEON-NEXT: subs r0, r0, r3 787; CHECK-NEON-NEXT: mov r2, #0 788; CHECK-NEON-NEXT: sbcs r0, r1, #0 789; CHECK-NEON-NEXT: mov r0, #0 790; CHECK-NEON-NEXT: movwlo r0, #1 791; CHECK-NEON-NEXT: cmp r0, #0 792; CHECK-NEON-NEXT: mvnne r0, #0 793; CHECK-NEON-NEXT: subs r1, r4, r3 794; CHECK-NEON-NEXT: sbcs r1, r8, #0 795; CHECK-NEON-NEXT: mov r1, #0 796; CHECK-NEON-NEXT: movwlo r1, #1 797; CHECK-NEON-NEXT: cmp r1, #0 798; CHECK-NEON-NEXT: mvnne r1, #0 799; CHECK-NEON-NEXT: subs r6, r6, r3 800; CHECK-NEON-NEXT: sbcs r6, r9, #0 801; CHECK-NEON-NEXT: vdup.32 d19, r1 802; CHECK-NEON-NEXT: mov r6, #0 803; CHECK-NEON-NEXT: vdup.32 d18, r0 804; CHECK-NEON-NEXT: movwlo r6, #1 805; CHECK-NEON-NEXT: cmp r6, #0 806; CHECK-NEON-NEXT: mvnne r6, #0 807; CHECK-NEON-NEXT: subs r3, r5, r3 808; CHECK-NEON-NEXT: sbcs r3, r7, #0 809; CHECK-NEON-NEXT: vdup.32 d17, r6 810; CHECK-NEON-NEXT: movwlo r2, #1 811; CHECK-NEON-NEXT: cmp r2, #0 812; CHECK-NEON-NEXT: mvnne r2, #0 813; CHECK-NEON-NEXT: vand q10, q4, q9 814; CHECK-NEON-NEXT: vdup.32 d16, r2 815; CHECK-NEON-NEXT: vand q11, q6, q8 816; CHECK-NEON-NEXT: vorn q9, q10, q9 817; CHECK-NEON-NEXT: vorn q8, q11, q8 818; CHECK-NEON-NEXT: vmovn.i64 d1, q9 819; CHECK-NEON-NEXT: vmovn.i64 d0, q8 820; CHECK-NEON-NEXT: vpop {d8, d9, d10} 821; CHECK-NEON-NEXT: vpop {d12, d13} 822; CHECK-NEON-NEXT: pop {r4, r5, r6, r7, r8, r9, r11, pc} 823; 824; CHECK-FP16-LABEL: utesth_f16i32: 825; CHECK-FP16: @ %bb.0: @ %entry 826; CHECK-FP16-NEXT: .save {r4, r5, r6, r7, r8, r9, r11, lr} 827; CHECK-FP16-NEXT: push {r4, r5, r6, r7, r8, r9, r11, lr} 828; CHECK-FP16-NEXT: .vsave {d8, d9, d10, d11} 829; CHECK-FP16-NEXT: vpush {d8, d9, d10, d11} 830; CHECK-FP16-NEXT: vmov.u16 r0, d0[1] 831; CHECK-FP16-NEXT: vorr d8, d0, d0 832; CHECK-FP16-NEXT: vmov.u16 r5, d0[3] 833; CHECK-FP16-NEXT: vmov s0, r0 834; CHECK-FP16-NEXT: bl __fixunshfdi 835; CHECK-FP16-NEXT: mov r4, r0 836; CHECK-FP16-NEXT: vmov.u16 r0, d8[0] 837; CHECK-FP16-NEXT: mov r8, r1 838; CHECK-FP16-NEXT: vmov.32 d11[0], r4 839; CHECK-FP16-NEXT: vmov s0, r0 840; CHECK-FP16-NEXT: bl __fixunshfdi 841; CHECK-FP16-NEXT: vmov s0, r5 842; CHECK-FP16-NEXT: mov r6, r0 843; CHECK-FP16-NEXT: mov r9, r1 844; CHECK-FP16-NEXT: vmov.32 d10[0], r0 845; CHECK-FP16-NEXT: bl __fixunshfdi 846; CHECK-FP16-NEXT: mov r5, r0 847; CHECK-FP16-NEXT: vmov.u16 r0, d8[2] 848; CHECK-FP16-NEXT: mov r7, r1 849; CHECK-FP16-NEXT: vmov.32 d9[0], r5 850; CHECK-FP16-NEXT: vmov s0, r0 851; CHECK-FP16-NEXT: bl __fixunshfdi 852; CHECK-FP16-NEXT: mvn r3, #0 853; CHECK-FP16-NEXT: vmov.32 d8[0], r0 854; CHECK-FP16-NEXT: subs r0, r0, r3 855; CHECK-FP16-NEXT: mov r2, #0 856; CHECK-FP16-NEXT: sbcs r0, r1, #0 857; CHECK-FP16-NEXT: mov r0, #0 858; CHECK-FP16-NEXT: movwlo r0, #1 859; CHECK-FP16-NEXT: cmp r0, #0 860; CHECK-FP16-NEXT: mvnne r0, #0 861; CHECK-FP16-NEXT: subs r1, r5, r3 862; CHECK-FP16-NEXT: sbcs r1, r7, #0 863; CHECK-FP16-NEXT: mov r1, #0 864; CHECK-FP16-NEXT: movwlo r1, #1 865; CHECK-FP16-NEXT: cmp r1, #0 866; CHECK-FP16-NEXT: mvnne r1, #0 867; CHECK-FP16-NEXT: subs r7, r4, r3 868; CHECK-FP16-NEXT: sbcs r7, r8, #0 869; CHECK-FP16-NEXT: vdup.32 d19, r1 870; CHECK-FP16-NEXT: mov r7, #0 871; CHECK-FP16-NEXT: vdup.32 d18, r0 872; CHECK-FP16-NEXT: movwlo r7, #1 873; CHECK-FP16-NEXT: cmp r7, #0 874; CHECK-FP16-NEXT: mvnne r7, #0 875; CHECK-FP16-NEXT: subs r3, r6, r3 876; CHECK-FP16-NEXT: sbcs r3, r9, #0 877; CHECK-FP16-NEXT: vdup.32 d17, r7 878; CHECK-FP16-NEXT: movwlo r2, #1 879; CHECK-FP16-NEXT: cmp r2, #0 880; CHECK-FP16-NEXT: mvnne r2, #0 881; CHECK-FP16-NEXT: vand q10, q4, q9 882; CHECK-FP16-NEXT: vdup.32 d16, r2 883; CHECK-FP16-NEXT: vand q11, q5, q8 884; CHECK-FP16-NEXT: vorn q9, q10, q9 885; CHECK-FP16-NEXT: vorn q8, q11, q8 886; CHECK-FP16-NEXT: vmovn.i64 d1, q9 887; CHECK-FP16-NEXT: vmovn.i64 d0, q8 888; CHECK-FP16-NEXT: vpop {d8, d9, d10, d11} 889; CHECK-FP16-NEXT: pop {r4, r5, r6, r7, r8, r9, r11, pc} 890entry: 891 %conv = fptoui <4 x half> %x to <4 x i64> 892 %0 = icmp ult <4 x i64> %conv, <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295> 893 %spec.store.select = select <4 x i1> %0, <4 x i64> %conv, <4 x i64> <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295> 894 %conv6 = trunc <4 x i64> %spec.store.select to <4 x i32> 895 ret <4 x i32> %conv6 896} 897 898define <4 x i32> @ustest_f16i32(<4 x half> %x) { 899; CHECK-NEON-LABEL: ustest_f16i32: 900; CHECK-NEON: @ %bb.0: @ %entry 901; CHECK-NEON-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, lr} 902; CHECK-NEON-NEXT: push {r4, r5, r6, r7, r8, r9, r10, lr} 903; CHECK-NEON-NEXT: .vsave {d8, d9, d10, d11, d12, d13} 904; CHECK-NEON-NEXT: vpush {d8, d9, d10, d11, d12, d13} 905; CHECK-NEON-NEXT: vmov r0, s3 906; CHECK-NEON-NEXT: vmov.f32 s16, s2 907; CHECK-NEON-NEXT: vmov.f32 s18, s1 908; CHECK-NEON-NEXT: vmov.f32 s20, s0 909; CHECK-NEON-NEXT: bl __aeabi_h2f 910; CHECK-NEON-NEXT: bl __aeabi_f2lz 911; CHECK-NEON-NEXT: mov r5, r0 912; CHECK-NEON-NEXT: vmov r0, s16 913; CHECK-NEON-NEXT: mov r6, r1 914; CHECK-NEON-NEXT: bl __aeabi_h2f 915; CHECK-NEON-NEXT: vmov r8, s20 916; CHECK-NEON-NEXT: vmov.32 d13[0], r5 917; CHECK-NEON-NEXT: bl __aeabi_f2lz 918; CHECK-NEON-NEXT: vmov r2, s18 919; CHECK-NEON-NEXT: vmov.32 d12[0], r0 920; CHECK-NEON-NEXT: mvn r9, #0 921; CHECK-NEON-NEXT: subs r0, r0, r9 922; CHECK-NEON-NEXT: sbcs r0, r1, #0 923; CHECK-NEON-NEXT: vmov.32 d13[1], r6 924; CHECK-NEON-NEXT: mov r0, #0 925; CHECK-NEON-NEXT: mov r7, #0 926; CHECK-NEON-NEXT: movwlt r0, #1 927; CHECK-NEON-NEXT: cmp r0, #0 928; CHECK-NEON-NEXT: vmov.32 d12[1], r1 929; CHECK-NEON-NEXT: mvnne r0, #0 930; CHECK-NEON-NEXT: subs r1, r5, r9 931; CHECK-NEON-NEXT: sbcs r1, r6, #0 932; CHECK-NEON-NEXT: mov r1, #0 933; CHECK-NEON-NEXT: movwlt r1, #1 934; CHECK-NEON-NEXT: cmp r1, #0 935; CHECK-NEON-NEXT: mvnne r1, #0 936; CHECK-NEON-NEXT: vdup.32 d9, r1 937; CHECK-NEON-NEXT: vdup.32 d8, r0 938; CHECK-NEON-NEXT: mov r0, r2 939; CHECK-NEON-NEXT: bl __aeabi_h2f 940; CHECK-NEON-NEXT: vmov.i64 q5, #0xffffffff 941; CHECK-NEON-NEXT: vbsl q4, q6, q5 942; CHECK-NEON-NEXT: bl __aeabi_f2lz 943; CHECK-NEON-NEXT: mov r5, r0 944; CHECK-NEON-NEXT: vmov.32 d13[0], r0 945; CHECK-NEON-NEXT: mov r0, r8 946; CHECK-NEON-NEXT: mov r6, r1 947; CHECK-NEON-NEXT: vmov r4, r10, d8 948; CHECK-NEON-NEXT: bl __aeabi_h2f 949; CHECK-NEON-NEXT: bl __aeabi_f2lz 950; CHECK-NEON-NEXT: subs r2, r5, r9 951; CHECK-NEON-NEXT: vmov.32 d12[0], r0 952; CHECK-NEON-NEXT: sbcs r2, r6, #0 953; CHECK-NEON-NEXT: mov r2, #0 954; CHECK-NEON-NEXT: vmov.32 d13[1], r6 955; CHECK-NEON-NEXT: movwlt r2, #1 956; CHECK-NEON-NEXT: cmp r2, #0 957; CHECK-NEON-NEXT: mvnne r2, #0 958; CHECK-NEON-NEXT: subs r0, r0, r9 959; CHECK-NEON-NEXT: sbcs r0, r1, #0 960; CHECK-NEON-NEXT: vdup.32 d17, r2 961; CHECK-NEON-NEXT: mov r0, #0 962; CHECK-NEON-NEXT: vmov.32 d12[1], r1 963; CHECK-NEON-NEXT: movwlt r0, #1 964; CHECK-NEON-NEXT: cmp r0, #0 965; CHECK-NEON-NEXT: mvnne r0, #0 966; CHECK-NEON-NEXT: vmov r2, r3, d9 967; CHECK-NEON-NEXT: vdup.32 d16, r0 968; CHECK-NEON-NEXT: rsbs r6, r4, #0 969; CHECK-NEON-NEXT: vbsl q8, q6, q5 970; CHECK-NEON-NEXT: rscs r6, r10, #0 971; CHECK-NEON-NEXT: mov r6, #0 972; CHECK-NEON-NEXT: movwlt r6, #1 973; CHECK-NEON-NEXT: cmp r6, #0 974; CHECK-NEON-NEXT: vmov r0, r1, d17 975; CHECK-NEON-NEXT: mvnne r6, #0 976; CHECK-NEON-NEXT: vmov r5, r4, d16 977; CHECK-NEON-NEXT: rsbs r0, r0, #0 978; CHECK-NEON-NEXT: rscs r0, r1, #0 979; CHECK-NEON-NEXT: mov r0, #0 980; CHECK-NEON-NEXT: movwlt r0, #1 981; CHECK-NEON-NEXT: cmp r0, #0 982; CHECK-NEON-NEXT: mvnne r0, #0 983; CHECK-NEON-NEXT: rsbs r1, r2, #0 984; CHECK-NEON-NEXT: rscs r1, r3, #0 985; CHECK-NEON-NEXT: vmov.32 d19[0], r0 986; CHECK-NEON-NEXT: mov r1, #0 987; CHECK-NEON-NEXT: movwlt r1, #1 988; CHECK-NEON-NEXT: cmp r1, #0 989; CHECK-NEON-NEXT: mvnne r1, #0 990; CHECK-NEON-NEXT: rsbs r0, r5, #0 991; CHECK-NEON-NEXT: rscs r0, r4, #0 992; CHECK-NEON-NEXT: vmov.32 d21[0], r1 993; CHECK-NEON-NEXT: movwlt r7, #1 994; CHECK-NEON-NEXT: cmp r7, #0 995; CHECK-NEON-NEXT: vmov.32 d20[0], r6 996; CHECK-NEON-NEXT: mvnne r7, #0 997; CHECK-NEON-NEXT: vmov.32 d18[0], r7 998; CHECK-NEON-NEXT: vand q10, q4, q10 999; CHECK-NEON-NEXT: vand q8, q8, q9 1000; CHECK-NEON-NEXT: vmovn.i64 d1, q10 1001; CHECK-NEON-NEXT: vmovn.i64 d0, q8 1002; CHECK-NEON-NEXT: vpop {d8, d9, d10, d11, d12, d13} 1003; CHECK-NEON-NEXT: pop {r4, r5, r6, r7, r8, r9, r10, pc} 1004; 1005; CHECK-FP16-LABEL: ustest_f16i32: 1006; CHECK-FP16: @ %bb.0: @ %entry 1007; CHECK-FP16-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, lr} 1008; CHECK-FP16-NEXT: push {r4, r5, r6, r7, r8, r9, r10, lr} 1009; CHECK-FP16-NEXT: .vsave {d8, d9, d10, d11, d12, d13} 1010; CHECK-FP16-NEXT: vpush {d8, d9, d10, d11, d12, d13} 1011; CHECK-FP16-NEXT: vmov.u16 r0, d0[3] 1012; CHECK-FP16-NEXT: vorr d8, d0, d0 1013; CHECK-FP16-NEXT: vmov.u16 r8, d0[0] 1014; CHECK-FP16-NEXT: vmov.u16 r9, d0[1] 1015; CHECK-FP16-NEXT: vmov s0, r0 1016; CHECK-FP16-NEXT: bl __fixhfdi 1017; CHECK-FP16-NEXT: mov r4, r0 1018; CHECK-FP16-NEXT: vmov.u16 r0, d8[2] 1019; CHECK-FP16-NEXT: mov r5, r1 1020; CHECK-FP16-NEXT: vmov.32 d9[0], r4 1021; CHECK-FP16-NEXT: vmov s0, r0 1022; CHECK-FP16-NEXT: bl __fixhfdi 1023; CHECK-FP16-NEXT: mvn r10, #0 1024; CHECK-FP16-NEXT: subs r2, r4, r10 1025; CHECK-FP16-NEXT: sbcs r2, r5, #0 1026; CHECK-FP16-NEXT: vmov.32 d8[0], r0 1027; CHECK-FP16-NEXT: mov r2, #0 1028; CHECK-FP16-NEXT: vmov s0, r9 1029; CHECK-FP16-NEXT: movwlt r2, #1 1030; CHECK-FP16-NEXT: cmp r2, #0 1031; CHECK-FP16-NEXT: mvnne r2, #0 1032; CHECK-FP16-NEXT: subs r0, r0, r10 1033; CHECK-FP16-NEXT: sbcs r0, r1, #0 1034; CHECK-FP16-NEXT: vmov.32 d9[1], r5 1035; CHECK-FP16-NEXT: mov r0, #0 1036; CHECK-FP16-NEXT: vmov.i64 q5, #0xffffffff 1037; CHECK-FP16-NEXT: movwlt r0, #1 1038; CHECK-FP16-NEXT: cmp r0, #0 1039; CHECK-FP16-NEXT: vmov.32 d8[1], r1 1040; CHECK-FP16-NEXT: mvnne r0, #0 1041; CHECK-FP16-NEXT: mov r6, #0 1042; CHECK-FP16-NEXT: vdup.32 d17, r2 1043; CHECK-FP16-NEXT: vdup.32 d16, r0 1044; CHECK-FP16-NEXT: vbif q4, q5, q8 1045; CHECK-FP16-NEXT: bl __fixhfdi 1046; CHECK-FP16-NEXT: vmov s0, r8 1047; CHECK-FP16-NEXT: mov r4, r0 1048; CHECK-FP16-NEXT: mov r5, r1 1049; CHECK-FP16-NEXT: vmov.32 d13[0], r0 1050; CHECK-FP16-NEXT: vmov r7, r8, d8 1051; CHECK-FP16-NEXT: bl __fixhfdi 1052; CHECK-FP16-NEXT: subs r2, r4, r10 1053; CHECK-FP16-NEXT: vmov.32 d12[0], r0 1054; CHECK-FP16-NEXT: sbcs r2, r5, #0 1055; CHECK-FP16-NEXT: mov r2, #0 1056; CHECK-FP16-NEXT: vmov.32 d13[1], r5 1057; CHECK-FP16-NEXT: movwlt r2, #1 1058; CHECK-FP16-NEXT: cmp r2, #0 1059; CHECK-FP16-NEXT: mvnne r2, #0 1060; CHECK-FP16-NEXT: subs r0, r0, r10 1061; CHECK-FP16-NEXT: sbcs r0, r1, #0 1062; CHECK-FP16-NEXT: vdup.32 d17, r2 1063; CHECK-FP16-NEXT: mov r0, #0 1064; CHECK-FP16-NEXT: vmov.32 d12[1], r1 1065; CHECK-FP16-NEXT: movwlt r0, #1 1066; CHECK-FP16-NEXT: cmp r0, #0 1067; CHECK-FP16-NEXT: mvnne r0, #0 1068; CHECK-FP16-NEXT: vmov r2, r3, d9 1069; CHECK-FP16-NEXT: vdup.32 d16, r0 1070; CHECK-FP16-NEXT: rsbs r7, r7, #0 1071; CHECK-FP16-NEXT: vbsl q8, q6, q5 1072; CHECK-FP16-NEXT: rscs r7, r8, #0 1073; CHECK-FP16-NEXT: mov r7, #0 1074; CHECK-FP16-NEXT: movwlt r7, #1 1075; CHECK-FP16-NEXT: cmp r7, #0 1076; CHECK-FP16-NEXT: vmov r0, r1, d17 1077; CHECK-FP16-NEXT: mvnne r7, #0 1078; CHECK-FP16-NEXT: vmov r5, r4, d16 1079; CHECK-FP16-NEXT: rsbs r0, r0, #0 1080; CHECK-FP16-NEXT: rscs r0, r1, #0 1081; CHECK-FP16-NEXT: mov r0, #0 1082; CHECK-FP16-NEXT: movwlt r0, #1 1083; CHECK-FP16-NEXT: cmp r0, #0 1084; CHECK-FP16-NEXT: mvnne r0, #0 1085; CHECK-FP16-NEXT: rsbs r1, r2, #0 1086; CHECK-FP16-NEXT: rscs r1, r3, #0 1087; CHECK-FP16-NEXT: vmov.32 d19[0], r0 1088; CHECK-FP16-NEXT: mov r1, #0 1089; CHECK-FP16-NEXT: movwlt r1, #1 1090; CHECK-FP16-NEXT: cmp r1, #0 1091; CHECK-FP16-NEXT: mvnne r1, #0 1092; CHECK-FP16-NEXT: rsbs r0, r5, #0 1093; CHECK-FP16-NEXT: rscs r0, r4, #0 1094; CHECK-FP16-NEXT: vmov.32 d21[0], r1 1095; CHECK-FP16-NEXT: movwlt r6, #1 1096; CHECK-FP16-NEXT: cmp r6, #0 1097; CHECK-FP16-NEXT: vmov.32 d20[0], r7 1098; CHECK-FP16-NEXT: mvnne r6, #0 1099; CHECK-FP16-NEXT: vmov.32 d18[0], r6 1100; CHECK-FP16-NEXT: vand q10, q4, q10 1101; CHECK-FP16-NEXT: vand q8, q8, q9 1102; CHECK-FP16-NEXT: vmovn.i64 d1, q10 1103; CHECK-FP16-NEXT: vmovn.i64 d0, q8 1104; CHECK-FP16-NEXT: vpop {d8, d9, d10, d11, d12, d13} 1105; CHECK-FP16-NEXT: pop {r4, r5, r6, r7, r8, r9, r10, pc} 1106entry: 1107 %conv = fptosi <4 x half> %x to <4 x i64> 1108 %0 = icmp slt <4 x i64> %conv, <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295> 1109 %spec.store.select = select <4 x i1> %0, <4 x i64> %conv, <4 x i64> <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295> 1110 %1 = icmp sgt <4 x i64> %spec.store.select, zeroinitializer 1111 %spec.store.select7 = select <4 x i1> %1, <4 x i64> %spec.store.select, <4 x i64> zeroinitializer 1112 %conv6 = trunc <4 x i64> %spec.store.select7 to <4 x i32> 1113 ret <4 x i32> %conv6 1114} 1115 1116; i16 saturate 1117 1118define <2 x i16> @stest_f64i16(<2 x double> %x) { 1119; CHECK-LABEL: stest_f64i16: 1120; CHECK: @ %bb.0: @ %entry 1121; CHECK-NEXT: vcvt.s32.f64 s4, d0 1122; CHECK-NEXT: vmov r0, s4 1123; CHECK-NEXT: vcvt.s32.f64 s0, d1 1124; CHECK-NEXT: vmov.i32 d17, #0x7fff 1125; CHECK-NEXT: vmvn.i32 d18, #0x7fff 1126; CHECK-NEXT: vmov.32 d16[0], r0 1127; CHECK-NEXT: vmov r0, s0 1128; CHECK-NEXT: vmov.32 d16[1], r0 1129; CHECK-NEXT: vmin.s32 d16, d16, d17 1130; CHECK-NEXT: vmax.s32 d0, d16, d18 1131; CHECK-NEXT: bx lr 1132entry: 1133 %conv = fptosi <2 x double> %x to <2 x i32> 1134 %0 = icmp slt <2 x i32> %conv, <i32 32767, i32 32767> 1135 %spec.store.select = select <2 x i1> %0, <2 x i32> %conv, <2 x i32> <i32 32767, i32 32767> 1136 %1 = icmp sgt <2 x i32> %spec.store.select, <i32 -32768, i32 -32768> 1137 %spec.store.select7 = select <2 x i1> %1, <2 x i32> %spec.store.select, <2 x i32> <i32 -32768, i32 -32768> 1138 %conv6 = trunc <2 x i32> %spec.store.select7 to <2 x i16> 1139 ret <2 x i16> %conv6 1140} 1141 1142define <2 x i16> @utest_f64i16(<2 x double> %x) { 1143; CHECK-LABEL: utest_f64i16: 1144; CHECK: @ %bb.0: @ %entry 1145; CHECK-NEXT: vcvt.u32.f64 s4, d0 1146; CHECK-NEXT: vmov r0, s4 1147; CHECK-NEXT: vcvt.u32.f64 s0, d1 1148; CHECK-NEXT: vmov.i32 d17, #0xffff 1149; CHECK-NEXT: vmov.32 d16[0], r0 1150; CHECK-NEXT: vmov r0, s0 1151; CHECK-NEXT: vmov.32 d16[1], r0 1152; CHECK-NEXT: vmin.u32 d0, d16, d17 1153; CHECK-NEXT: bx lr 1154entry: 1155 %conv = fptoui <2 x double> %x to <2 x i32> 1156 %0 = icmp ult <2 x i32> %conv, <i32 65535, i32 65535> 1157 %spec.store.select = select <2 x i1> %0, <2 x i32> %conv, <2 x i32> <i32 65535, i32 65535> 1158 %conv6 = trunc <2 x i32> %spec.store.select to <2 x i16> 1159 ret <2 x i16> %conv6 1160} 1161 1162define <2 x i16> @ustest_f64i16(<2 x double> %x) { 1163; CHECK-LABEL: ustest_f64i16: 1164; CHECK: @ %bb.0: @ %entry 1165; CHECK-NEXT: vcvt.s32.f64 s4, d0 1166; CHECK-NEXT: vmov r0, s4 1167; CHECK-NEXT: vcvt.s32.f64 s0, d1 1168; CHECK-NEXT: vmov.i32 d17, #0xffff 1169; CHECK-NEXT: vmov.i32 d18, #0x0 1170; CHECK-NEXT: vmov.32 d16[0], r0 1171; CHECK-NEXT: vmov r0, s0 1172; CHECK-NEXT: vmov.32 d16[1], r0 1173; CHECK-NEXT: vmin.s32 d16, d16, d17 1174; CHECK-NEXT: vmax.s32 d0, d16, d18 1175; CHECK-NEXT: bx lr 1176entry: 1177 %conv = fptosi <2 x double> %x to <2 x i32> 1178 %0 = icmp slt <2 x i32> %conv, <i32 65535, i32 65535> 1179 %spec.store.select = select <2 x i1> %0, <2 x i32> %conv, <2 x i32> <i32 65535, i32 65535> 1180 %1 = icmp sgt <2 x i32> %spec.store.select, zeroinitializer 1181 %spec.store.select7 = select <2 x i1> %1, <2 x i32> %spec.store.select, <2 x i32> zeroinitializer 1182 %conv6 = trunc <2 x i32> %spec.store.select7 to <2 x i16> 1183 ret <2 x i16> %conv6 1184} 1185 1186define <4 x i16> @stest_f32i16(<4 x float> %x) { 1187; CHECK-LABEL: stest_f32i16: 1188; CHECK: @ %bb.0: @ %entry 1189; CHECK-NEXT: vcvt.s32.f32 q8, q0 1190; CHECK-NEXT: vmov.i32 q9, #0x7fff 1191; CHECK-NEXT: vmvn.i32 q10, #0x7fff 1192; CHECK-NEXT: vmin.s32 q8, q8, q9 1193; CHECK-NEXT: vmax.s32 q8, q8, q10 1194; CHECK-NEXT: vmovn.i32 d0, q8 1195; CHECK-NEXT: bx lr 1196entry: 1197 %conv = fptosi <4 x float> %x to <4 x i32> 1198 %0 = icmp slt <4 x i32> %conv, <i32 32767, i32 32767, i32 32767, i32 32767> 1199 %spec.store.select = select <4 x i1> %0, <4 x i32> %conv, <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767> 1200 %1 = icmp sgt <4 x i32> %spec.store.select, <i32 -32768, i32 -32768, i32 -32768, i32 -32768> 1201 %spec.store.select7 = select <4 x i1> %1, <4 x i32> %spec.store.select, <4 x i32> <i32 -32768, i32 -32768, i32 -32768, i32 -32768> 1202 %conv6 = trunc <4 x i32> %spec.store.select7 to <4 x i16> 1203 ret <4 x i16> %conv6 1204} 1205 1206define <4 x i16> @utest_f32i16(<4 x float> %x) { 1207; CHECK-LABEL: utest_f32i16: 1208; CHECK: @ %bb.0: @ %entry 1209; CHECK-NEXT: vcvt.u32.f32 q8, q0 1210; CHECK-NEXT: vmov.i32 q9, #0xffff 1211; CHECK-NEXT: vmin.u32 q8, q8, q9 1212; CHECK-NEXT: vmovn.i32 d0, q8 1213; CHECK-NEXT: bx lr 1214entry: 1215 %conv = fptoui <4 x float> %x to <4 x i32> 1216 %0 = icmp ult <4 x i32> %conv, <i32 65535, i32 65535, i32 65535, i32 65535> 1217 %spec.store.select = select <4 x i1> %0, <4 x i32> %conv, <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535> 1218 %conv6 = trunc <4 x i32> %spec.store.select to <4 x i16> 1219 ret <4 x i16> %conv6 1220} 1221 1222define <4 x i16> @ustest_f32i16(<4 x float> %x) { 1223; CHECK-LABEL: ustest_f32i16: 1224; CHECK: @ %bb.0: @ %entry 1225; CHECK-NEXT: vcvt.s32.f32 q8, q0 1226; CHECK-NEXT: vmov.i32 q9, #0xffff 1227; CHECK-NEXT: vmov.i32 q10, #0x0 1228; CHECK-NEXT: vmin.s32 q8, q8, q9 1229; CHECK-NEXT: vmax.s32 q8, q8, q10 1230; CHECK-NEXT: vmovn.i32 d0, q8 1231; CHECK-NEXT: bx lr 1232entry: 1233 %conv = fptosi <4 x float> %x to <4 x i32> 1234 %0 = icmp slt <4 x i32> %conv, <i32 65535, i32 65535, i32 65535, i32 65535> 1235 %spec.store.select = select <4 x i1> %0, <4 x i32> %conv, <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535> 1236 %1 = icmp sgt <4 x i32> %spec.store.select, zeroinitializer 1237 %spec.store.select7 = select <4 x i1> %1, <4 x i32> %spec.store.select, <4 x i32> zeroinitializer 1238 %conv6 = trunc <4 x i32> %spec.store.select7 to <4 x i16> 1239 ret <4 x i16> %conv6 1240} 1241 1242define <8 x i16> @stest_f16i16(<8 x half> %x) { 1243; CHECK-NEON-LABEL: stest_f16i16: 1244; CHECK-NEON: @ %bb.0: @ %entry 1245; CHECK-NEON-NEXT: .save {r4, r5, r6, r7, r11, lr} 1246; CHECK-NEON-NEXT: push {r4, r5, r6, r7, r11, lr} 1247; CHECK-NEON-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} 1248; CHECK-NEON-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} 1249; CHECK-NEON-NEXT: vmov r0, s1 1250; CHECK-NEON-NEXT: vmov.f32 s16, s7 1251; CHECK-NEON-NEXT: vmov.f32 s18, s6 1252; CHECK-NEON-NEXT: vmov.f32 s20, s5 1253; CHECK-NEON-NEXT: vmov.f32 s22, s4 1254; CHECK-NEON-NEXT: vmov.f32 s24, s3 1255; CHECK-NEON-NEXT: vmov.f32 s26, s2 1256; CHECK-NEON-NEXT: vmov.f32 s28, s0 1257; CHECK-NEON-NEXT: bl __aeabi_h2f 1258; CHECK-NEON-NEXT: mov r4, r0 1259; CHECK-NEON-NEXT: vmov r0, s26 1260; CHECK-NEON-NEXT: bl __aeabi_h2f 1261; CHECK-NEON-NEXT: mov r5, r0 1262; CHECK-NEON-NEXT: vmov r0, s22 1263; CHECK-NEON-NEXT: bl __aeabi_h2f 1264; CHECK-NEON-NEXT: mov r6, r0 1265; CHECK-NEON-NEXT: vmov r0, s24 1266; CHECK-NEON-NEXT: bl __aeabi_h2f 1267; CHECK-NEON-NEXT: mov r7, r0 1268; CHECK-NEON-NEXT: vmov r0, s18 1269; CHECK-NEON-NEXT: bl __aeabi_h2f 1270; CHECK-NEON-NEXT: vmov s0, r0 1271; CHECK-NEON-NEXT: vcvt.s32.f32 s0, s0 1272; CHECK-NEON-NEXT: vmov r0, s0 1273; CHECK-NEON-NEXT: vmov.32 d13[0], r0 1274; CHECK-NEON-NEXT: vmov r0, s16 1275; CHECK-NEON-NEXT: bl __aeabi_h2f 1276; CHECK-NEON-NEXT: vmov s0, r0 1277; CHECK-NEON-NEXT: vmov s22, r7 1278; CHECK-NEON-NEXT: vcvt.s32.f32 s0, s0 1279; CHECK-NEON-NEXT: vmov s30, r6 1280; CHECK-NEON-NEXT: vmov r0, s0 1281; CHECK-NEON-NEXT: vmov.32 d13[1], r0 1282; CHECK-NEON-NEXT: vmov r0, s28 1283; CHECK-NEON-NEXT: bl __aeabi_h2f 1284; CHECK-NEON-NEXT: vmov s0, r0 1285; CHECK-NEON-NEXT: vmov r1, s20 1286; CHECK-NEON-NEXT: vcvt.s32.f32 s0, s0 1287; CHECK-NEON-NEXT: vmov s2, r5 1288; CHECK-NEON-NEXT: vcvt.s32.f32 s20, s2 1289; CHECK-NEON-NEXT: vmov r0, s0 1290; CHECK-NEON-NEXT: vcvt.s32.f32 s0, s30 1291; CHECK-NEON-NEXT: vmov.32 d8[0], r0 1292; CHECK-NEON-NEXT: vmov r0, s0 1293; CHECK-NEON-NEXT: vmov.32 d12[0], r0 1294; CHECK-NEON-NEXT: mov r0, r1 1295; CHECK-NEON-NEXT: bl __aeabi_h2f 1296; CHECK-NEON-NEXT: vmov s0, r0 1297; CHECK-NEON-NEXT: vmov r0, s20 1298; CHECK-NEON-NEXT: vcvt.s32.f32 s0, s0 1299; CHECK-NEON-NEXT: vmov s2, r4 1300; CHECK-NEON-NEXT: vmov.i32 q8, #0x7fff 1301; CHECK-NEON-NEXT: vcvt.s32.f32 s2, s2 1302; CHECK-NEON-NEXT: vmvn.i32 q9, #0x7fff 1303; CHECK-NEON-NEXT: vmov.32 d9[0], r0 1304; CHECK-NEON-NEXT: vmov r0, s0 1305; CHECK-NEON-NEXT: vcvt.s32.f32 s0, s22 1306; CHECK-NEON-NEXT: vmov.32 d12[1], r0 1307; CHECK-NEON-NEXT: vmov r0, s0 1308; CHECK-NEON-NEXT: vmin.s32 q10, q6, q8 1309; CHECK-NEON-NEXT: vmax.s32 q10, q10, q9 1310; CHECK-NEON-NEXT: vmov.32 d9[1], r0 1311; CHECK-NEON-NEXT: vmov r0, s2 1312; CHECK-NEON-NEXT: vmovn.i32 d1, q10 1313; CHECK-NEON-NEXT: vmov.32 d8[1], r0 1314; CHECK-NEON-NEXT: vmin.s32 q8, q4, q8 1315; CHECK-NEON-NEXT: vmax.s32 q8, q8, q9 1316; CHECK-NEON-NEXT: vmovn.i32 d0, q8 1317; CHECK-NEON-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15} 1318; CHECK-NEON-NEXT: pop {r4, r5, r6, r7, r11, pc} 1319; 1320; CHECK-FP16-LABEL: stest_f16i16: 1321; CHECK-FP16: @ %bb.0: @ %entry 1322; CHECK-FP16-NEXT: vmovx.f16 s4, s0 1323; CHECK-FP16-NEXT: vcvt.s32.f16 s12, s0 1324; CHECK-FP16-NEXT: vcvt.s32.f16 s0, s3 1325; CHECK-FP16-NEXT: vcvt.s32.f16 s5, s2 1326; CHECK-FP16-NEXT: vmov r0, s0 1327; CHECK-FP16-NEXT: vcvt.s32.f16 s14, s1 1328; CHECK-FP16-NEXT: vmovx.f16 s10, s3 1329; CHECK-FP16-NEXT: vmovx.f16 s8, s2 1330; CHECK-FP16-NEXT: vcvt.s32.f16 s10, s10 1331; CHECK-FP16-NEXT: vcvt.s32.f16 s8, s8 1332; CHECK-FP16-NEXT: vmovx.f16 s6, s1 1333; CHECK-FP16-NEXT: vcvt.s32.f16 s4, s4 1334; CHECK-FP16-NEXT: vcvt.s32.f16 s6, s6 1335; CHECK-FP16-NEXT: vmov.i32 q10, #0x7fff 1336; CHECK-FP16-NEXT: vmvn.i32 q11, #0x7fff 1337; CHECK-FP16-NEXT: vmov.32 d17[0], r0 1338; CHECK-FP16-NEXT: vmov r0, s5 1339; CHECK-FP16-NEXT: vmov.32 d16[0], r0 1340; CHECK-FP16-NEXT: vmov r0, s14 1341; CHECK-FP16-NEXT: vmov.32 d19[0], r0 1342; CHECK-FP16-NEXT: vmov r0, s12 1343; CHECK-FP16-NEXT: vmov.32 d18[0], r0 1344; CHECK-FP16-NEXT: vmov r0, s10 1345; CHECK-FP16-NEXT: vmov.32 d17[1], r0 1346; CHECK-FP16-NEXT: vmov r0, s8 1347; CHECK-FP16-NEXT: vmov.32 d16[1], r0 1348; CHECK-FP16-NEXT: vmov r0, s6 1349; CHECK-FP16-NEXT: vmin.s32 q8, q8, q10 1350; CHECK-FP16-NEXT: vmax.s32 q8, q8, q11 1351; CHECK-FP16-NEXT: vmovn.i32 d1, q8 1352; CHECK-FP16-NEXT: vmov.32 d19[1], r0 1353; CHECK-FP16-NEXT: vmov r0, s4 1354; CHECK-FP16-NEXT: vmov.32 d18[1], r0 1355; CHECK-FP16-NEXT: vmin.s32 q9, q9, q10 1356; CHECK-FP16-NEXT: vmax.s32 q9, q9, q11 1357; CHECK-FP16-NEXT: vmovn.i32 d0, q9 1358; CHECK-FP16-NEXT: bx lr 1359entry: 1360 %conv = fptosi <8 x half> %x to <8 x i32> 1361 %0 = icmp slt <8 x i32> %conv, <i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767> 1362 %spec.store.select = select <8 x i1> %0, <8 x i32> %conv, <8 x i32> <i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767> 1363 %1 = icmp sgt <8 x i32> %spec.store.select, <i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768> 1364 %spec.store.select7 = select <8 x i1> %1, <8 x i32> %spec.store.select, <8 x i32> <i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768> 1365 %conv6 = trunc <8 x i32> %spec.store.select7 to <8 x i16> 1366 ret <8 x i16> %conv6 1367} 1368 1369define <8 x i16> @utesth_f16i16(<8 x half> %x) { 1370; CHECK-NEON-LABEL: utesth_f16i16: 1371; CHECK-NEON: @ %bb.0: @ %entry 1372; CHECK-NEON-NEXT: .save {r4, r5, r6, r7, r11, lr} 1373; CHECK-NEON-NEXT: push {r4, r5, r6, r7, r11, lr} 1374; CHECK-NEON-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14} 1375; CHECK-NEON-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14} 1376; CHECK-NEON-NEXT: vmov r0, s1 1377; CHECK-NEON-NEXT: vmov.f32 s16, s7 1378; CHECK-NEON-NEXT: vmov.f32 s18, s6 1379; CHECK-NEON-NEXT: vmov.f32 s20, s5 1380; CHECK-NEON-NEXT: vmov.f32 s22, s4 1381; CHECK-NEON-NEXT: vmov.f32 s24, s3 1382; CHECK-NEON-NEXT: vmov.f32 s26, s2 1383; CHECK-NEON-NEXT: vmov.f32 s28, s0 1384; CHECK-NEON-NEXT: bl __aeabi_h2f 1385; CHECK-NEON-NEXT: mov r4, r0 1386; CHECK-NEON-NEXT: vmov r0, s26 1387; CHECK-NEON-NEXT: bl __aeabi_h2f 1388; CHECK-NEON-NEXT: mov r5, r0 1389; CHECK-NEON-NEXT: vmov r0, s22 1390; CHECK-NEON-NEXT: bl __aeabi_h2f 1391; CHECK-NEON-NEXT: mov r6, r0 1392; CHECK-NEON-NEXT: vmov r0, s24 1393; CHECK-NEON-NEXT: bl __aeabi_h2f 1394; CHECK-NEON-NEXT: mov r7, r0 1395; CHECK-NEON-NEXT: vmov r0, s18 1396; CHECK-NEON-NEXT: bl __aeabi_h2f 1397; CHECK-NEON-NEXT: vmov s0, r0 1398; CHECK-NEON-NEXT: vcvt.u32.f32 s0, s0 1399; CHECK-NEON-NEXT: vmov r0, s0 1400; CHECK-NEON-NEXT: vmov.32 d13[0], r0 1401; CHECK-NEON-NEXT: vmov r0, s16 1402; CHECK-NEON-NEXT: bl __aeabi_h2f 1403; CHECK-NEON-NEXT: vmov s0, r0 1404; CHECK-NEON-NEXT: vmov s16, r7 1405; CHECK-NEON-NEXT: vcvt.u32.f32 s0, s0 1406; CHECK-NEON-NEXT: vmov s18, r6 1407; CHECK-NEON-NEXT: vmov r0, s0 1408; CHECK-NEON-NEXT: vmov.32 d13[1], r0 1409; CHECK-NEON-NEXT: vmov r0, s28 1410; CHECK-NEON-NEXT: bl __aeabi_h2f 1411; CHECK-NEON-NEXT: vmov s0, r0 1412; CHECK-NEON-NEXT: vmov r1, s20 1413; CHECK-NEON-NEXT: vcvt.u32.f32 s0, s0 1414; CHECK-NEON-NEXT: vmov s2, r5 1415; CHECK-NEON-NEXT: vmov r0, s0 1416; CHECK-NEON-NEXT: vcvt.u32.f32 s0, s18 1417; CHECK-NEON-NEXT: vcvt.u32.f32 s18, s2 1418; CHECK-NEON-NEXT: vmov.32 d10[0], r0 1419; CHECK-NEON-NEXT: vmov r0, s0 1420; CHECK-NEON-NEXT: vmov.32 d12[0], r0 1421; CHECK-NEON-NEXT: mov r0, r1 1422; CHECK-NEON-NEXT: bl __aeabi_h2f 1423; CHECK-NEON-NEXT: vmov s0, r0 1424; CHECK-NEON-NEXT: vmov r0, s18 1425; CHECK-NEON-NEXT: vcvt.u32.f32 s0, s0 1426; CHECK-NEON-NEXT: vmov s2, r4 1427; CHECK-NEON-NEXT: vmov.i32 q8, #0xffff 1428; CHECK-NEON-NEXT: vcvt.u32.f32 s2, s2 1429; CHECK-NEON-NEXT: vmov.32 d11[0], r0 1430; CHECK-NEON-NEXT: vmov r0, s0 1431; CHECK-NEON-NEXT: vcvt.u32.f32 s0, s16 1432; CHECK-NEON-NEXT: vmov.32 d12[1], r0 1433; CHECK-NEON-NEXT: vmov r0, s0 1434; CHECK-NEON-NEXT: vmin.u32 q9, q6, q8 1435; CHECK-NEON-NEXT: vmov.32 d11[1], r0 1436; CHECK-NEON-NEXT: vmov r0, s2 1437; CHECK-NEON-NEXT: vmovn.i32 d1, q9 1438; CHECK-NEON-NEXT: vmov.32 d10[1], r0 1439; CHECK-NEON-NEXT: vmin.u32 q8, q5, q8 1440; CHECK-NEON-NEXT: vmovn.i32 d0, q8 1441; CHECK-NEON-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14} 1442; CHECK-NEON-NEXT: pop {r4, r5, r6, r7, r11, pc} 1443; 1444; CHECK-FP16-LABEL: utesth_f16i16: 1445; CHECK-FP16: @ %bb.0: @ %entry 1446; CHECK-FP16-NEXT: vmovx.f16 s4, s0 1447; CHECK-FP16-NEXT: vcvt.u32.f16 s12, s0 1448; CHECK-FP16-NEXT: vcvt.u32.f16 s0, s3 1449; CHECK-FP16-NEXT: vcvt.u32.f16 s5, s2 1450; CHECK-FP16-NEXT: vmov r0, s0 1451; CHECK-FP16-NEXT: vcvt.u32.f16 s14, s1 1452; CHECK-FP16-NEXT: vmovx.f16 s10, s3 1453; CHECK-FP16-NEXT: vmovx.f16 s8, s2 1454; CHECK-FP16-NEXT: vcvt.u32.f16 s10, s10 1455; CHECK-FP16-NEXT: vcvt.u32.f16 s8, s8 1456; CHECK-FP16-NEXT: vmovx.f16 s6, s1 1457; CHECK-FP16-NEXT: vcvt.u32.f16 s4, s4 1458; CHECK-FP16-NEXT: vcvt.u32.f16 s6, s6 1459; CHECK-FP16-NEXT: vmov.i32 q10, #0xffff 1460; CHECK-FP16-NEXT: vmov.32 d17[0], r0 1461; CHECK-FP16-NEXT: vmov r0, s5 1462; CHECK-FP16-NEXT: vmov.32 d16[0], r0 1463; CHECK-FP16-NEXT: vmov r0, s14 1464; CHECK-FP16-NEXT: vmov.32 d19[0], r0 1465; CHECK-FP16-NEXT: vmov r0, s12 1466; CHECK-FP16-NEXT: vmov.32 d18[0], r0 1467; CHECK-FP16-NEXT: vmov r0, s10 1468; CHECK-FP16-NEXT: vmov.32 d17[1], r0 1469; CHECK-FP16-NEXT: vmov r0, s8 1470; CHECK-FP16-NEXT: vmov.32 d16[1], r0 1471; CHECK-FP16-NEXT: vmov r0, s6 1472; CHECK-FP16-NEXT: vmin.u32 q8, q8, q10 1473; CHECK-FP16-NEXT: vmovn.i32 d1, q8 1474; CHECK-FP16-NEXT: vmov.32 d19[1], r0 1475; CHECK-FP16-NEXT: vmov r0, s4 1476; CHECK-FP16-NEXT: vmov.32 d18[1], r0 1477; CHECK-FP16-NEXT: vmin.u32 q9, q9, q10 1478; CHECK-FP16-NEXT: vmovn.i32 d0, q9 1479; CHECK-FP16-NEXT: bx lr 1480entry: 1481 %conv = fptoui <8 x half> %x to <8 x i32> 1482 %0 = icmp ult <8 x i32> %conv, <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535> 1483 %spec.store.select = select <8 x i1> %0, <8 x i32> %conv, <8 x i32> <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535> 1484 %conv6 = trunc <8 x i32> %spec.store.select to <8 x i16> 1485 ret <8 x i16> %conv6 1486} 1487 1488define <8 x i16> @ustest_f16i16(<8 x half> %x) { 1489; CHECK-NEON-LABEL: ustest_f16i16: 1490; CHECK-NEON: @ %bb.0: @ %entry 1491; CHECK-NEON-NEXT: .save {r4, r5, r6, r7, r11, lr} 1492; CHECK-NEON-NEXT: push {r4, r5, r6, r7, r11, lr} 1493; CHECK-NEON-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} 1494; CHECK-NEON-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} 1495; CHECK-NEON-NEXT: vmov r0, s1 1496; CHECK-NEON-NEXT: vmov.f32 s16, s7 1497; CHECK-NEON-NEXT: vmov.f32 s18, s6 1498; CHECK-NEON-NEXT: vmov.f32 s20, s5 1499; CHECK-NEON-NEXT: vmov.f32 s22, s4 1500; CHECK-NEON-NEXT: vmov.f32 s24, s3 1501; CHECK-NEON-NEXT: vmov.f32 s26, s2 1502; CHECK-NEON-NEXT: vmov.f32 s28, s0 1503; CHECK-NEON-NEXT: bl __aeabi_h2f 1504; CHECK-NEON-NEXT: mov r4, r0 1505; CHECK-NEON-NEXT: vmov r0, s26 1506; CHECK-NEON-NEXT: bl __aeabi_h2f 1507; CHECK-NEON-NEXT: mov r5, r0 1508; CHECK-NEON-NEXT: vmov r0, s22 1509; CHECK-NEON-NEXT: bl __aeabi_h2f 1510; CHECK-NEON-NEXT: mov r6, r0 1511; CHECK-NEON-NEXT: vmov r0, s24 1512; CHECK-NEON-NEXT: bl __aeabi_h2f 1513; CHECK-NEON-NEXT: mov r7, r0 1514; CHECK-NEON-NEXT: vmov r0, s18 1515; CHECK-NEON-NEXT: bl __aeabi_h2f 1516; CHECK-NEON-NEXT: vmov s0, r0 1517; CHECK-NEON-NEXT: vcvt.s32.f32 s0, s0 1518; CHECK-NEON-NEXT: vmov r0, s0 1519; CHECK-NEON-NEXT: vmov.32 d13[0], r0 1520; CHECK-NEON-NEXT: vmov r0, s16 1521; CHECK-NEON-NEXT: bl __aeabi_h2f 1522; CHECK-NEON-NEXT: vmov s0, r0 1523; CHECK-NEON-NEXT: vmov s22, r7 1524; CHECK-NEON-NEXT: vcvt.s32.f32 s0, s0 1525; CHECK-NEON-NEXT: vmov s30, r6 1526; CHECK-NEON-NEXT: vmov r0, s0 1527; CHECK-NEON-NEXT: vmov.32 d13[1], r0 1528; CHECK-NEON-NEXT: vmov r0, s28 1529; CHECK-NEON-NEXT: bl __aeabi_h2f 1530; CHECK-NEON-NEXT: vmov s0, r0 1531; CHECK-NEON-NEXT: vmov r1, s20 1532; CHECK-NEON-NEXT: vcvt.s32.f32 s0, s0 1533; CHECK-NEON-NEXT: vmov s2, r5 1534; CHECK-NEON-NEXT: vcvt.s32.f32 s20, s2 1535; CHECK-NEON-NEXT: vmov r0, s0 1536; CHECK-NEON-NEXT: vcvt.s32.f32 s0, s30 1537; CHECK-NEON-NEXT: vmov.32 d8[0], r0 1538; CHECK-NEON-NEXT: vmov r0, s0 1539; CHECK-NEON-NEXT: vmov.32 d12[0], r0 1540; CHECK-NEON-NEXT: mov r0, r1 1541; CHECK-NEON-NEXT: bl __aeabi_h2f 1542; CHECK-NEON-NEXT: vmov s0, r0 1543; CHECK-NEON-NEXT: vmov r0, s20 1544; CHECK-NEON-NEXT: vcvt.s32.f32 s0, s0 1545; CHECK-NEON-NEXT: vmov s2, r4 1546; CHECK-NEON-NEXT: vmov.i32 q8, #0xffff 1547; CHECK-NEON-NEXT: vcvt.s32.f32 s2, s2 1548; CHECK-NEON-NEXT: vmov.i32 q9, #0x0 1549; CHECK-NEON-NEXT: vmov.32 d9[0], r0 1550; CHECK-NEON-NEXT: vmov r0, s0 1551; CHECK-NEON-NEXT: vcvt.s32.f32 s0, s22 1552; CHECK-NEON-NEXT: vmov.32 d12[1], r0 1553; CHECK-NEON-NEXT: vmov r0, s0 1554; CHECK-NEON-NEXT: vmin.s32 q10, q6, q8 1555; CHECK-NEON-NEXT: vmax.s32 q10, q10, q9 1556; CHECK-NEON-NEXT: vmov.32 d9[1], r0 1557; CHECK-NEON-NEXT: vmov r0, s2 1558; CHECK-NEON-NEXT: vmovn.i32 d1, q10 1559; CHECK-NEON-NEXT: vmov.32 d8[1], r0 1560; CHECK-NEON-NEXT: vmin.s32 q8, q4, q8 1561; CHECK-NEON-NEXT: vmax.s32 q8, q8, q9 1562; CHECK-NEON-NEXT: vmovn.i32 d0, q8 1563; CHECK-NEON-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15} 1564; CHECK-NEON-NEXT: pop {r4, r5, r6, r7, r11, pc} 1565; 1566; CHECK-FP16-LABEL: ustest_f16i16: 1567; CHECK-FP16: @ %bb.0: @ %entry 1568; CHECK-FP16-NEXT: vmovx.f16 s4, s0 1569; CHECK-FP16-NEXT: vcvt.s32.f16 s12, s0 1570; CHECK-FP16-NEXT: vcvt.s32.f16 s0, s3 1571; CHECK-FP16-NEXT: vcvt.s32.f16 s5, s2 1572; CHECK-FP16-NEXT: vmov r0, s0 1573; CHECK-FP16-NEXT: vcvt.s32.f16 s14, s1 1574; CHECK-FP16-NEXT: vmovx.f16 s10, s3 1575; CHECK-FP16-NEXT: vmovx.f16 s8, s2 1576; CHECK-FP16-NEXT: vcvt.s32.f16 s10, s10 1577; CHECK-FP16-NEXT: vcvt.s32.f16 s8, s8 1578; CHECK-FP16-NEXT: vmovx.f16 s6, s1 1579; CHECK-FP16-NEXT: vcvt.s32.f16 s4, s4 1580; CHECK-FP16-NEXT: vcvt.s32.f16 s6, s6 1581; CHECK-FP16-NEXT: vmov.i32 q10, #0xffff 1582; CHECK-FP16-NEXT: vmov.i32 q11, #0x0 1583; CHECK-FP16-NEXT: vmov.32 d17[0], r0 1584; CHECK-FP16-NEXT: vmov r0, s5 1585; CHECK-FP16-NEXT: vmov.32 d16[0], r0 1586; CHECK-FP16-NEXT: vmov r0, s14 1587; CHECK-FP16-NEXT: vmov.32 d19[0], r0 1588; CHECK-FP16-NEXT: vmov r0, s12 1589; CHECK-FP16-NEXT: vmov.32 d18[0], r0 1590; CHECK-FP16-NEXT: vmov r0, s10 1591; CHECK-FP16-NEXT: vmov.32 d17[1], r0 1592; CHECK-FP16-NEXT: vmov r0, s8 1593; CHECK-FP16-NEXT: vmov.32 d16[1], r0 1594; CHECK-FP16-NEXT: vmov r0, s6 1595; CHECK-FP16-NEXT: vmin.s32 q8, q8, q10 1596; CHECK-FP16-NEXT: vmax.s32 q8, q8, q11 1597; CHECK-FP16-NEXT: vmovn.i32 d1, q8 1598; CHECK-FP16-NEXT: vmov.32 d19[1], r0 1599; CHECK-FP16-NEXT: vmov r0, s4 1600; CHECK-FP16-NEXT: vmov.32 d18[1], r0 1601; CHECK-FP16-NEXT: vmin.s32 q9, q9, q10 1602; CHECK-FP16-NEXT: vmax.s32 q9, q9, q11 1603; CHECK-FP16-NEXT: vmovn.i32 d0, q9 1604; CHECK-FP16-NEXT: bx lr 1605entry: 1606 %conv = fptosi <8 x half> %x to <8 x i32> 1607 %0 = icmp slt <8 x i32> %conv, <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535> 1608 %spec.store.select = select <8 x i1> %0, <8 x i32> %conv, <8 x i32> <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535> 1609 %1 = icmp sgt <8 x i32> %spec.store.select, zeroinitializer 1610 %spec.store.select7 = select <8 x i1> %1, <8 x i32> %spec.store.select, <8 x i32> zeroinitializer 1611 %conv6 = trunc <8 x i32> %spec.store.select7 to <8 x i16> 1612 ret <8 x i16> %conv6 1613} 1614 1615; i64 saturate 1616 1617define <2 x i64> @stest_f64i64(<2 x double> %x) { 1618; CHECK-LABEL: stest_f64i64: 1619; CHECK: @ %bb.0: @ %entry 1620; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, lr} 1621; CHECK-NEXT: push {r4, r5, r6, r7, r8, r9, r10, lr} 1622; CHECK-NEXT: .vsave {d8, d9} 1623; CHECK-NEXT: vpush {d8, d9} 1624; CHECK-NEXT: vorr q4, q0, q0 1625; CHECK-NEXT: vorr d0, d9, d9 1626; CHECK-NEXT: bl __fixdfti 1627; CHECK-NEXT: mov r4, r1 1628; CHECK-NEXT: mvn r9, #0 1629; CHECK-NEXT: subs r1, r0, r9 1630; CHECK-NEXT: mvn r5, #-2147483648 1631; CHECK-NEXT: sbcs r1, r4, r5 1632; CHECK-NEXT: vorr d0, d8, d8 1633; CHECK-NEXT: sbcs r1, r2, #0 1634; CHECK-NEXT: mov r7, #0 1635; CHECK-NEXT: sbcs r1, r3, #0 1636; CHECK-NEXT: mov r8, #-2147483648 1637; CHECK-NEXT: mov r1, #0 1638; CHECK-NEXT: mov r10, #0 1639; CHECK-NEXT: movwlt r1, #1 1640; CHECK-NEXT: cmp r1, #0 1641; CHECK-NEXT: moveq r3, r1 1642; CHECK-NEXT: movne r1, r2 1643; CHECK-NEXT: moveq r4, r5 1644; CHECK-NEXT: moveq r0, r9 1645; CHECK-NEXT: rsbs r2, r0, #0 1646; CHECK-NEXT: rscs r2, r4, #-2147483648 1647; CHECK-NEXT: sbcs r1, r9, r1 1648; CHECK-NEXT: sbcs r1, r9, r3 1649; CHECK-NEXT: movwlt r7, #1 1650; CHECK-NEXT: cmp r7, #0 1651; CHECK-NEXT: movne r7, r0 1652; CHECK-NEXT: moveq r4, r8 1653; CHECK-NEXT: bl __fixdfti 1654; CHECK-NEXT: subs r6, r0, r9 1655; CHECK-NEXT: vmov.32 d1[0], r7 1656; CHECK-NEXT: sbcs r6, r1, r5 1657; CHECK-NEXT: sbcs r6, r2, #0 1658; CHECK-NEXT: sbcs r6, r3, #0 1659; CHECK-NEXT: mov r6, #0 1660; CHECK-NEXT: movwlt r6, #1 1661; CHECK-NEXT: cmp r6, #0 1662; CHECK-NEXT: moveq r3, r6 1663; CHECK-NEXT: movne r6, r2 1664; CHECK-NEXT: movne r5, r1 1665; CHECK-NEXT: moveq r0, r9 1666; CHECK-NEXT: rsbs r1, r0, #0 1667; CHECK-NEXT: rscs r1, r5, #-2147483648 1668; CHECK-NEXT: sbcs r1, r9, r6 1669; CHECK-NEXT: sbcs r1, r9, r3 1670; CHECK-NEXT: movwlt r10, #1 1671; CHECK-NEXT: cmp r10, #0 1672; CHECK-NEXT: movne r10, r0 1673; CHECK-NEXT: moveq r5, r8 1674; CHECK-NEXT: vmov.32 d0[0], r10 1675; CHECK-NEXT: vmov.32 d1[1], r4 1676; CHECK-NEXT: vmov.32 d0[1], r5 1677; CHECK-NEXT: vpop {d8, d9} 1678; CHECK-NEXT: pop {r4, r5, r6, r7, r8, r9, r10, pc} 1679entry: 1680 %conv = fptosi <2 x double> %x to <2 x i128> 1681 %0 = icmp slt <2 x i128> %conv, <i128 9223372036854775807, i128 9223372036854775807> 1682 %spec.store.select = select <2 x i1> %0, <2 x i128> %conv, <2 x i128> <i128 9223372036854775807, i128 9223372036854775807> 1683 %1 = icmp sgt <2 x i128> %spec.store.select, <i128 -9223372036854775808, i128 -9223372036854775808> 1684 %spec.store.select7 = select <2 x i1> %1, <2 x i128> %spec.store.select, <2 x i128> <i128 -9223372036854775808, i128 -9223372036854775808> 1685 %conv6 = trunc <2 x i128> %spec.store.select7 to <2 x i64> 1686 ret <2 x i64> %conv6 1687} 1688 1689define <2 x i64> @utest_f64i64(<2 x double> %x) { 1690; CHECK-LABEL: utest_f64i64: 1691; CHECK: @ %bb.0: @ %entry 1692; CHECK-NEXT: .save {r4, r5, r6, lr} 1693; CHECK-NEXT: push {r4, r5, r6, lr} 1694; CHECK-NEXT: .vsave {d8, d9} 1695; CHECK-NEXT: vpush {d8, d9} 1696; CHECK-NEXT: vorr q4, q0, q0 1697; CHECK-NEXT: vorr d0, d9, d9 1698; CHECK-NEXT: bl __fixunsdfti 1699; CHECK-NEXT: mov r4, r1 1700; CHECK-NEXT: subs r1, r2, #1 1701; CHECK-NEXT: vorr d0, d8, d8 1702; CHECK-NEXT: sbcs r1, r3, #0 1703; CHECK-NEXT: mov r6, #0 1704; CHECK-NEXT: mov r5, #0 1705; CHECK-NEXT: movwlo r6, #1 1706; CHECK-NEXT: cmp r6, #0 1707; CHECK-NEXT: moveq r4, r6 1708; CHECK-NEXT: movne r6, r0 1709; CHECK-NEXT: bl __fixunsdfti 1710; CHECK-NEXT: subs r2, r2, #1 1711; CHECK-NEXT: vmov.32 d1[0], r6 1712; CHECK-NEXT: sbcs r2, r3, #0 1713; CHECK-NEXT: movwlo r5, #1 1714; CHECK-NEXT: cmp r5, #0 1715; CHECK-NEXT: moveq r0, r5 1716; CHECK-NEXT: movne r5, r1 1717; CHECK-NEXT: vmov.32 d0[0], r0 1718; CHECK-NEXT: vmov.32 d1[1], r4 1719; CHECK-NEXT: vmov.32 d0[1], r5 1720; CHECK-NEXT: vpop {d8, d9} 1721; CHECK-NEXT: pop {r4, r5, r6, pc} 1722entry: 1723 %conv = fptoui <2 x double> %x to <2 x i128> 1724 %0 = icmp ult <2 x i128> %conv, <i128 18446744073709551616, i128 18446744073709551616> 1725 %spec.store.select = select <2 x i1> %0, <2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616> 1726 %conv6 = trunc <2 x i128> %spec.store.select to <2 x i64> 1727 ret <2 x i64> %conv6 1728} 1729 1730define <2 x i64> @ustest_f64i64(<2 x double> %x) { 1731; CHECK-LABEL: ustest_f64i64: 1732; CHECK: @ %bb.0: @ %entry 1733; CHECK-NEXT: .save {r4, r5, r6, r7, r8, lr} 1734; CHECK-NEXT: push {r4, r5, r6, r7, r8, lr} 1735; CHECK-NEXT: .vsave {d8, d9} 1736; CHECK-NEXT: vpush {d8, d9} 1737; CHECK-NEXT: vorr q4, q0, q0 1738; CHECK-NEXT: vorr d0, d9, d9 1739; CHECK-NEXT: bl __fixdfti 1740; CHECK-NEXT: mov r4, r1 1741; CHECK-NEXT: subs r1, r2, #1 1742; CHECK-NEXT: sbcs r1, r3, #0 1743; CHECK-NEXT: mov r8, #1 1744; CHECK-NEXT: mov r1, #0 1745; CHECK-NEXT: movge r2, r8 1746; CHECK-NEXT: movwlt r1, #1 1747; CHECK-NEXT: cmp r1, #0 1748; CHECK-NEXT: moveq r3, r1 1749; CHECK-NEXT: moveq r4, r1 1750; CHECK-NEXT: movne r1, r0 1751; CHECK-NEXT: rsbs r0, r1, #0 1752; CHECK-NEXT: rscs r0, r4, #0 1753; CHECK-NEXT: vorr d0, d8, d8 1754; CHECK-NEXT: rscs r0, r2, #0 1755; CHECK-NEXT: mov r7, #0 1756; CHECK-NEXT: rscs r0, r3, #0 1757; CHECK-NEXT: mov r5, #0 1758; CHECK-NEXT: movwlt r7, #1 1759; CHECK-NEXT: cmp r7, #0 1760; CHECK-NEXT: moveq r4, r7 1761; CHECK-NEXT: movne r7, r1 1762; CHECK-NEXT: bl __fixdfti 1763; CHECK-NEXT: subs r6, r2, #1 1764; CHECK-NEXT: vmov.32 d1[0], r7 1765; CHECK-NEXT: sbcs r6, r3, #0 1766; CHECK-NEXT: movlt r8, r2 1767; CHECK-NEXT: mov r2, #0 1768; CHECK-NEXT: movwlt r2, #1 1769; CHECK-NEXT: cmp r2, #0 1770; CHECK-NEXT: moveq r3, r2 1771; CHECK-NEXT: moveq r1, r2 1772; CHECK-NEXT: movne r2, r0 1773; CHECK-NEXT: rsbs r0, r2, #0 1774; CHECK-NEXT: rscs r0, r1, #0 1775; CHECK-NEXT: rscs r0, r8, #0 1776; CHECK-NEXT: rscs r0, r3, #0 1777; CHECK-NEXT: movwlt r5, #1 1778; CHECK-NEXT: cmp r5, #0 1779; CHECK-NEXT: moveq r2, r5 1780; CHECK-NEXT: movne r5, r1 1781; CHECK-NEXT: vmov.32 d0[0], r2 1782; CHECK-NEXT: vmov.32 d1[1], r4 1783; CHECK-NEXT: vmov.32 d0[1], r5 1784; CHECK-NEXT: vpop {d8, d9} 1785; CHECK-NEXT: pop {r4, r5, r6, r7, r8, pc} 1786entry: 1787 %conv = fptosi <2 x double> %x to <2 x i128> 1788 %0 = icmp slt <2 x i128> %conv, <i128 18446744073709551616, i128 18446744073709551616> 1789 %spec.store.select = select <2 x i1> %0, <2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616> 1790 %1 = icmp sgt <2 x i128> %spec.store.select, zeroinitializer 1791 %spec.store.select7 = select <2 x i1> %1, <2 x i128> %spec.store.select, <2 x i128> zeroinitializer 1792 %conv6 = trunc <2 x i128> %spec.store.select7 to <2 x i64> 1793 ret <2 x i64> %conv6 1794} 1795 1796define <2 x i64> @stest_f32i64(<2 x float> %x) { 1797; CHECK-LABEL: stest_f32i64: 1798; CHECK: @ %bb.0: @ %entry 1799; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, lr} 1800; CHECK-NEXT: push {r4, r5, r6, r7, r8, r9, r10, lr} 1801; CHECK-NEXT: .vsave {d8} 1802; CHECK-NEXT: vpush {d8} 1803; CHECK-NEXT: vmov.f64 d8, d0 1804; CHECK-NEXT: vmov.f32 s0, s17 1805; CHECK-NEXT: bl __fixsfti 1806; CHECK-NEXT: mov r4, r1 1807; CHECK-NEXT: mvn r9, #0 1808; CHECK-NEXT: subs r1, r0, r9 1809; CHECK-NEXT: mvn r5, #-2147483648 1810; CHECK-NEXT: sbcs r1, r4, r5 1811; CHECK-NEXT: vmov.f32 s0, s16 1812; CHECK-NEXT: sbcs r1, r2, #0 1813; CHECK-NEXT: mov r7, #0 1814; CHECK-NEXT: sbcs r1, r3, #0 1815; CHECK-NEXT: mov r8, #-2147483648 1816; CHECK-NEXT: mov r1, #0 1817; CHECK-NEXT: mov r10, #0 1818; CHECK-NEXT: movwlt r1, #1 1819; CHECK-NEXT: cmp r1, #0 1820; CHECK-NEXT: moveq r3, r1 1821; CHECK-NEXT: movne r1, r2 1822; CHECK-NEXT: moveq r4, r5 1823; CHECK-NEXT: moveq r0, r9 1824; CHECK-NEXT: rsbs r2, r0, #0 1825; CHECK-NEXT: rscs r2, r4, #-2147483648 1826; CHECK-NEXT: sbcs r1, r9, r1 1827; CHECK-NEXT: sbcs r1, r9, r3 1828; CHECK-NEXT: movwlt r7, #1 1829; CHECK-NEXT: cmp r7, #0 1830; CHECK-NEXT: movne r7, r0 1831; CHECK-NEXT: moveq r4, r8 1832; CHECK-NEXT: bl __fixsfti 1833; CHECK-NEXT: subs r6, r0, r9 1834; CHECK-NEXT: vmov.32 d1[0], r7 1835; CHECK-NEXT: sbcs r6, r1, r5 1836; CHECK-NEXT: sbcs r6, r2, #0 1837; CHECK-NEXT: sbcs r6, r3, #0 1838; CHECK-NEXT: mov r6, #0 1839; CHECK-NEXT: movwlt r6, #1 1840; CHECK-NEXT: cmp r6, #0 1841; CHECK-NEXT: moveq r3, r6 1842; CHECK-NEXT: movne r6, r2 1843; CHECK-NEXT: movne r5, r1 1844; CHECK-NEXT: moveq r0, r9 1845; CHECK-NEXT: rsbs r1, r0, #0 1846; CHECK-NEXT: rscs r1, r5, #-2147483648 1847; CHECK-NEXT: sbcs r1, r9, r6 1848; CHECK-NEXT: sbcs r1, r9, r3 1849; CHECK-NEXT: movwlt r10, #1 1850; CHECK-NEXT: cmp r10, #0 1851; CHECK-NEXT: movne r10, r0 1852; CHECK-NEXT: moveq r5, r8 1853; CHECK-NEXT: vmov.32 d0[0], r10 1854; CHECK-NEXT: vmov.32 d1[1], r4 1855; CHECK-NEXT: vmov.32 d0[1], r5 1856; CHECK-NEXT: vpop {d8} 1857; CHECK-NEXT: pop {r4, r5, r6, r7, r8, r9, r10, pc} 1858entry: 1859 %conv = fptosi <2 x float> %x to <2 x i128> 1860 %0 = icmp slt <2 x i128> %conv, <i128 9223372036854775807, i128 9223372036854775807> 1861 %spec.store.select = select <2 x i1> %0, <2 x i128> %conv, <2 x i128> <i128 9223372036854775807, i128 9223372036854775807> 1862 %1 = icmp sgt <2 x i128> %spec.store.select, <i128 -9223372036854775808, i128 -9223372036854775808> 1863 %spec.store.select7 = select <2 x i1> %1, <2 x i128> %spec.store.select, <2 x i128> <i128 -9223372036854775808, i128 -9223372036854775808> 1864 %conv6 = trunc <2 x i128> %spec.store.select7 to <2 x i64> 1865 ret <2 x i64> %conv6 1866} 1867 1868define <2 x i64> @utest_f32i64(<2 x float> %x) { 1869; CHECK-LABEL: utest_f32i64: 1870; CHECK: @ %bb.0: @ %entry 1871; CHECK-NEXT: .save {r4, r5, r6, lr} 1872; CHECK-NEXT: push {r4, r5, r6, lr} 1873; CHECK-NEXT: .vsave {d8} 1874; CHECK-NEXT: vpush {d8} 1875; CHECK-NEXT: vmov.f64 d8, d0 1876; CHECK-NEXT: vmov.f32 s0, s17 1877; CHECK-NEXT: bl __fixunssfti 1878; CHECK-NEXT: vmov.f32 s0, s16 1879; CHECK-NEXT: mov r4, r1 1880; CHECK-NEXT: subs r1, r2, #1 1881; CHECK-NEXT: mov r6, #0 1882; CHECK-NEXT: sbcs r1, r3, #0 1883; CHECK-NEXT: mov r5, #0 1884; CHECK-NEXT: movwlo r6, #1 1885; CHECK-NEXT: cmp r6, #0 1886; CHECK-NEXT: moveq r4, r6 1887; CHECK-NEXT: movne r6, r0 1888; CHECK-NEXT: bl __fixunssfti 1889; CHECK-NEXT: subs r2, r2, #1 1890; CHECK-NEXT: vmov.32 d1[0], r6 1891; CHECK-NEXT: sbcs r2, r3, #0 1892; CHECK-NEXT: movwlo r5, #1 1893; CHECK-NEXT: cmp r5, #0 1894; CHECK-NEXT: moveq r0, r5 1895; CHECK-NEXT: movne r5, r1 1896; CHECK-NEXT: vmov.32 d0[0], r0 1897; CHECK-NEXT: vmov.32 d1[1], r4 1898; CHECK-NEXT: vmov.32 d0[1], r5 1899; CHECK-NEXT: vpop {d8} 1900; CHECK-NEXT: pop {r4, r5, r6, pc} 1901entry: 1902 %conv = fptoui <2 x float> %x to <2 x i128> 1903 %0 = icmp ult <2 x i128> %conv, <i128 18446744073709551616, i128 18446744073709551616> 1904 %spec.store.select = select <2 x i1> %0, <2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616> 1905 %conv6 = trunc <2 x i128> %spec.store.select to <2 x i64> 1906 ret <2 x i64> %conv6 1907} 1908 1909define <2 x i64> @ustest_f32i64(<2 x float> %x) { 1910; CHECK-LABEL: ustest_f32i64: 1911; CHECK: @ %bb.0: @ %entry 1912; CHECK-NEXT: .save {r4, r5, r6, r7, r8, lr} 1913; CHECK-NEXT: push {r4, r5, r6, r7, r8, lr} 1914; CHECK-NEXT: .vsave {d8} 1915; CHECK-NEXT: vpush {d8} 1916; CHECK-NEXT: vmov.f64 d8, d0 1917; CHECK-NEXT: vmov.f32 s0, s17 1918; CHECK-NEXT: bl __fixsfti 1919; CHECK-NEXT: mov r4, r1 1920; CHECK-NEXT: subs r1, r2, #1 1921; CHECK-NEXT: sbcs r1, r3, #0 1922; CHECK-NEXT: mov r8, #1 1923; CHECK-NEXT: mov r1, #0 1924; CHECK-NEXT: vmov.f32 s0, s16 1925; CHECK-NEXT: movge r2, r8 1926; CHECK-NEXT: movwlt r1, #1 1927; CHECK-NEXT: cmp r1, #0 1928; CHECK-NEXT: mov r7, #0 1929; CHECK-NEXT: moveq r3, r1 1930; CHECK-NEXT: moveq r4, r1 1931; CHECK-NEXT: movne r1, r0 1932; CHECK-NEXT: rsbs r0, r1, #0 1933; CHECK-NEXT: rscs r0, r4, #0 1934; CHECK-NEXT: mov r5, #0 1935; CHECK-NEXT: rscs r0, r2, #0 1936; CHECK-NEXT: rscs r0, r3, #0 1937; CHECK-NEXT: movwlt r7, #1 1938; CHECK-NEXT: cmp r7, #0 1939; CHECK-NEXT: moveq r4, r7 1940; CHECK-NEXT: movne r7, r1 1941; CHECK-NEXT: bl __fixsfti 1942; CHECK-NEXT: subs r6, r2, #1 1943; CHECK-NEXT: vmov.32 d1[0], r7 1944; CHECK-NEXT: sbcs r6, r3, #0 1945; CHECK-NEXT: movlt r8, r2 1946; CHECK-NEXT: mov r2, #0 1947; CHECK-NEXT: movwlt r2, #1 1948; CHECK-NEXT: cmp r2, #0 1949; CHECK-NEXT: moveq r3, r2 1950; CHECK-NEXT: moveq r1, r2 1951; CHECK-NEXT: movne r2, r0 1952; CHECK-NEXT: rsbs r0, r2, #0 1953; CHECK-NEXT: rscs r0, r1, #0 1954; CHECK-NEXT: rscs r0, r8, #0 1955; CHECK-NEXT: rscs r0, r3, #0 1956; CHECK-NEXT: movwlt r5, #1 1957; CHECK-NEXT: cmp r5, #0 1958; CHECK-NEXT: moveq r2, r5 1959; CHECK-NEXT: movne r5, r1 1960; CHECK-NEXT: vmov.32 d0[0], r2 1961; CHECK-NEXT: vmov.32 d1[1], r4 1962; CHECK-NEXT: vmov.32 d0[1], r5 1963; CHECK-NEXT: vpop {d8} 1964; CHECK-NEXT: pop {r4, r5, r6, r7, r8, pc} 1965entry: 1966 %conv = fptosi <2 x float> %x to <2 x i128> 1967 %0 = icmp slt <2 x i128> %conv, <i128 18446744073709551616, i128 18446744073709551616> 1968 %spec.store.select = select <2 x i1> %0, <2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616> 1969 %1 = icmp sgt <2 x i128> %spec.store.select, zeroinitializer 1970 %spec.store.select7 = select <2 x i1> %1, <2 x i128> %spec.store.select, <2 x i128> zeroinitializer 1971 %conv6 = trunc <2 x i128> %spec.store.select7 to <2 x i64> 1972 ret <2 x i64> %conv6 1973} 1974 1975define <2 x i64> @stest_f16i64(<2 x half> %x) { 1976; CHECK-NEON-LABEL: stest_f16i64: 1977; CHECK-NEON: @ %bb.0: @ %entry 1978; CHECK-NEON-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, lr} 1979; CHECK-NEON-NEXT: push {r4, r5, r6, r7, r8, r9, r10, lr} 1980; CHECK-NEON-NEXT: .vsave {d8} 1981; CHECK-NEON-NEXT: vpush {d8} 1982; CHECK-NEON-NEXT: vmov r0, s0 1983; CHECK-NEON-NEXT: vmov.f32 s16, s1 1984; CHECK-NEON-NEXT: bl __aeabi_h2f 1985; CHECK-NEON-NEXT: mov r8, r0 1986; CHECK-NEON-NEXT: vmov r0, s16 1987; CHECK-NEON-NEXT: bl __aeabi_h2f 1988; CHECK-NEON-NEXT: vmov s0, r0 1989; CHECK-NEON-NEXT: bl __fixsfti 1990; CHECK-NEON-NEXT: mov r4, r1 1991; CHECK-NEON-NEXT: mvn r9, #0 1992; CHECK-NEON-NEXT: subs r1, r0, r9 1993; CHECK-NEON-NEXT: mvn r6, #-2147483648 1994; CHECK-NEON-NEXT: sbcs r1, r4, r6 1995; CHECK-NEON-NEXT: vmov s0, r8 1996; CHECK-NEON-NEXT: sbcs r1, r2, #0 1997; CHECK-NEON-NEXT: mov r5, #0 1998; CHECK-NEON-NEXT: sbcs r1, r3, #0 1999; CHECK-NEON-NEXT: mov r8, #-2147483648 2000; CHECK-NEON-NEXT: mov r1, #0 2001; CHECK-NEON-NEXT: mov r10, #0 2002; CHECK-NEON-NEXT: movwlt r1, #1 2003; CHECK-NEON-NEXT: cmp r1, #0 2004; CHECK-NEON-NEXT: moveq r3, r1 2005; CHECK-NEON-NEXT: movne r1, r2 2006; CHECK-NEON-NEXT: moveq r4, r6 2007; CHECK-NEON-NEXT: moveq r0, r9 2008; CHECK-NEON-NEXT: rsbs r2, r0, #0 2009; CHECK-NEON-NEXT: rscs r2, r4, #-2147483648 2010; CHECK-NEON-NEXT: sbcs r1, r9, r1 2011; CHECK-NEON-NEXT: sbcs r1, r9, r3 2012; CHECK-NEON-NEXT: movwlt r5, #1 2013; CHECK-NEON-NEXT: cmp r5, #0 2014; CHECK-NEON-NEXT: movne r5, r0 2015; CHECK-NEON-NEXT: moveq r4, r8 2016; CHECK-NEON-NEXT: bl __fixsfti 2017; CHECK-NEON-NEXT: subs r7, r0, r9 2018; CHECK-NEON-NEXT: vmov.32 d1[0], r5 2019; CHECK-NEON-NEXT: sbcs r7, r1, r6 2020; CHECK-NEON-NEXT: sbcs r7, r2, #0 2021; CHECK-NEON-NEXT: sbcs r7, r3, #0 2022; CHECK-NEON-NEXT: mov r7, #0 2023; CHECK-NEON-NEXT: movwlt r7, #1 2024; CHECK-NEON-NEXT: cmp r7, #0 2025; CHECK-NEON-NEXT: moveq r3, r7 2026; CHECK-NEON-NEXT: movne r7, r2 2027; CHECK-NEON-NEXT: movne r6, r1 2028; CHECK-NEON-NEXT: moveq r0, r9 2029; CHECK-NEON-NEXT: rsbs r1, r0, #0 2030; CHECK-NEON-NEXT: rscs r1, r6, #-2147483648 2031; CHECK-NEON-NEXT: sbcs r1, r9, r7 2032; CHECK-NEON-NEXT: sbcs r1, r9, r3 2033; CHECK-NEON-NEXT: movwlt r10, #1 2034; CHECK-NEON-NEXT: cmp r10, #0 2035; CHECK-NEON-NEXT: movne r10, r0 2036; CHECK-NEON-NEXT: moveq r6, r8 2037; CHECK-NEON-NEXT: vmov.32 d0[0], r10 2038; CHECK-NEON-NEXT: vmov.32 d1[1], r4 2039; CHECK-NEON-NEXT: vmov.32 d0[1], r6 2040; CHECK-NEON-NEXT: vpop {d8} 2041; CHECK-NEON-NEXT: pop {r4, r5, r6, r7, r8, r9, r10, pc} 2042; 2043; CHECK-FP16-LABEL: stest_f16i64: 2044; CHECK-FP16: @ %bb.0: @ %entry 2045; CHECK-FP16-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, lr} 2046; CHECK-FP16-NEXT: push {r4, r5, r6, r7, r8, r9, r10, lr} 2047; CHECK-FP16-NEXT: vmov.u16 r0, d0[1] 2048; CHECK-FP16-NEXT: vmov.u16 r7, d0[0] 2049; CHECK-FP16-NEXT: vmov s0, r0 2050; CHECK-FP16-NEXT: bl __fixhfti 2051; CHECK-FP16-NEXT: mov r4, r1 2052; CHECK-FP16-NEXT: mvn r9, #0 2053; CHECK-FP16-NEXT: subs r1, r0, r9 2054; CHECK-FP16-NEXT: mvn r5, #-2147483648 2055; CHECK-FP16-NEXT: sbcs r1, r4, r5 2056; CHECK-FP16-NEXT: vmov s0, r7 2057; CHECK-FP16-NEXT: sbcs r1, r2, #0 2058; CHECK-FP16-NEXT: mov r7, #0 2059; CHECK-FP16-NEXT: sbcs r1, r3, #0 2060; CHECK-FP16-NEXT: mov r8, #-2147483648 2061; CHECK-FP16-NEXT: mov r1, #0 2062; CHECK-FP16-NEXT: mov r10, #0 2063; CHECK-FP16-NEXT: movwlt r1, #1 2064; CHECK-FP16-NEXT: cmp r1, #0 2065; CHECK-FP16-NEXT: moveq r3, r1 2066; CHECK-FP16-NEXT: movne r1, r2 2067; CHECK-FP16-NEXT: moveq r4, r5 2068; CHECK-FP16-NEXT: moveq r0, r9 2069; CHECK-FP16-NEXT: rsbs r2, r0, #0 2070; CHECK-FP16-NEXT: rscs r2, r4, #-2147483648 2071; CHECK-FP16-NEXT: sbcs r1, r9, r1 2072; CHECK-FP16-NEXT: sbcs r1, r9, r3 2073; CHECK-FP16-NEXT: movwlt r7, #1 2074; CHECK-FP16-NEXT: cmp r7, #0 2075; CHECK-FP16-NEXT: movne r7, r0 2076; CHECK-FP16-NEXT: moveq r4, r8 2077; CHECK-FP16-NEXT: bl __fixhfti 2078; CHECK-FP16-NEXT: subs r6, r0, r9 2079; CHECK-FP16-NEXT: vmov.32 d1[0], r7 2080; CHECK-FP16-NEXT: sbcs r6, r1, r5 2081; CHECK-FP16-NEXT: sbcs r6, r2, #0 2082; CHECK-FP16-NEXT: sbcs r6, r3, #0 2083; CHECK-FP16-NEXT: mov r6, #0 2084; CHECK-FP16-NEXT: movwlt r6, #1 2085; CHECK-FP16-NEXT: cmp r6, #0 2086; CHECK-FP16-NEXT: moveq r3, r6 2087; CHECK-FP16-NEXT: movne r6, r2 2088; CHECK-FP16-NEXT: movne r5, r1 2089; CHECK-FP16-NEXT: moveq r0, r9 2090; CHECK-FP16-NEXT: rsbs r1, r0, #0 2091; CHECK-FP16-NEXT: rscs r1, r5, #-2147483648 2092; CHECK-FP16-NEXT: sbcs r1, r9, r6 2093; CHECK-FP16-NEXT: sbcs r1, r9, r3 2094; CHECK-FP16-NEXT: movwlt r10, #1 2095; CHECK-FP16-NEXT: cmp r10, #0 2096; CHECK-FP16-NEXT: movne r10, r0 2097; CHECK-FP16-NEXT: moveq r5, r8 2098; CHECK-FP16-NEXT: vmov.32 d0[0], r10 2099; CHECK-FP16-NEXT: vmov.32 d1[1], r4 2100; CHECK-FP16-NEXT: vmov.32 d0[1], r5 2101; CHECK-FP16-NEXT: pop {r4, r5, r6, r7, r8, r9, r10, pc} 2102entry: 2103 %conv = fptosi <2 x half> %x to <2 x i128> 2104 %0 = icmp slt <2 x i128> %conv, <i128 9223372036854775807, i128 9223372036854775807> 2105 %spec.store.select = select <2 x i1> %0, <2 x i128> %conv, <2 x i128> <i128 9223372036854775807, i128 9223372036854775807> 2106 %1 = icmp sgt <2 x i128> %spec.store.select, <i128 -9223372036854775808, i128 -9223372036854775808> 2107 %spec.store.select7 = select <2 x i1> %1, <2 x i128> %spec.store.select, <2 x i128> <i128 -9223372036854775808, i128 -9223372036854775808> 2108 %conv6 = trunc <2 x i128> %spec.store.select7 to <2 x i64> 2109 ret <2 x i64> %conv6 2110} 2111 2112define <2 x i64> @utesth_f16i64(<2 x half> %x) { 2113; CHECK-NEON-LABEL: utesth_f16i64: 2114; CHECK-NEON: @ %bb.0: @ %entry 2115; CHECK-NEON-NEXT: .save {r4, r5, r6, lr} 2116; CHECK-NEON-NEXT: push {r4, r5, r6, lr} 2117; CHECK-NEON-NEXT: .vsave {d8} 2118; CHECK-NEON-NEXT: vpush {d8} 2119; CHECK-NEON-NEXT: vmov r0, s0 2120; CHECK-NEON-NEXT: vmov.f32 s16, s1 2121; CHECK-NEON-NEXT: bl __aeabi_h2f 2122; CHECK-NEON-NEXT: mov r5, r0 2123; CHECK-NEON-NEXT: vmov r0, s16 2124; CHECK-NEON-NEXT: bl __aeabi_h2f 2125; CHECK-NEON-NEXT: vmov s0, r0 2126; CHECK-NEON-NEXT: bl __fixunssfti 2127; CHECK-NEON-NEXT: mov r4, r1 2128; CHECK-NEON-NEXT: subs r1, r2, #1 2129; CHECK-NEON-NEXT: vmov s0, r5 2130; CHECK-NEON-NEXT: sbcs r1, r3, #0 2131; CHECK-NEON-NEXT: mov r5, #0 2132; CHECK-NEON-NEXT: mov r6, #0 2133; CHECK-NEON-NEXT: movwlo r5, #1 2134; CHECK-NEON-NEXT: cmp r5, #0 2135; CHECK-NEON-NEXT: moveq r4, r5 2136; CHECK-NEON-NEXT: movne r5, r0 2137; CHECK-NEON-NEXT: bl __fixunssfti 2138; CHECK-NEON-NEXT: subs r2, r2, #1 2139; CHECK-NEON-NEXT: vmov.32 d1[0], r5 2140; CHECK-NEON-NEXT: sbcs r2, r3, #0 2141; CHECK-NEON-NEXT: movwlo r6, #1 2142; CHECK-NEON-NEXT: cmp r6, #0 2143; CHECK-NEON-NEXT: moveq r0, r6 2144; CHECK-NEON-NEXT: movne r6, r1 2145; CHECK-NEON-NEXT: vmov.32 d0[0], r0 2146; CHECK-NEON-NEXT: vmov.32 d1[1], r4 2147; CHECK-NEON-NEXT: vmov.32 d0[1], r6 2148; CHECK-NEON-NEXT: vpop {d8} 2149; CHECK-NEON-NEXT: pop {r4, r5, r6, pc} 2150; 2151; CHECK-FP16-LABEL: utesth_f16i64: 2152; CHECK-FP16: @ %bb.0: @ %entry 2153; CHECK-FP16-NEXT: .save {r4, r5, r6, lr} 2154; CHECK-FP16-NEXT: push {r4, r5, r6, lr} 2155; CHECK-FP16-NEXT: vmov.u16 r0, d0[1] 2156; CHECK-FP16-NEXT: vmov.u16 r6, d0[0] 2157; CHECK-FP16-NEXT: vmov s0, r0 2158; CHECK-FP16-NEXT: bl __fixunshfti 2159; CHECK-FP16-NEXT: mov r4, r1 2160; CHECK-FP16-NEXT: subs r1, r2, #1 2161; CHECK-FP16-NEXT: vmov s0, r6 2162; CHECK-FP16-NEXT: sbcs r1, r3, #0 2163; CHECK-FP16-NEXT: mov r6, #0 2164; CHECK-FP16-NEXT: mov r5, #0 2165; CHECK-FP16-NEXT: movwlo r6, #1 2166; CHECK-FP16-NEXT: cmp r6, #0 2167; CHECK-FP16-NEXT: moveq r4, r6 2168; CHECK-FP16-NEXT: movne r6, r0 2169; CHECK-FP16-NEXT: bl __fixunshfti 2170; CHECK-FP16-NEXT: subs r2, r2, #1 2171; CHECK-FP16-NEXT: vmov.32 d1[0], r6 2172; CHECK-FP16-NEXT: sbcs r2, r3, #0 2173; CHECK-FP16-NEXT: movwlo r5, #1 2174; CHECK-FP16-NEXT: cmp r5, #0 2175; CHECK-FP16-NEXT: moveq r0, r5 2176; CHECK-FP16-NEXT: movne r5, r1 2177; CHECK-FP16-NEXT: vmov.32 d0[0], r0 2178; CHECK-FP16-NEXT: vmov.32 d1[1], r4 2179; CHECK-FP16-NEXT: vmov.32 d0[1], r5 2180; CHECK-FP16-NEXT: pop {r4, r5, r6, pc} 2181entry: 2182 %conv = fptoui <2 x half> %x to <2 x i128> 2183 %0 = icmp ult <2 x i128> %conv, <i128 18446744073709551616, i128 18446744073709551616> 2184 %spec.store.select = select <2 x i1> %0, <2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616> 2185 %conv6 = trunc <2 x i128> %spec.store.select to <2 x i64> 2186 ret <2 x i64> %conv6 2187} 2188 2189define <2 x i64> @ustest_f16i64(<2 x half> %x) { 2190; CHECK-NEON-LABEL: ustest_f16i64: 2191; CHECK-NEON: @ %bb.0: @ %entry 2192; CHECK-NEON-NEXT: .save {r4, r5, r6, r7, r8, lr} 2193; CHECK-NEON-NEXT: push {r4, r5, r6, r7, r8, lr} 2194; CHECK-NEON-NEXT: .vsave {d8} 2195; CHECK-NEON-NEXT: vpush {d8} 2196; CHECK-NEON-NEXT: vmov r0, s0 2197; CHECK-NEON-NEXT: vmov.f32 s16, s1 2198; CHECK-NEON-NEXT: bl __aeabi_h2f 2199; CHECK-NEON-NEXT: mov r5, r0 2200; CHECK-NEON-NEXT: vmov r0, s16 2201; CHECK-NEON-NEXT: bl __aeabi_h2f 2202; CHECK-NEON-NEXT: vmov s0, r0 2203; CHECK-NEON-NEXT: bl __fixsfti 2204; CHECK-NEON-NEXT: mov r4, r1 2205; CHECK-NEON-NEXT: subs r1, r2, #1 2206; CHECK-NEON-NEXT: sbcs r1, r3, #0 2207; CHECK-NEON-NEXT: mov r8, #1 2208; CHECK-NEON-NEXT: mov r1, #0 2209; CHECK-NEON-NEXT: movge r2, r8 2210; CHECK-NEON-NEXT: movwlt r1, #1 2211; CHECK-NEON-NEXT: cmp r1, #0 2212; CHECK-NEON-NEXT: moveq r3, r1 2213; CHECK-NEON-NEXT: moveq r4, r1 2214; CHECK-NEON-NEXT: movne r1, r0 2215; CHECK-NEON-NEXT: rsbs r0, r1, #0 2216; CHECK-NEON-NEXT: rscs r0, r4, #0 2217; CHECK-NEON-NEXT: vmov s0, r5 2218; CHECK-NEON-NEXT: rscs r0, r2, #0 2219; CHECK-NEON-NEXT: mov r7, #0 2220; CHECK-NEON-NEXT: rscs r0, r3, #0 2221; CHECK-NEON-NEXT: mov r5, #0 2222; CHECK-NEON-NEXT: movwlt r7, #1 2223; CHECK-NEON-NEXT: cmp r7, #0 2224; CHECK-NEON-NEXT: moveq r4, r7 2225; CHECK-NEON-NEXT: movne r7, r1 2226; CHECK-NEON-NEXT: bl __fixsfti 2227; CHECK-NEON-NEXT: subs r6, r2, #1 2228; CHECK-NEON-NEXT: vmov.32 d1[0], r7 2229; CHECK-NEON-NEXT: sbcs r6, r3, #0 2230; CHECK-NEON-NEXT: movlt r8, r2 2231; CHECK-NEON-NEXT: mov r2, #0 2232; CHECK-NEON-NEXT: movwlt r2, #1 2233; CHECK-NEON-NEXT: cmp r2, #0 2234; CHECK-NEON-NEXT: moveq r3, r2 2235; CHECK-NEON-NEXT: moveq r1, r2 2236; CHECK-NEON-NEXT: movne r2, r0 2237; CHECK-NEON-NEXT: rsbs r0, r2, #0 2238; CHECK-NEON-NEXT: rscs r0, r1, #0 2239; CHECK-NEON-NEXT: rscs r0, r8, #0 2240; CHECK-NEON-NEXT: rscs r0, r3, #0 2241; CHECK-NEON-NEXT: movwlt r5, #1 2242; CHECK-NEON-NEXT: cmp r5, #0 2243; CHECK-NEON-NEXT: moveq r2, r5 2244; CHECK-NEON-NEXT: movne r5, r1 2245; CHECK-NEON-NEXT: vmov.32 d0[0], r2 2246; CHECK-NEON-NEXT: vmov.32 d1[1], r4 2247; CHECK-NEON-NEXT: vmov.32 d0[1], r5 2248; CHECK-NEON-NEXT: vpop {d8} 2249; CHECK-NEON-NEXT: pop {r4, r5, r6, r7, r8, pc} 2250; 2251; CHECK-FP16-LABEL: ustest_f16i64: 2252; CHECK-FP16: @ %bb.0: @ %entry 2253; CHECK-FP16-NEXT: .save {r4, r5, r6, r7, r8, lr} 2254; CHECK-FP16-NEXT: push {r4, r5, r6, r7, r8, lr} 2255; CHECK-FP16-NEXT: vmov.u16 r0, d0[1] 2256; CHECK-FP16-NEXT: vmov.u16 r5, d0[0] 2257; CHECK-FP16-NEXT: vmov s0, r0 2258; CHECK-FP16-NEXT: bl __fixhfti 2259; CHECK-FP16-NEXT: mov r4, r1 2260; CHECK-FP16-NEXT: subs r1, r2, #1 2261; CHECK-FP16-NEXT: sbcs r1, r3, #0 2262; CHECK-FP16-NEXT: mov r8, #1 2263; CHECK-FP16-NEXT: mov r1, #0 2264; CHECK-FP16-NEXT: movge r2, r8 2265; CHECK-FP16-NEXT: movwlt r1, #1 2266; CHECK-FP16-NEXT: cmp r1, #0 2267; CHECK-FP16-NEXT: moveq r3, r1 2268; CHECK-FP16-NEXT: moveq r4, r1 2269; CHECK-FP16-NEXT: movne r1, r0 2270; CHECK-FP16-NEXT: rsbs r0, r1, #0 2271; CHECK-FP16-NEXT: rscs r0, r4, #0 2272; CHECK-FP16-NEXT: vmov s0, r5 2273; CHECK-FP16-NEXT: rscs r0, r2, #0 2274; CHECK-FP16-NEXT: mov r7, #0 2275; CHECK-FP16-NEXT: rscs r0, r3, #0 2276; CHECK-FP16-NEXT: mov r5, #0 2277; CHECK-FP16-NEXT: movwlt r7, #1 2278; CHECK-FP16-NEXT: cmp r7, #0 2279; CHECK-FP16-NEXT: moveq r4, r7 2280; CHECK-FP16-NEXT: movne r7, r1 2281; CHECK-FP16-NEXT: bl __fixhfti 2282; CHECK-FP16-NEXT: subs r6, r2, #1 2283; CHECK-FP16-NEXT: vmov.32 d1[0], r7 2284; CHECK-FP16-NEXT: sbcs r6, r3, #0 2285; CHECK-FP16-NEXT: movlt r8, r2 2286; CHECK-FP16-NEXT: mov r2, #0 2287; CHECK-FP16-NEXT: movwlt r2, #1 2288; CHECK-FP16-NEXT: cmp r2, #0 2289; CHECK-FP16-NEXT: moveq r3, r2 2290; CHECK-FP16-NEXT: moveq r1, r2 2291; CHECK-FP16-NEXT: movne r2, r0 2292; CHECK-FP16-NEXT: rsbs r0, r2, #0 2293; CHECK-FP16-NEXT: rscs r0, r1, #0 2294; CHECK-FP16-NEXT: rscs r0, r8, #0 2295; CHECK-FP16-NEXT: rscs r0, r3, #0 2296; CHECK-FP16-NEXT: movwlt r5, #1 2297; CHECK-FP16-NEXT: cmp r5, #0 2298; CHECK-FP16-NEXT: moveq r2, r5 2299; CHECK-FP16-NEXT: movne r5, r1 2300; CHECK-FP16-NEXT: vmov.32 d0[0], r2 2301; CHECK-FP16-NEXT: vmov.32 d1[1], r4 2302; CHECK-FP16-NEXT: vmov.32 d0[1], r5 2303; CHECK-FP16-NEXT: pop {r4, r5, r6, r7, r8, pc} 2304entry: 2305 %conv = fptosi <2 x half> %x to <2 x i128> 2306 %0 = icmp slt <2 x i128> %conv, <i128 18446744073709551616, i128 18446744073709551616> 2307 %spec.store.select = select <2 x i1> %0, <2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616> 2308 %1 = icmp sgt <2 x i128> %spec.store.select, zeroinitializer 2309 %spec.store.select7 = select <2 x i1> %1, <2 x i128> %spec.store.select, <2 x i128> zeroinitializer 2310 %conv6 = trunc <2 x i128> %spec.store.select7 to <2 x i64> 2311 ret <2 x i64> %conv6 2312} 2313 2314 2315 2316; i32 saturate 2317 2318define <2 x i32> @stest_f64i32_mm(<2 x double> %x) { 2319; CHECK-LABEL: stest_f64i32_mm: 2320; CHECK: @ %bb.0: @ %entry 2321; CHECK-NEXT: .save {r4, r5, r6, r7, r8, lr} 2322; CHECK-NEXT: push {r4, r5, r6, r7, r8, lr} 2323; CHECK-NEXT: .vsave {d8, d9} 2324; CHECK-NEXT: vpush {d8, d9} 2325; CHECK-NEXT: vorr q4, q0, q0 2326; CHECK-NEXT: vmov r0, r1, d8 2327; CHECK-NEXT: bl __aeabi_d2lz 2328; CHECK-NEXT: mov r4, r0 2329; CHECK-NEXT: mov r8, r1 2330; CHECK-NEXT: vmov r0, r1, d9 2331; CHECK-NEXT: mvn r6, #-2147483648 2332; CHECK-NEXT: subs r2, r4, r6 2333; CHECK-NEXT: mov r5, #0 2334; CHECK-NEXT: sbcs r2, r8, #0 2335; CHECK-NEXT: mov r7, #0 2336; CHECK-NEXT: movge r4, r6 2337; CHECK-NEXT: movwlt r5, #1 2338; CHECK-NEXT: bl __aeabi_d2lz 2339; CHECK-NEXT: subs r2, r0, r6 2340; CHECK-NEXT: sbcs r2, r1, #0 2341; CHECK-NEXT: movlt r6, r0 2342; CHECK-NEXT: movwlt r7, #1 2343; CHECK-NEXT: cmp r7, #0 2344; CHECK-NEXT: mov r0, #-2147483648 2345; CHECK-NEXT: movne r7, r1 2346; CHECK-NEXT: cmp r5, #0 2347; CHECK-NEXT: movne r5, r8 2348; CHECK-NEXT: rsbs r2, r4, #-2147483648 2349; CHECK-NEXT: mvn r1, #0 2350; CHECK-NEXT: sbcs r2, r1, r5 2351; CHECK-NEXT: movge r4, r0 2352; CHECK-NEXT: rsbs r2, r6, #-2147483648 2353; CHECK-NEXT: vmov.32 d0[0], r4 2354; CHECK-NEXT: sbcs r1, r1, r7 2355; CHECK-NEXT: movge r6, r0 2356; CHECK-NEXT: vmov.32 d0[1], r6 2357; CHECK-NEXT: vpop {d8, d9} 2358; CHECK-NEXT: pop {r4, r5, r6, r7, r8, pc} 2359entry: 2360 %conv = fptosi <2 x double> %x to <2 x i64> 2361 %spec.store.select = call <2 x i64> @llvm.smin.v2i64(<2 x i64> %conv, <2 x i64> <i64 2147483647, i64 2147483647>) 2362 %spec.store.select7 = call <2 x i64> @llvm.smax.v2i64(<2 x i64> %spec.store.select, <2 x i64> <i64 -2147483648, i64 -2147483648>) 2363 %conv6 = trunc <2 x i64> %spec.store.select7 to <2 x i32> 2364 ret <2 x i32> %conv6 2365} 2366 2367define <2 x i32> @utest_f64i32_mm(<2 x double> %x) { 2368; CHECK-LABEL: utest_f64i32_mm: 2369; CHECK: @ %bb.0: @ %entry 2370; CHECK-NEXT: .save {r4, lr} 2371; CHECK-NEXT: push {r4, lr} 2372; CHECK-NEXT: .vsave {d8, d9} 2373; CHECK-NEXT: vpush {d8, d9} 2374; CHECK-NEXT: vorr q4, q0, q0 2375; CHECK-NEXT: vmov r0, r1, d9 2376; CHECK-NEXT: bl __aeabi_d2ulz 2377; CHECK-NEXT: mov r4, r1 2378; CHECK-NEXT: vmov r2, r1, d8 2379; CHECK-NEXT: vmov.32 d9[0], r0 2380; CHECK-NEXT: mov r0, r2 2381; CHECK-NEXT: bl __aeabi_d2ulz 2382; CHECK-NEXT: vmov.32 d8[0], r0 2383; CHECK-NEXT: vmov.i64 q8, #0xffffffff 2384; CHECK-NEXT: vmov.32 d9[1], r4 2385; CHECK-NEXT: vmov.32 d8[1], r1 2386; CHECK-NEXT: vqsub.u64 q8, q4, q8 2387; CHECK-NEXT: vsub.i64 q8, q4, q8 2388; CHECK-NEXT: vmovn.i64 d0, q8 2389; CHECK-NEXT: vpop {d8, d9} 2390; CHECK-NEXT: pop {r4, pc} 2391entry: 2392 %conv = fptoui <2 x double> %x to <2 x i64> 2393 %spec.store.select = call <2 x i64> @llvm.umin.v2i64(<2 x i64> %conv, <2 x i64> <i64 4294967295, i64 4294967295>) 2394 %conv6 = trunc <2 x i64> %spec.store.select to <2 x i32> 2395 ret <2 x i32> %conv6 2396} 2397 2398define <2 x i32> @ustest_f64i32_mm(<2 x double> %x) { 2399; CHECK-LABEL: ustest_f64i32_mm: 2400; CHECK: @ %bb.0: @ %entry 2401; CHECK-NEXT: .save {r4, r5, r6, lr} 2402; CHECK-NEXT: push {r4, r5, r6, lr} 2403; CHECK-NEXT: .vsave {d8, d9} 2404; CHECK-NEXT: vpush {d8, d9} 2405; CHECK-NEXT: vorr q4, q0, q0 2406; CHECK-NEXT: vmov r0, r1, d8 2407; CHECK-NEXT: bl __aeabi_d2lz 2408; CHECK-NEXT: vmov r2, r12, d9 2409; CHECK-NEXT: mvn r4, #0 2410; CHECK-NEXT: subs r5, r0, r4 2411; CHECK-NEXT: mov r3, #0 2412; CHECK-NEXT: sbcs r5, r1, #0 2413; CHECK-NEXT: mov r6, #0 2414; CHECK-NEXT: movge r0, r4 2415; CHECK-NEXT: movwlt r3, #1 2416; CHECK-NEXT: cmp r3, #0 2417; CHECK-NEXT: mov r5, #0 2418; CHECK-NEXT: movne r3, r1 2419; CHECK-NEXT: rsbs r1, r0, #0 2420; CHECK-NEXT: rscs r1, r3, #0 2421; CHECK-NEXT: movwlt r6, #1 2422; CHECK-NEXT: cmp r6, #0 2423; CHECK-NEXT: movne r6, r0 2424; CHECK-NEXT: mov r0, r2 2425; CHECK-NEXT: mov r1, r12 2426; CHECK-NEXT: bl __aeabi_d2lz 2427; CHECK-NEXT: subs r2, r0, r4 2428; CHECK-NEXT: vmov.32 d0[0], r6 2429; CHECK-NEXT: sbcs r2, r1, #0 2430; CHECK-NEXT: movlt r4, r0 2431; CHECK-NEXT: mov r0, #0 2432; CHECK-NEXT: movwlt r0, #1 2433; CHECK-NEXT: cmp r0, #0 2434; CHECK-NEXT: movne r0, r1 2435; CHECK-NEXT: rsbs r1, r4, #0 2436; CHECK-NEXT: rscs r0, r0, #0 2437; CHECK-NEXT: movwlt r5, #1 2438; CHECK-NEXT: cmp r5, #0 2439; CHECK-NEXT: movne r5, r4 2440; CHECK-NEXT: vmov.32 d0[1], r5 2441; CHECK-NEXT: vpop {d8, d9} 2442; CHECK-NEXT: pop {r4, r5, r6, pc} 2443entry: 2444 %conv = fptosi <2 x double> %x to <2 x i64> 2445 %spec.store.select = call <2 x i64> @llvm.smin.v2i64(<2 x i64> %conv, <2 x i64> <i64 4294967295, i64 4294967295>) 2446 %spec.store.select7 = call <2 x i64> @llvm.smax.v2i64(<2 x i64> %spec.store.select, <2 x i64> zeroinitializer) 2447 %conv6 = trunc <2 x i64> %spec.store.select7 to <2 x i32> 2448 ret <2 x i32> %conv6 2449} 2450 2451define <4 x i32> @stest_f32i32_mm(<4 x float> %x) { 2452; CHECK-LABEL: stest_f32i32_mm: 2453; CHECK: @ %bb.0: @ %entry 2454; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr} 2455; CHECK-NEXT: push {r4, r5, r6, r7, r8, r9, r10, r11, lr} 2456; CHECK-NEXT: .pad #4 2457; CHECK-NEXT: sub sp, sp, #4 2458; CHECK-NEXT: .vsave {d8, d9} 2459; CHECK-NEXT: vpush {d8, d9} 2460; CHECK-NEXT: .pad #8 2461; CHECK-NEXT: sub sp, sp, #8 2462; CHECK-NEXT: vorr q4, q0, q0 2463; CHECK-NEXT: vmov r0, s19 2464; CHECK-NEXT: bl __aeabi_f2lz 2465; CHECK-NEXT: vmov r2, s18 2466; CHECK-NEXT: mov r11, r0 2467; CHECK-NEXT: vmov r0, s17 2468; CHECK-NEXT: mvn r6, #-2147483648 2469; CHECK-NEXT: mov r3, #-2147483648 2470; CHECK-NEXT: mvn r10, #0 2471; CHECK-NEXT: vmov r7, s16 2472; CHECK-NEXT: mov r4, #0 2473; CHECK-NEXT: str r2, [sp, #4] @ 4-byte Spill 2474; CHECK-NEXT: subs r2, r11, r6 2475; CHECK-NEXT: sbcs r2, r1, #0 2476; CHECK-NEXT: mov r2, #0 2477; CHECK-NEXT: movge r11, r6 2478; CHECK-NEXT: movwlt r2, #1 2479; CHECK-NEXT: cmp r2, #0 2480; CHECK-NEXT: movne r2, r1 2481; CHECK-NEXT: rsbs r1, r11, #-2147483648 2482; CHECK-NEXT: sbcs r1, r10, r2 2483; CHECK-NEXT: movge r11, r3 2484; CHECK-NEXT: bl __aeabi_f2lz 2485; CHECK-NEXT: mov r5, r0 2486; CHECK-NEXT: subs r0, r0, r6 2487; CHECK-NEXT: sbcs r0, r1, #0 2488; CHECK-NEXT: mov r9, #0 2489; CHECK-NEXT: mov r0, r7 2490; CHECK-NEXT: movge r5, r6 2491; CHECK-NEXT: movwlt r9, #1 2492; CHECK-NEXT: cmp r9, #0 2493; CHECK-NEXT: movne r9, r1 2494; CHECK-NEXT: bl __aeabi_f2lz 2495; CHECK-NEXT: mov r7, r0 2496; CHECK-NEXT: subs r0, r0, r6 2497; CHECK-NEXT: sbcs r0, r1, #0 2498; CHECK-NEXT: mov r8, #0 2499; CHECK-NEXT: ldr r0, [sp, #4] @ 4-byte Reload 2500; CHECK-NEXT: movge r7, r6 2501; CHECK-NEXT: movwlt r8, #1 2502; CHECK-NEXT: cmp r8, #0 2503; CHECK-NEXT: movne r8, r1 2504; CHECK-NEXT: bl __aeabi_f2lz 2505; CHECK-NEXT: subs r2, r0, r6 2506; CHECK-NEXT: sbcs r2, r1, #0 2507; CHECK-NEXT: movlt r6, r0 2508; CHECK-NEXT: movwlt r4, #1 2509; CHECK-NEXT: cmp r4, #0 2510; CHECK-NEXT: movne r4, r1 2511; CHECK-NEXT: rsbs r0, r6, #-2147483648 2512; CHECK-NEXT: sbcs r0, r10, r4 2513; CHECK-NEXT: mov r1, #-2147483648 2514; CHECK-NEXT: movge r6, r1 2515; CHECK-NEXT: rsbs r0, r7, #-2147483648 2516; CHECK-NEXT: sbcs r0, r10, r8 2517; CHECK-NEXT: vmov.32 d1[0], r6 2518; CHECK-NEXT: movge r7, r1 2519; CHECK-NEXT: rsbs r0, r5, #-2147483648 2520; CHECK-NEXT: vmov.32 d0[0], r7 2521; CHECK-NEXT: sbcs r0, r10, r9 2522; CHECK-NEXT: movge r5, r1 2523; CHECK-NEXT: vmov.32 d1[1], r11 2524; CHECK-NEXT: vmov.32 d0[1], r5 2525; CHECK-NEXT: add sp, sp, #8 2526; CHECK-NEXT: vpop {d8, d9} 2527; CHECK-NEXT: add sp, sp, #4 2528; CHECK-NEXT: pop {r4, r5, r6, r7, r8, r9, r10, r11, pc} 2529entry: 2530 %conv = fptosi <4 x float> %x to <4 x i64> 2531 %spec.store.select = call <4 x i64> @llvm.smin.v4i64(<4 x i64> %conv, <4 x i64> <i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647>) 2532 %spec.store.select7 = call <4 x i64> @llvm.smax.v4i64(<4 x i64> %spec.store.select, <4 x i64> <i64 -2147483648, i64 -2147483648, i64 -2147483648, i64 -2147483648>) 2533 %conv6 = trunc <4 x i64> %spec.store.select7 to <4 x i32> 2534 ret <4 x i32> %conv6 2535} 2536 2537define <4 x i32> @utest_f32i32_mm(<4 x float> %x) { 2538; CHECK-LABEL: utest_f32i32_mm: 2539; CHECK: @ %bb.0: @ %entry 2540; CHECK-NEXT: .save {r4, r5, r6, r7, r11, lr} 2541; CHECK-NEXT: push {r4, r5, r6, r7, r11, lr} 2542; CHECK-NEXT: .vsave {d8, d9, d10, d11} 2543; CHECK-NEXT: vpush {d8, d9, d10, d11} 2544; CHECK-NEXT: vorr q4, q0, q0 2545; CHECK-NEXT: vmov r0, s17 2546; CHECK-NEXT: bl __aeabi_f2ulz 2547; CHECK-NEXT: mov r4, r1 2548; CHECK-NEXT: vmov r1, s18 2549; CHECK-NEXT: vmov r5, s19 2550; CHECK-NEXT: vmov r6, s16 2551; CHECK-NEXT: vmov.32 d9[0], r0 2552; CHECK-NEXT: mov r0, r1 2553; CHECK-NEXT: bl __aeabi_f2ulz 2554; CHECK-NEXT: vmov.32 d10[0], r0 2555; CHECK-NEXT: mov r0, r5 2556; CHECK-NEXT: mov r7, r1 2557; CHECK-NEXT: bl __aeabi_f2ulz 2558; CHECK-NEXT: vmov.32 d11[0], r0 2559; CHECK-NEXT: mov r0, r6 2560; CHECK-NEXT: mov r5, r1 2561; CHECK-NEXT: bl __aeabi_f2ulz 2562; CHECK-NEXT: vmov.32 d8[0], r0 2563; CHECK-NEXT: vmov.i64 q8, #0xffffffff 2564; CHECK-NEXT: vmov.32 d11[1], r5 2565; CHECK-NEXT: vmov.32 d9[1], r4 2566; CHECK-NEXT: vmov.32 d10[1], r7 2567; CHECK-NEXT: vmov.32 d8[1], r1 2568; CHECK-NEXT: vqsub.u64 q9, q5, q8 2569; CHECK-NEXT: vqsub.u64 q8, q4, q8 2570; CHECK-NEXT: vsub.i64 q9, q5, q9 2571; CHECK-NEXT: vsub.i64 q8, q4, q8 2572; CHECK-NEXT: vmovn.i64 d1, q9 2573; CHECK-NEXT: vmovn.i64 d0, q8 2574; CHECK-NEXT: vpop {d8, d9, d10, d11} 2575; CHECK-NEXT: pop {r4, r5, r6, r7, r11, pc} 2576entry: 2577 %conv = fptoui <4 x float> %x to <4 x i64> 2578 %spec.store.select = call <4 x i64> @llvm.umin.v4i64(<4 x i64> %conv, <4 x i64> <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>) 2579 %conv6 = trunc <4 x i64> %spec.store.select to <4 x i32> 2580 ret <4 x i32> %conv6 2581} 2582 2583define <4 x i32> @ustest_f32i32_mm(<4 x float> %x) { 2584; CHECK-LABEL: ustest_f32i32_mm: 2585; CHECK: @ %bb.0: @ %entry 2586; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, lr} 2587; CHECK-NEXT: push {r4, r5, r6, r7, r8, r9, r10, lr} 2588; CHECK-NEXT: .vsave {d8, d9} 2589; CHECK-NEXT: vpush {d8, d9} 2590; CHECK-NEXT: vorr q4, q0, q0 2591; CHECK-NEXT: vmov r0, s19 2592; CHECK-NEXT: bl __aeabi_f2lz 2593; CHECK-NEXT: vmov r2, s16 2594; CHECK-NEXT: mvn r6, #0 2595; CHECK-NEXT: subs r3, r0, r6 2596; CHECK-NEXT: mov r4, #0 2597; CHECK-NEXT: sbcs r3, r1, #0 2598; CHECK-NEXT: vmov r8, s17 2599; CHECK-NEXT: mov r3, #0 2600; CHECK-NEXT: movge r0, r6 2601; CHECK-NEXT: movwlt r3, #1 2602; CHECK-NEXT: cmp r3, #0 2603; CHECK-NEXT: movne r3, r1 2604; CHECK-NEXT: rsbs r1, r0, #0 2605; CHECK-NEXT: rscs r1, r3, #0 2606; CHECK-NEXT: vmov r9, s18 2607; CHECK-NEXT: movwlt r4, #1 2608; CHECK-NEXT: cmp r4, #0 2609; CHECK-NEXT: movne r4, r0 2610; CHECK-NEXT: mov r10, #0 2611; CHECK-NEXT: mov r0, r2 2612; CHECK-NEXT: bl __aeabi_f2lz 2613; CHECK-NEXT: subs r2, r0, r6 2614; CHECK-NEXT: mov r5, #0 2615; CHECK-NEXT: sbcs r2, r1, #0 2616; CHECK-NEXT: mov r2, #0 2617; CHECK-NEXT: movge r0, r6 2618; CHECK-NEXT: movwlt r2, #1 2619; CHECK-NEXT: cmp r2, #0 2620; CHECK-NEXT: movne r2, r1 2621; CHECK-NEXT: rsbs r1, r0, #0 2622; CHECK-NEXT: rscs r1, r2, #0 2623; CHECK-NEXT: movwlt r5, #1 2624; CHECK-NEXT: cmp r5, #0 2625; CHECK-NEXT: movne r5, r0 2626; CHECK-NEXT: mov r0, r9 2627; CHECK-NEXT: bl __aeabi_f2lz 2628; CHECK-NEXT: subs r2, r0, r6 2629; CHECK-NEXT: mov r7, #0 2630; CHECK-NEXT: sbcs r2, r1, #0 2631; CHECK-NEXT: mov r2, #0 2632; CHECK-NEXT: movge r0, r6 2633; CHECK-NEXT: movwlt r2, #1 2634; CHECK-NEXT: cmp r2, #0 2635; CHECK-NEXT: movne r2, r1 2636; CHECK-NEXT: rsbs r1, r0, #0 2637; CHECK-NEXT: rscs r1, r2, #0 2638; CHECK-NEXT: movwlt r7, #1 2639; CHECK-NEXT: cmp r7, #0 2640; CHECK-NEXT: movne r7, r0 2641; CHECK-NEXT: mov r0, r8 2642; CHECK-NEXT: bl __aeabi_f2lz 2643; CHECK-NEXT: subs r2, r0, r6 2644; CHECK-NEXT: vmov.32 d1[0], r7 2645; CHECK-NEXT: sbcs r2, r1, #0 2646; CHECK-NEXT: movlt r6, r0 2647; CHECK-NEXT: mov r0, #0 2648; CHECK-NEXT: movwlt r0, #1 2649; CHECK-NEXT: cmp r0, #0 2650; CHECK-NEXT: movne r0, r1 2651; CHECK-NEXT: rsbs r1, r6, #0 2652; CHECK-NEXT: rscs r0, r0, #0 2653; CHECK-NEXT: vmov.32 d0[0], r5 2654; CHECK-NEXT: movwlt r10, #1 2655; CHECK-NEXT: cmp r10, #0 2656; CHECK-NEXT: vmov.32 d1[1], r4 2657; CHECK-NEXT: movne r10, r6 2658; CHECK-NEXT: vmov.32 d0[1], r10 2659; CHECK-NEXT: vpop {d8, d9} 2660; CHECK-NEXT: pop {r4, r5, r6, r7, r8, r9, r10, pc} 2661entry: 2662 %conv = fptosi <4 x float> %x to <4 x i64> 2663 %spec.store.select = call <4 x i64> @llvm.smin.v4i64(<4 x i64> %conv, <4 x i64> <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>) 2664 %spec.store.select7 = call <4 x i64> @llvm.smax.v4i64(<4 x i64> %spec.store.select, <4 x i64> zeroinitializer) 2665 %conv6 = trunc <4 x i64> %spec.store.select7 to <4 x i32> 2666 ret <4 x i32> %conv6 2667} 2668 2669define <4 x i32> @stest_f16i32_mm(<4 x half> %x) { 2670; CHECK-NEON-LABEL: stest_f16i32_mm: 2671; CHECK-NEON: @ %bb.0: @ %entry 2672; CHECK-NEON-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr} 2673; CHECK-NEON-NEXT: push {r4, r5, r6, r7, r8, r9, r10, r11, lr} 2674; CHECK-NEON-NEXT: .pad #4 2675; CHECK-NEON-NEXT: sub sp, sp, #4 2676; CHECK-NEON-NEXT: .vsave {d8, d9, d10} 2677; CHECK-NEON-NEXT: vpush {d8, d9, d10} 2678; CHECK-NEON-NEXT: .pad #8 2679; CHECK-NEON-NEXT: sub sp, sp, #8 2680; CHECK-NEON-NEXT: vmov r0, s3 2681; CHECK-NEON-NEXT: vmov.f32 s16, s2 2682; CHECK-NEON-NEXT: vmov.f32 s18, s1 2683; CHECK-NEON-NEXT: vmov.f32 s20, s0 2684; CHECK-NEON-NEXT: bl __aeabi_h2f 2685; CHECK-NEON-NEXT: bl __aeabi_f2lz 2686; CHECK-NEON-NEXT: vmov r2, s16 2687; CHECK-NEON-NEXT: mov r11, r0 2688; CHECK-NEON-NEXT: vmov r0, s18 2689; CHECK-NEON-NEXT: mvn r6, #-2147483648 2690; CHECK-NEON-NEXT: mov r3, #-2147483648 2691; CHECK-NEON-NEXT: mvn r10, #0 2692; CHECK-NEON-NEXT: vmov r7, s20 2693; CHECK-NEON-NEXT: mov r4, #0 2694; CHECK-NEON-NEXT: str r2, [sp, #4] @ 4-byte Spill 2695; CHECK-NEON-NEXT: subs r2, r11, r6 2696; CHECK-NEON-NEXT: sbcs r2, r1, #0 2697; CHECK-NEON-NEXT: mov r2, #0 2698; CHECK-NEON-NEXT: movge r11, r6 2699; CHECK-NEON-NEXT: movwlt r2, #1 2700; CHECK-NEON-NEXT: cmp r2, #0 2701; CHECK-NEON-NEXT: movne r2, r1 2702; CHECK-NEON-NEXT: rsbs r1, r11, #-2147483648 2703; CHECK-NEON-NEXT: sbcs r1, r10, r2 2704; CHECK-NEON-NEXT: movge r11, r3 2705; CHECK-NEON-NEXT: bl __aeabi_h2f 2706; CHECK-NEON-NEXT: bl __aeabi_f2lz 2707; CHECK-NEON-NEXT: mov r5, r0 2708; CHECK-NEON-NEXT: subs r0, r0, r6 2709; CHECK-NEON-NEXT: sbcs r0, r1, #0 2710; CHECK-NEON-NEXT: mov r8, #0 2711; CHECK-NEON-NEXT: mov r0, r7 2712; CHECK-NEON-NEXT: movge r5, r6 2713; CHECK-NEON-NEXT: movwlt r8, #1 2714; CHECK-NEON-NEXT: cmp r8, #0 2715; CHECK-NEON-NEXT: movne r8, r1 2716; CHECK-NEON-NEXT: bl __aeabi_h2f 2717; CHECK-NEON-NEXT: bl __aeabi_f2lz 2718; CHECK-NEON-NEXT: mov r7, r0 2719; CHECK-NEON-NEXT: subs r0, r0, r6 2720; CHECK-NEON-NEXT: sbcs r0, r1, #0 2721; CHECK-NEON-NEXT: mov r9, #0 2722; CHECK-NEON-NEXT: ldr r0, [sp, #4] @ 4-byte Reload 2723; CHECK-NEON-NEXT: movge r7, r6 2724; CHECK-NEON-NEXT: movwlt r9, #1 2725; CHECK-NEON-NEXT: cmp r9, #0 2726; CHECK-NEON-NEXT: movne r9, r1 2727; CHECK-NEON-NEXT: bl __aeabi_h2f 2728; CHECK-NEON-NEXT: bl __aeabi_f2lz 2729; CHECK-NEON-NEXT: subs r2, r0, r6 2730; CHECK-NEON-NEXT: sbcs r2, r1, #0 2731; CHECK-NEON-NEXT: movlt r6, r0 2732; CHECK-NEON-NEXT: movwlt r4, #1 2733; CHECK-NEON-NEXT: cmp r4, #0 2734; CHECK-NEON-NEXT: movne r4, r1 2735; CHECK-NEON-NEXT: rsbs r0, r6, #-2147483648 2736; CHECK-NEON-NEXT: sbcs r0, r10, r4 2737; CHECK-NEON-NEXT: mov r1, #-2147483648 2738; CHECK-NEON-NEXT: movge r6, r1 2739; CHECK-NEON-NEXT: rsbs r0, r7, #-2147483648 2740; CHECK-NEON-NEXT: sbcs r0, r10, r9 2741; CHECK-NEON-NEXT: vmov.32 d1[0], r6 2742; CHECK-NEON-NEXT: movge r7, r1 2743; CHECK-NEON-NEXT: rsbs r0, r5, #-2147483648 2744; CHECK-NEON-NEXT: vmov.32 d0[0], r7 2745; CHECK-NEON-NEXT: sbcs r0, r10, r8 2746; CHECK-NEON-NEXT: movge r5, r1 2747; CHECK-NEON-NEXT: vmov.32 d1[1], r11 2748; CHECK-NEON-NEXT: vmov.32 d0[1], r5 2749; CHECK-NEON-NEXT: add sp, sp, #8 2750; CHECK-NEON-NEXT: vpop {d8, d9, d10} 2751; CHECK-NEON-NEXT: add sp, sp, #4 2752; CHECK-NEON-NEXT: pop {r4, r5, r6, r7, r8, r9, r10, r11, pc} 2753; 2754; CHECK-FP16-LABEL: stest_f16i32_mm: 2755; CHECK-FP16: @ %bb.0: @ %entry 2756; CHECK-FP16-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr} 2757; CHECK-FP16-NEXT: push {r4, r5, r6, r7, r8, r9, r10, r11, lr} 2758; CHECK-FP16-NEXT: .pad #4 2759; CHECK-FP16-NEXT: sub sp, sp, #4 2760; CHECK-FP16-NEXT: .vsave {d8, d9} 2761; CHECK-FP16-NEXT: vpush {d8, d9} 2762; CHECK-FP16-NEXT: vmov.u16 r0, d0[3] 2763; CHECK-FP16-NEXT: vmov.u16 r4, d0[2] 2764; CHECK-FP16-NEXT: vmov.u16 r5, d0[0] 2765; CHECK-FP16-NEXT: vmov.u16 r6, d0[1] 2766; CHECK-FP16-NEXT: vmov s0, r0 2767; CHECK-FP16-NEXT: bl __fixhfdi 2768; CHECK-FP16-NEXT: mov r10, r0 2769; CHECK-FP16-NEXT: mvn r7, #-2147483648 2770; CHECK-FP16-NEXT: subs r0, r0, r7 2771; CHECK-FP16-NEXT: vmov s0, r6 2772; CHECK-FP16-NEXT: sbcs r0, r1, #0 2773; CHECK-FP16-NEXT: mov r2, #-2147483648 2774; CHECK-FP16-NEXT: mov r0, #0 2775; CHECK-FP16-NEXT: movge r10, r7 2776; CHECK-FP16-NEXT: movwlt r0, #1 2777; CHECK-FP16-NEXT: cmp r0, #0 2778; CHECK-FP16-NEXT: movne r0, r1 2779; CHECK-FP16-NEXT: rsbs r1, r10, #-2147483648 2780; CHECK-FP16-NEXT: mvn r9, #0 2781; CHECK-FP16-NEXT: sbcs r0, r9, r0 2782; CHECK-FP16-NEXT: vmov s16, r4 2783; CHECK-FP16-NEXT: mov r11, #0 2784; CHECK-FP16-NEXT: vmov s18, r5 2785; CHECK-FP16-NEXT: movge r10, r2 2786; CHECK-FP16-NEXT: bl __fixhfdi 2787; CHECK-FP16-NEXT: vmov.f32 s0, s18 2788; CHECK-FP16-NEXT: mov r5, r0 2789; CHECK-FP16-NEXT: subs r0, r0, r7 2790; CHECK-FP16-NEXT: mov r4, #0 2791; CHECK-FP16-NEXT: sbcs r0, r1, #0 2792; CHECK-FP16-NEXT: movge r5, r7 2793; CHECK-FP16-NEXT: movwlt r4, #1 2794; CHECK-FP16-NEXT: cmp r4, #0 2795; CHECK-FP16-NEXT: movne r4, r1 2796; CHECK-FP16-NEXT: bl __fixhfdi 2797; CHECK-FP16-NEXT: vmov.f32 s0, s16 2798; CHECK-FP16-NEXT: mov r6, r0 2799; CHECK-FP16-NEXT: subs r0, r0, r7 2800; CHECK-FP16-NEXT: mov r8, #0 2801; CHECK-FP16-NEXT: sbcs r0, r1, #0 2802; CHECK-FP16-NEXT: movge r6, r7 2803; CHECK-FP16-NEXT: movwlt r8, #1 2804; CHECK-FP16-NEXT: cmp r8, #0 2805; CHECK-FP16-NEXT: movne r8, r1 2806; CHECK-FP16-NEXT: bl __fixhfdi 2807; CHECK-FP16-NEXT: subs r2, r0, r7 2808; CHECK-FP16-NEXT: sbcs r2, r1, #0 2809; CHECK-FP16-NEXT: movlt r7, r0 2810; CHECK-FP16-NEXT: movwlt r11, #1 2811; CHECK-FP16-NEXT: cmp r11, #0 2812; CHECK-FP16-NEXT: movne r11, r1 2813; CHECK-FP16-NEXT: rsbs r0, r7, #-2147483648 2814; CHECK-FP16-NEXT: sbcs r0, r9, r11 2815; CHECK-FP16-NEXT: mov r1, #-2147483648 2816; CHECK-FP16-NEXT: movge r7, r1 2817; CHECK-FP16-NEXT: rsbs r0, r6, #-2147483648 2818; CHECK-FP16-NEXT: sbcs r0, r9, r8 2819; CHECK-FP16-NEXT: vmov.32 d1[0], r7 2820; CHECK-FP16-NEXT: movge r6, r1 2821; CHECK-FP16-NEXT: rsbs r0, r5, #-2147483648 2822; CHECK-FP16-NEXT: vmov.32 d0[0], r6 2823; CHECK-FP16-NEXT: sbcs r0, r9, r4 2824; CHECK-FP16-NEXT: movge r5, r1 2825; CHECK-FP16-NEXT: vmov.32 d1[1], r10 2826; CHECK-FP16-NEXT: vmov.32 d0[1], r5 2827; CHECK-FP16-NEXT: vpop {d8, d9} 2828; CHECK-FP16-NEXT: add sp, sp, #4 2829; CHECK-FP16-NEXT: pop {r4, r5, r6, r7, r8, r9, r10, r11, pc} 2830entry: 2831 %conv = fptosi <4 x half> %x to <4 x i64> 2832 %spec.store.select = call <4 x i64> @llvm.smin.v4i64(<4 x i64> %conv, <4 x i64> <i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647>) 2833 %spec.store.select7 = call <4 x i64> @llvm.smax.v4i64(<4 x i64> %spec.store.select, <4 x i64> <i64 -2147483648, i64 -2147483648, i64 -2147483648, i64 -2147483648>) 2834 %conv6 = trunc <4 x i64> %spec.store.select7 to <4 x i32> 2835 ret <4 x i32> %conv6 2836} 2837 2838define <4 x i32> @utesth_f16i32_mm(<4 x half> %x) { 2839; CHECK-NEON-LABEL: utesth_f16i32_mm: 2840; CHECK-NEON: @ %bb.0: @ %entry 2841; CHECK-NEON-NEXT: .save {r4, r5, r6, r7, r11, lr} 2842; CHECK-NEON-NEXT: push {r4, r5, r6, r7, r11, lr} 2843; CHECK-NEON-NEXT: .vsave {d8, d9, d10, d11} 2844; CHECK-NEON-NEXT: vpush {d8, d9, d10, d11} 2845; CHECK-NEON-NEXT: vmov r0, s1 2846; CHECK-NEON-NEXT: vmov.f32 s16, s3 2847; CHECK-NEON-NEXT: vmov.f32 s18, s2 2848; CHECK-NEON-NEXT: vmov.f32 s20, s0 2849; CHECK-NEON-NEXT: bl __aeabi_h2f 2850; CHECK-NEON-NEXT: bl __aeabi_f2ulz 2851; CHECK-NEON-NEXT: mov r4, r1 2852; CHECK-NEON-NEXT: vmov r1, s18 2853; CHECK-NEON-NEXT: vmov r6, s16 2854; CHECK-NEON-NEXT: vmov.32 d9[0], r0 2855; CHECK-NEON-NEXT: vmov r7, s20 2856; CHECK-NEON-NEXT: mov r0, r1 2857; CHECK-NEON-NEXT: bl __aeabi_h2f 2858; CHECK-NEON-NEXT: bl __aeabi_f2ulz 2859; CHECK-NEON-NEXT: vmov.32 d10[0], r0 2860; CHECK-NEON-NEXT: mov r0, r6 2861; CHECK-NEON-NEXT: mov r5, r1 2862; CHECK-NEON-NEXT: bl __aeabi_h2f 2863; CHECK-NEON-NEXT: bl __aeabi_f2ulz 2864; CHECK-NEON-NEXT: vmov.32 d11[0], r0 2865; CHECK-NEON-NEXT: mov r0, r7 2866; CHECK-NEON-NEXT: mov r6, r1 2867; CHECK-NEON-NEXT: bl __aeabi_h2f 2868; CHECK-NEON-NEXT: bl __aeabi_f2ulz 2869; CHECK-NEON-NEXT: vmov.32 d8[0], r0 2870; CHECK-NEON-NEXT: vmov.i64 q8, #0xffffffff 2871; CHECK-NEON-NEXT: vmov.32 d11[1], r6 2872; CHECK-NEON-NEXT: vmov.32 d9[1], r4 2873; CHECK-NEON-NEXT: vmov.32 d10[1], r5 2874; CHECK-NEON-NEXT: vmov.32 d8[1], r1 2875; CHECK-NEON-NEXT: vqsub.u64 q9, q5, q8 2876; CHECK-NEON-NEXT: vqsub.u64 q8, q4, q8 2877; CHECK-NEON-NEXT: vsub.i64 q9, q5, q9 2878; CHECK-NEON-NEXT: vsub.i64 q8, q4, q8 2879; CHECK-NEON-NEXT: vmovn.i64 d1, q9 2880; CHECK-NEON-NEXT: vmovn.i64 d0, q8 2881; CHECK-NEON-NEXT: vpop {d8, d9, d10, d11} 2882; CHECK-NEON-NEXT: pop {r4, r5, r6, r7, r11, pc} 2883; 2884; CHECK-FP16-LABEL: utesth_f16i32_mm: 2885; CHECK-FP16: @ %bb.0: @ %entry 2886; CHECK-FP16-NEXT: .save {r4, r5, r6, lr} 2887; CHECK-FP16-NEXT: push {r4, r5, r6, lr} 2888; CHECK-FP16-NEXT: .vsave {d10, d11, d12, d13} 2889; CHECK-FP16-NEXT: vpush {d10, d11, d12, d13} 2890; CHECK-FP16-NEXT: .vsave {d8} 2891; CHECK-FP16-NEXT: vpush {d8} 2892; CHECK-FP16-NEXT: vmov.u16 r0, d0[1] 2893; CHECK-FP16-NEXT: vorr d8, d0, d0 2894; CHECK-FP16-NEXT: vmov.u16 r6, d0[3] 2895; CHECK-FP16-NEXT: vmov s0, r0 2896; CHECK-FP16-NEXT: bl __fixunshfdi 2897; CHECK-FP16-NEXT: mov r4, r1 2898; CHECK-FP16-NEXT: vmov.u16 r1, d8[2] 2899; CHECK-FP16-NEXT: vmov.32 d11[0], r0 2900; CHECK-FP16-NEXT: vmov s0, r1 2901; CHECK-FP16-NEXT: bl __fixunshfdi 2902; CHECK-FP16-NEXT: vmov s0, r6 2903; CHECK-FP16-NEXT: mov r5, r1 2904; CHECK-FP16-NEXT: vmov.32 d12[0], r0 2905; CHECK-FP16-NEXT: bl __fixunshfdi 2906; CHECK-FP16-NEXT: mov r6, r1 2907; CHECK-FP16-NEXT: vmov.u16 r1, d8[0] 2908; CHECK-FP16-NEXT: vmov.32 d13[0], r0 2909; CHECK-FP16-NEXT: vmov s0, r1 2910; CHECK-FP16-NEXT: bl __fixunshfdi 2911; CHECK-FP16-NEXT: vmov.32 d10[0], r0 2912; CHECK-FP16-NEXT: vmov.i64 q8, #0xffffffff 2913; CHECK-FP16-NEXT: vmov.32 d13[1], r6 2914; CHECK-FP16-NEXT: vmov.32 d11[1], r4 2915; CHECK-FP16-NEXT: vmov.32 d12[1], r5 2916; CHECK-FP16-NEXT: vmov.32 d10[1], r1 2917; CHECK-FP16-NEXT: vqsub.u64 q9, q6, q8 2918; CHECK-FP16-NEXT: vqsub.u64 q8, q5, q8 2919; CHECK-FP16-NEXT: vsub.i64 q9, q6, q9 2920; CHECK-FP16-NEXT: vsub.i64 q8, q5, q8 2921; CHECK-FP16-NEXT: vmovn.i64 d1, q9 2922; CHECK-FP16-NEXT: vmovn.i64 d0, q8 2923; CHECK-FP16-NEXT: vpop {d8} 2924; CHECK-FP16-NEXT: vpop {d10, d11, d12, d13} 2925; CHECK-FP16-NEXT: pop {r4, r5, r6, pc} 2926entry: 2927 %conv = fptoui <4 x half> %x to <4 x i64> 2928 %spec.store.select = call <4 x i64> @llvm.umin.v4i64(<4 x i64> %conv, <4 x i64> <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>) 2929 %conv6 = trunc <4 x i64> %spec.store.select to <4 x i32> 2930 ret <4 x i32> %conv6 2931} 2932 2933define <4 x i32> @ustest_f16i32_mm(<4 x half> %x) { 2934; CHECK-NEON-LABEL: ustest_f16i32_mm: 2935; CHECK-NEON: @ %bb.0: @ %entry 2936; CHECK-NEON-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, lr} 2937; CHECK-NEON-NEXT: push {r4, r5, r6, r7, r8, r9, r10, lr} 2938; CHECK-NEON-NEXT: .vsave {d8, d9, d10} 2939; CHECK-NEON-NEXT: vpush {d8, d9, d10} 2940; CHECK-NEON-NEXT: vmov r0, s3 2941; CHECK-NEON-NEXT: vmov.f32 s16, s2 2942; CHECK-NEON-NEXT: vmov.f32 s18, s1 2943; CHECK-NEON-NEXT: vmov.f32 s20, s0 2944; CHECK-NEON-NEXT: bl __aeabi_h2f 2945; CHECK-NEON-NEXT: bl __aeabi_f2lz 2946; CHECK-NEON-NEXT: vmov r2, s20 2947; CHECK-NEON-NEXT: mvn r6, #0 2948; CHECK-NEON-NEXT: subs r3, r0, r6 2949; CHECK-NEON-NEXT: mov r4, #0 2950; CHECK-NEON-NEXT: sbcs r3, r1, #0 2951; CHECK-NEON-NEXT: vmov r8, s18 2952; CHECK-NEON-NEXT: mov r3, #0 2953; CHECK-NEON-NEXT: movge r0, r6 2954; CHECK-NEON-NEXT: movwlt r3, #1 2955; CHECK-NEON-NEXT: cmp r3, #0 2956; CHECK-NEON-NEXT: movne r3, r1 2957; CHECK-NEON-NEXT: rsbs r1, r0, #0 2958; CHECK-NEON-NEXT: rscs r1, r3, #0 2959; CHECK-NEON-NEXT: vmov r9, s16 2960; CHECK-NEON-NEXT: movwlt r4, #1 2961; CHECK-NEON-NEXT: cmp r4, #0 2962; CHECK-NEON-NEXT: movne r4, r0 2963; CHECK-NEON-NEXT: mov r10, #0 2964; CHECK-NEON-NEXT: mov r0, r2 2965; CHECK-NEON-NEXT: bl __aeabi_h2f 2966; CHECK-NEON-NEXT: bl __aeabi_f2lz 2967; CHECK-NEON-NEXT: subs r2, r0, r6 2968; CHECK-NEON-NEXT: mov r5, #0 2969; CHECK-NEON-NEXT: sbcs r2, r1, #0 2970; CHECK-NEON-NEXT: mov r2, #0 2971; CHECK-NEON-NEXT: movge r0, r6 2972; CHECK-NEON-NEXT: movwlt r2, #1 2973; CHECK-NEON-NEXT: cmp r2, #0 2974; CHECK-NEON-NEXT: movne r2, r1 2975; CHECK-NEON-NEXT: rsbs r1, r0, #0 2976; CHECK-NEON-NEXT: rscs r1, r2, #0 2977; CHECK-NEON-NEXT: movwlt r5, #1 2978; CHECK-NEON-NEXT: cmp r5, #0 2979; CHECK-NEON-NEXT: movne r5, r0 2980; CHECK-NEON-NEXT: mov r0, r9 2981; CHECK-NEON-NEXT: bl __aeabi_h2f 2982; CHECK-NEON-NEXT: bl __aeabi_f2lz 2983; CHECK-NEON-NEXT: subs r2, r0, r6 2984; CHECK-NEON-NEXT: mov r7, #0 2985; CHECK-NEON-NEXT: sbcs r2, r1, #0 2986; CHECK-NEON-NEXT: mov r2, #0 2987; CHECK-NEON-NEXT: movge r0, r6 2988; CHECK-NEON-NEXT: movwlt r2, #1 2989; CHECK-NEON-NEXT: cmp r2, #0 2990; CHECK-NEON-NEXT: movne r2, r1 2991; CHECK-NEON-NEXT: rsbs r1, r0, #0 2992; CHECK-NEON-NEXT: rscs r1, r2, #0 2993; CHECK-NEON-NEXT: movwlt r7, #1 2994; CHECK-NEON-NEXT: cmp r7, #0 2995; CHECK-NEON-NEXT: movne r7, r0 2996; CHECK-NEON-NEXT: mov r0, r8 2997; CHECK-NEON-NEXT: bl __aeabi_h2f 2998; CHECK-NEON-NEXT: bl __aeabi_f2lz 2999; CHECK-NEON-NEXT: subs r2, r0, r6 3000; CHECK-NEON-NEXT: vmov.32 d1[0], r7 3001; CHECK-NEON-NEXT: sbcs r2, r1, #0 3002; CHECK-NEON-NEXT: movlt r6, r0 3003; CHECK-NEON-NEXT: mov r0, #0 3004; CHECK-NEON-NEXT: movwlt r0, #1 3005; CHECK-NEON-NEXT: cmp r0, #0 3006; CHECK-NEON-NEXT: movne r0, r1 3007; CHECK-NEON-NEXT: rsbs r1, r6, #0 3008; CHECK-NEON-NEXT: rscs r0, r0, #0 3009; CHECK-NEON-NEXT: vmov.32 d0[0], r5 3010; CHECK-NEON-NEXT: movwlt r10, #1 3011; CHECK-NEON-NEXT: cmp r10, #0 3012; CHECK-NEON-NEXT: vmov.32 d1[1], r4 3013; CHECK-NEON-NEXT: movne r10, r6 3014; CHECK-NEON-NEXT: vmov.32 d0[1], r10 3015; CHECK-NEON-NEXT: vpop {d8, d9, d10} 3016; CHECK-NEON-NEXT: pop {r4, r5, r6, r7, r8, r9, r10, pc} 3017; 3018; CHECK-FP16-LABEL: ustest_f16i32_mm: 3019; CHECK-FP16: @ %bb.0: @ %entry 3020; CHECK-FP16-NEXT: .save {r4, r5, r6, r7, r8, lr} 3021; CHECK-FP16-NEXT: push {r4, r5, r6, r7, r8, lr} 3022; CHECK-FP16-NEXT: .vsave {d8, d9} 3023; CHECK-FP16-NEXT: vpush {d8, d9} 3024; CHECK-FP16-NEXT: vmov.u16 r0, d0[3] 3025; CHECK-FP16-NEXT: vorr d8, d0, d0 3026; CHECK-FP16-NEXT: vmov.u16 r5, d0[0] 3027; CHECK-FP16-NEXT: vmov s0, r0 3028; CHECK-FP16-NEXT: bl __fixhfdi 3029; CHECK-FP16-NEXT: vmov.u16 r2, d8[1] 3030; CHECK-FP16-NEXT: mvn r4, #0 3031; CHECK-FP16-NEXT: vmov.u16 r3, d8[2] 3032; CHECK-FP16-NEXT: vmov s0, r5 3033; CHECK-FP16-NEXT: mov r6, #0 3034; CHECK-FP16-NEXT: mov r8, #0 3035; CHECK-FP16-NEXT: vmov s16, r2 3036; CHECK-FP16-NEXT: subs r2, r0, r4 3037; CHECK-FP16-NEXT: sbcs r2, r1, #0 3038; CHECK-FP16-NEXT: vmov s18, r3 3039; CHECK-FP16-NEXT: mov r2, #0 3040; CHECK-FP16-NEXT: movge r0, r4 3041; CHECK-FP16-NEXT: movwlt r2, #1 3042; CHECK-FP16-NEXT: cmp r2, #0 3043; CHECK-FP16-NEXT: movne r2, r1 3044; CHECK-FP16-NEXT: rsbs r1, r0, #0 3045; CHECK-FP16-NEXT: rscs r1, r2, #0 3046; CHECK-FP16-NEXT: movwlt r6, #1 3047; CHECK-FP16-NEXT: cmp r6, #0 3048; CHECK-FP16-NEXT: movne r6, r0 3049; CHECK-FP16-NEXT: bl __fixhfdi 3050; CHECK-FP16-NEXT: subs r2, r0, r4 3051; CHECK-FP16-NEXT: vmov.f32 s0, s18 3052; CHECK-FP16-NEXT: sbcs r2, r1, #0 3053; CHECK-FP16-NEXT: mov r7, #0 3054; CHECK-FP16-NEXT: mov r2, #0 3055; CHECK-FP16-NEXT: movge r0, r4 3056; CHECK-FP16-NEXT: movwlt r2, #1 3057; CHECK-FP16-NEXT: cmp r2, #0 3058; CHECK-FP16-NEXT: movne r2, r1 3059; CHECK-FP16-NEXT: rsbs r1, r0, #0 3060; CHECK-FP16-NEXT: rscs r1, r2, #0 3061; CHECK-FP16-NEXT: movwlt r7, #1 3062; CHECK-FP16-NEXT: cmp r7, #0 3063; CHECK-FP16-NEXT: movne r7, r0 3064; CHECK-FP16-NEXT: bl __fixhfdi 3065; CHECK-FP16-NEXT: subs r2, r0, r4 3066; CHECK-FP16-NEXT: vmov.f32 s0, s16 3067; CHECK-FP16-NEXT: sbcs r2, r1, #0 3068; CHECK-FP16-NEXT: mov r5, #0 3069; CHECK-FP16-NEXT: mov r2, #0 3070; CHECK-FP16-NEXT: movge r0, r4 3071; CHECK-FP16-NEXT: movwlt r2, #1 3072; CHECK-FP16-NEXT: cmp r2, #0 3073; CHECK-FP16-NEXT: movne r2, r1 3074; CHECK-FP16-NEXT: rsbs r1, r0, #0 3075; CHECK-FP16-NEXT: rscs r1, r2, #0 3076; CHECK-FP16-NEXT: movwlt r5, #1 3077; CHECK-FP16-NEXT: cmp r5, #0 3078; CHECK-FP16-NEXT: movne r5, r0 3079; CHECK-FP16-NEXT: bl __fixhfdi 3080; CHECK-FP16-NEXT: subs r2, r0, r4 3081; CHECK-FP16-NEXT: vmov.32 d1[0], r5 3082; CHECK-FP16-NEXT: sbcs r2, r1, #0 3083; CHECK-FP16-NEXT: movlt r4, r0 3084; CHECK-FP16-NEXT: mov r0, #0 3085; CHECK-FP16-NEXT: movwlt r0, #1 3086; CHECK-FP16-NEXT: cmp r0, #0 3087; CHECK-FP16-NEXT: movne r0, r1 3088; CHECK-FP16-NEXT: rsbs r1, r4, #0 3089; CHECK-FP16-NEXT: rscs r0, r0, #0 3090; CHECK-FP16-NEXT: vmov.32 d0[0], r7 3091; CHECK-FP16-NEXT: movwlt r8, #1 3092; CHECK-FP16-NEXT: cmp r8, #0 3093; CHECK-FP16-NEXT: vmov.32 d1[1], r6 3094; CHECK-FP16-NEXT: movne r8, r4 3095; CHECK-FP16-NEXT: vmov.32 d0[1], r8 3096; CHECK-FP16-NEXT: vpop {d8, d9} 3097; CHECK-FP16-NEXT: pop {r4, r5, r6, r7, r8, pc} 3098entry: 3099 %conv = fptosi <4 x half> %x to <4 x i64> 3100 %spec.store.select = call <4 x i64> @llvm.smin.v4i64(<4 x i64> %conv, <4 x i64> <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>) 3101 %spec.store.select7 = call <4 x i64> @llvm.smax.v4i64(<4 x i64> %spec.store.select, <4 x i64> zeroinitializer) 3102 %conv6 = trunc <4 x i64> %spec.store.select7 to <4 x i32> 3103 ret <4 x i32> %conv6 3104} 3105 3106; i16 saturate 3107 3108define <2 x i16> @stest_f64i16_mm(<2 x double> %x) { 3109; CHECK-LABEL: stest_f64i16_mm: 3110; CHECK: @ %bb.0: @ %entry 3111; CHECK-NEXT: vcvt.s32.f64 s4, d0 3112; CHECK-NEXT: vmov r0, s4 3113; CHECK-NEXT: vcvt.s32.f64 s0, d1 3114; CHECK-NEXT: vmov.i32 d17, #0x7fff 3115; CHECK-NEXT: vmvn.i32 d18, #0x7fff 3116; CHECK-NEXT: vmov.32 d16[0], r0 3117; CHECK-NEXT: vmov r0, s0 3118; CHECK-NEXT: vmov.32 d16[1], r0 3119; CHECK-NEXT: vmin.s32 d16, d16, d17 3120; CHECK-NEXT: vmax.s32 d0, d16, d18 3121; CHECK-NEXT: bx lr 3122entry: 3123 %conv = fptosi <2 x double> %x to <2 x i32> 3124 %spec.store.select = call <2 x i32> @llvm.smin.v2i32(<2 x i32> %conv, <2 x i32> <i32 32767, i32 32767>) 3125 %spec.store.select7 = call <2 x i32> @llvm.smax.v2i32(<2 x i32> %spec.store.select, <2 x i32> <i32 -32768, i32 -32768>) 3126 %conv6 = trunc <2 x i32> %spec.store.select7 to <2 x i16> 3127 ret <2 x i16> %conv6 3128} 3129 3130define <2 x i16> @utest_f64i16_mm(<2 x double> %x) { 3131; CHECK-LABEL: utest_f64i16_mm: 3132; CHECK: @ %bb.0: @ %entry 3133; CHECK-NEXT: vcvt.u32.f64 s4, d0 3134; CHECK-NEXT: vmov r0, s4 3135; CHECK-NEXT: vcvt.u32.f64 s0, d1 3136; CHECK-NEXT: vmov.i32 d17, #0xffff 3137; CHECK-NEXT: vmov.32 d16[0], r0 3138; CHECK-NEXT: vmov r0, s0 3139; CHECK-NEXT: vmov.32 d16[1], r0 3140; CHECK-NEXT: vmin.u32 d0, d16, d17 3141; CHECK-NEXT: bx lr 3142entry: 3143 %conv = fptoui <2 x double> %x to <2 x i32> 3144 %spec.store.select = call <2 x i32> @llvm.umin.v2i32(<2 x i32> %conv, <2 x i32> <i32 65535, i32 65535>) 3145 %conv6 = trunc <2 x i32> %spec.store.select to <2 x i16> 3146 ret <2 x i16> %conv6 3147} 3148 3149define <2 x i16> @ustest_f64i16_mm(<2 x double> %x) { 3150; CHECK-LABEL: ustest_f64i16_mm: 3151; CHECK: @ %bb.0: @ %entry 3152; CHECK-NEXT: vcvt.s32.f64 s4, d0 3153; CHECK-NEXT: vmov r0, s4 3154; CHECK-NEXT: vcvt.s32.f64 s0, d1 3155; CHECK-NEXT: vmov.i32 d17, #0xffff 3156; CHECK-NEXT: vmov.i32 d18, #0x0 3157; CHECK-NEXT: vmov.32 d16[0], r0 3158; CHECK-NEXT: vmov r0, s0 3159; CHECK-NEXT: vmov.32 d16[1], r0 3160; CHECK-NEXT: vmin.s32 d16, d16, d17 3161; CHECK-NEXT: vmax.s32 d0, d16, d18 3162; CHECK-NEXT: bx lr 3163entry: 3164 %conv = fptosi <2 x double> %x to <2 x i32> 3165 %spec.store.select = call <2 x i32> @llvm.smin.v2i32(<2 x i32> %conv, <2 x i32> <i32 65535, i32 65535>) 3166 %spec.store.select7 = call <2 x i32> @llvm.smax.v2i32(<2 x i32> %spec.store.select, <2 x i32> zeroinitializer) 3167 %conv6 = trunc <2 x i32> %spec.store.select7 to <2 x i16> 3168 ret <2 x i16> %conv6 3169} 3170 3171define <4 x i16> @stest_f32i16_mm(<4 x float> %x) { 3172; CHECK-LABEL: stest_f32i16_mm: 3173; CHECK: @ %bb.0: @ %entry 3174; CHECK-NEXT: vcvt.s32.f32 q8, q0 3175; CHECK-NEXT: vmov.i32 q9, #0x7fff 3176; CHECK-NEXT: vmvn.i32 q10, #0x7fff 3177; CHECK-NEXT: vmin.s32 q8, q8, q9 3178; CHECK-NEXT: vmax.s32 q8, q8, q10 3179; CHECK-NEXT: vmovn.i32 d0, q8 3180; CHECK-NEXT: bx lr 3181entry: 3182 %conv = fptosi <4 x float> %x to <4 x i32> 3183 %spec.store.select = call <4 x i32> @llvm.smin.v4i32(<4 x i32> %conv, <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767>) 3184 %spec.store.select7 = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %spec.store.select, <4 x i32> <i32 -32768, i32 -32768, i32 -32768, i32 -32768>) 3185 %conv6 = trunc <4 x i32> %spec.store.select7 to <4 x i16> 3186 ret <4 x i16> %conv6 3187} 3188 3189define <4 x i16> @utest_f32i16_mm(<4 x float> %x) { 3190; CHECK-LABEL: utest_f32i16_mm: 3191; CHECK: @ %bb.0: @ %entry 3192; CHECK-NEXT: vcvt.u32.f32 q8, q0 3193; CHECK-NEXT: vmov.i32 q9, #0xffff 3194; CHECK-NEXT: vmin.u32 q8, q8, q9 3195; CHECK-NEXT: vmovn.i32 d0, q8 3196; CHECK-NEXT: bx lr 3197entry: 3198 %conv = fptoui <4 x float> %x to <4 x i32> 3199 %spec.store.select = call <4 x i32> @llvm.umin.v4i32(<4 x i32> %conv, <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>) 3200 %conv6 = trunc <4 x i32> %spec.store.select to <4 x i16> 3201 ret <4 x i16> %conv6 3202} 3203 3204define <4 x i16> @ustest_f32i16_mm(<4 x float> %x) { 3205; CHECK-LABEL: ustest_f32i16_mm: 3206; CHECK: @ %bb.0: @ %entry 3207; CHECK-NEXT: vcvt.s32.f32 q8, q0 3208; CHECK-NEXT: vmov.i32 q9, #0xffff 3209; CHECK-NEXT: vmov.i32 q10, #0x0 3210; CHECK-NEXT: vmin.s32 q8, q8, q9 3211; CHECK-NEXT: vmax.s32 q8, q8, q10 3212; CHECK-NEXT: vmovn.i32 d0, q8 3213; CHECK-NEXT: bx lr 3214entry: 3215 %conv = fptosi <4 x float> %x to <4 x i32> 3216 %spec.store.select = call <4 x i32> @llvm.smin.v4i32(<4 x i32> %conv, <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>) 3217 %spec.store.select7 = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %spec.store.select, <4 x i32> zeroinitializer) 3218 %conv6 = trunc <4 x i32> %spec.store.select7 to <4 x i16> 3219 ret <4 x i16> %conv6 3220} 3221 3222define <8 x i16> @stest_f16i16_mm(<8 x half> %x) { 3223; CHECK-NEON-LABEL: stest_f16i16_mm: 3224; CHECK-NEON: @ %bb.0: @ %entry 3225; CHECK-NEON-NEXT: .save {r4, r5, r6, r7, r11, lr} 3226; CHECK-NEON-NEXT: push {r4, r5, r6, r7, r11, lr} 3227; CHECK-NEON-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} 3228; CHECK-NEON-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} 3229; CHECK-NEON-NEXT: vmov r0, s1 3230; CHECK-NEON-NEXT: vmov.f32 s16, s7 3231; CHECK-NEON-NEXT: vmov.f32 s18, s6 3232; CHECK-NEON-NEXT: vmov.f32 s20, s5 3233; CHECK-NEON-NEXT: vmov.f32 s22, s4 3234; CHECK-NEON-NEXT: vmov.f32 s24, s3 3235; CHECK-NEON-NEXT: vmov.f32 s26, s2 3236; CHECK-NEON-NEXT: vmov.f32 s28, s0 3237; CHECK-NEON-NEXT: bl __aeabi_h2f 3238; CHECK-NEON-NEXT: mov r4, r0 3239; CHECK-NEON-NEXT: vmov r0, s26 3240; CHECK-NEON-NEXT: bl __aeabi_h2f 3241; CHECK-NEON-NEXT: mov r5, r0 3242; CHECK-NEON-NEXT: vmov r0, s22 3243; CHECK-NEON-NEXT: bl __aeabi_h2f 3244; CHECK-NEON-NEXT: mov r6, r0 3245; CHECK-NEON-NEXT: vmov r0, s24 3246; CHECK-NEON-NEXT: bl __aeabi_h2f 3247; CHECK-NEON-NEXT: mov r7, r0 3248; CHECK-NEON-NEXT: vmov r0, s18 3249; CHECK-NEON-NEXT: bl __aeabi_h2f 3250; CHECK-NEON-NEXT: vmov s0, r0 3251; CHECK-NEON-NEXT: vcvt.s32.f32 s0, s0 3252; CHECK-NEON-NEXT: vmov r0, s0 3253; CHECK-NEON-NEXT: vmov.32 d13[0], r0 3254; CHECK-NEON-NEXT: vmov r0, s16 3255; CHECK-NEON-NEXT: bl __aeabi_h2f 3256; CHECK-NEON-NEXT: vmov s0, r0 3257; CHECK-NEON-NEXT: vmov s22, r7 3258; CHECK-NEON-NEXT: vcvt.s32.f32 s0, s0 3259; CHECK-NEON-NEXT: vmov s30, r6 3260; CHECK-NEON-NEXT: vmov r0, s0 3261; CHECK-NEON-NEXT: vmov.32 d13[1], r0 3262; CHECK-NEON-NEXT: vmov r0, s28 3263; CHECK-NEON-NEXT: bl __aeabi_h2f 3264; CHECK-NEON-NEXT: vmov s0, r0 3265; CHECK-NEON-NEXT: vmov r1, s20 3266; CHECK-NEON-NEXT: vcvt.s32.f32 s0, s0 3267; CHECK-NEON-NEXT: vmov s2, r5 3268; CHECK-NEON-NEXT: vcvt.s32.f32 s20, s2 3269; CHECK-NEON-NEXT: vmov r0, s0 3270; CHECK-NEON-NEXT: vcvt.s32.f32 s0, s30 3271; CHECK-NEON-NEXT: vmov.32 d8[0], r0 3272; CHECK-NEON-NEXT: vmov r0, s0 3273; CHECK-NEON-NEXT: vmov.32 d12[0], r0 3274; CHECK-NEON-NEXT: mov r0, r1 3275; CHECK-NEON-NEXT: bl __aeabi_h2f 3276; CHECK-NEON-NEXT: vmov s0, r0 3277; CHECK-NEON-NEXT: vmov r0, s20 3278; CHECK-NEON-NEXT: vcvt.s32.f32 s0, s0 3279; CHECK-NEON-NEXT: vmov s2, r4 3280; CHECK-NEON-NEXT: vmov.i32 q8, #0x7fff 3281; CHECK-NEON-NEXT: vcvt.s32.f32 s2, s2 3282; CHECK-NEON-NEXT: vmvn.i32 q9, #0x7fff 3283; CHECK-NEON-NEXT: vmov.32 d9[0], r0 3284; CHECK-NEON-NEXT: vmov r0, s0 3285; CHECK-NEON-NEXT: vcvt.s32.f32 s0, s22 3286; CHECK-NEON-NEXT: vmov.32 d12[1], r0 3287; CHECK-NEON-NEXT: vmov r0, s0 3288; CHECK-NEON-NEXT: vmin.s32 q10, q6, q8 3289; CHECK-NEON-NEXT: vmax.s32 q10, q10, q9 3290; CHECK-NEON-NEXT: vmov.32 d9[1], r0 3291; CHECK-NEON-NEXT: vmov r0, s2 3292; CHECK-NEON-NEXT: vmovn.i32 d1, q10 3293; CHECK-NEON-NEXT: vmov.32 d8[1], r0 3294; CHECK-NEON-NEXT: vmin.s32 q8, q4, q8 3295; CHECK-NEON-NEXT: vmax.s32 q8, q8, q9 3296; CHECK-NEON-NEXT: vmovn.i32 d0, q8 3297; CHECK-NEON-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15} 3298; CHECK-NEON-NEXT: pop {r4, r5, r6, r7, r11, pc} 3299; 3300; CHECK-FP16-LABEL: stest_f16i16_mm: 3301; CHECK-FP16: @ %bb.0: @ %entry 3302; CHECK-FP16-NEXT: vmovx.f16 s4, s0 3303; CHECK-FP16-NEXT: vcvt.s32.f16 s12, s0 3304; CHECK-FP16-NEXT: vcvt.s32.f16 s0, s3 3305; CHECK-FP16-NEXT: vcvt.s32.f16 s5, s2 3306; CHECK-FP16-NEXT: vmov r0, s0 3307; CHECK-FP16-NEXT: vcvt.s32.f16 s14, s1 3308; CHECK-FP16-NEXT: vmovx.f16 s10, s3 3309; CHECK-FP16-NEXT: vmovx.f16 s8, s2 3310; CHECK-FP16-NEXT: vcvt.s32.f16 s10, s10 3311; CHECK-FP16-NEXT: vcvt.s32.f16 s8, s8 3312; CHECK-FP16-NEXT: vmovx.f16 s6, s1 3313; CHECK-FP16-NEXT: vcvt.s32.f16 s4, s4 3314; CHECK-FP16-NEXT: vcvt.s32.f16 s6, s6 3315; CHECK-FP16-NEXT: vmov.i32 q10, #0x7fff 3316; CHECK-FP16-NEXT: vmvn.i32 q11, #0x7fff 3317; CHECK-FP16-NEXT: vmov.32 d17[0], r0 3318; CHECK-FP16-NEXT: vmov r0, s5 3319; CHECK-FP16-NEXT: vmov.32 d16[0], r0 3320; CHECK-FP16-NEXT: vmov r0, s14 3321; CHECK-FP16-NEXT: vmov.32 d19[0], r0 3322; CHECK-FP16-NEXT: vmov r0, s12 3323; CHECK-FP16-NEXT: vmov.32 d18[0], r0 3324; CHECK-FP16-NEXT: vmov r0, s10 3325; CHECK-FP16-NEXT: vmov.32 d17[1], r0 3326; CHECK-FP16-NEXT: vmov r0, s8 3327; CHECK-FP16-NEXT: vmov.32 d16[1], r0 3328; CHECK-FP16-NEXT: vmov r0, s6 3329; CHECK-FP16-NEXT: vmin.s32 q8, q8, q10 3330; CHECK-FP16-NEXT: vmax.s32 q8, q8, q11 3331; CHECK-FP16-NEXT: vmovn.i32 d1, q8 3332; CHECK-FP16-NEXT: vmov.32 d19[1], r0 3333; CHECK-FP16-NEXT: vmov r0, s4 3334; CHECK-FP16-NEXT: vmov.32 d18[1], r0 3335; CHECK-FP16-NEXT: vmin.s32 q9, q9, q10 3336; CHECK-FP16-NEXT: vmax.s32 q9, q9, q11 3337; CHECK-FP16-NEXT: vmovn.i32 d0, q9 3338; CHECK-FP16-NEXT: bx lr 3339entry: 3340 %conv = fptosi <8 x half> %x to <8 x i32> 3341 %spec.store.select = call <8 x i32> @llvm.smin.v8i32(<8 x i32> %conv, <8 x i32> <i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767>) 3342 %spec.store.select7 = call <8 x i32> @llvm.smax.v8i32(<8 x i32> %spec.store.select, <8 x i32> <i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768>) 3343 %conv6 = trunc <8 x i32> %spec.store.select7 to <8 x i16> 3344 ret <8 x i16> %conv6 3345} 3346 3347define <8 x i16> @utesth_f16i16_mm(<8 x half> %x) { 3348; CHECK-NEON-LABEL: utesth_f16i16_mm: 3349; CHECK-NEON: @ %bb.0: @ %entry 3350; CHECK-NEON-NEXT: .save {r4, r5, r6, r7, r11, lr} 3351; CHECK-NEON-NEXT: push {r4, r5, r6, r7, r11, lr} 3352; CHECK-NEON-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14} 3353; CHECK-NEON-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14} 3354; CHECK-NEON-NEXT: vmov r0, s1 3355; CHECK-NEON-NEXT: vmov.f32 s16, s7 3356; CHECK-NEON-NEXT: vmov.f32 s18, s6 3357; CHECK-NEON-NEXT: vmov.f32 s20, s5 3358; CHECK-NEON-NEXT: vmov.f32 s22, s4 3359; CHECK-NEON-NEXT: vmov.f32 s24, s3 3360; CHECK-NEON-NEXT: vmov.f32 s26, s2 3361; CHECK-NEON-NEXT: vmov.f32 s28, s0 3362; CHECK-NEON-NEXT: bl __aeabi_h2f 3363; CHECK-NEON-NEXT: mov r4, r0 3364; CHECK-NEON-NEXT: vmov r0, s26 3365; CHECK-NEON-NEXT: bl __aeabi_h2f 3366; CHECK-NEON-NEXT: mov r5, r0 3367; CHECK-NEON-NEXT: vmov r0, s22 3368; CHECK-NEON-NEXT: bl __aeabi_h2f 3369; CHECK-NEON-NEXT: mov r6, r0 3370; CHECK-NEON-NEXT: vmov r0, s24 3371; CHECK-NEON-NEXT: bl __aeabi_h2f 3372; CHECK-NEON-NEXT: mov r7, r0 3373; CHECK-NEON-NEXT: vmov r0, s18 3374; CHECK-NEON-NEXT: bl __aeabi_h2f 3375; CHECK-NEON-NEXT: vmov s0, r0 3376; CHECK-NEON-NEXT: vcvt.u32.f32 s0, s0 3377; CHECK-NEON-NEXT: vmov r0, s0 3378; CHECK-NEON-NEXT: vmov.32 d13[0], r0 3379; CHECK-NEON-NEXT: vmov r0, s16 3380; CHECK-NEON-NEXT: bl __aeabi_h2f 3381; CHECK-NEON-NEXT: vmov s0, r0 3382; CHECK-NEON-NEXT: vmov s16, r7 3383; CHECK-NEON-NEXT: vcvt.u32.f32 s0, s0 3384; CHECK-NEON-NEXT: vmov s18, r6 3385; CHECK-NEON-NEXT: vmov r0, s0 3386; CHECK-NEON-NEXT: vmov.32 d13[1], r0 3387; CHECK-NEON-NEXT: vmov r0, s28 3388; CHECK-NEON-NEXT: bl __aeabi_h2f 3389; CHECK-NEON-NEXT: vmov s0, r0 3390; CHECK-NEON-NEXT: vmov r1, s20 3391; CHECK-NEON-NEXT: vcvt.u32.f32 s0, s0 3392; CHECK-NEON-NEXT: vmov s2, r5 3393; CHECK-NEON-NEXT: vmov r0, s0 3394; CHECK-NEON-NEXT: vcvt.u32.f32 s0, s18 3395; CHECK-NEON-NEXT: vcvt.u32.f32 s18, s2 3396; CHECK-NEON-NEXT: vmov.32 d10[0], r0 3397; CHECK-NEON-NEXT: vmov r0, s0 3398; CHECK-NEON-NEXT: vmov.32 d12[0], r0 3399; CHECK-NEON-NEXT: mov r0, r1 3400; CHECK-NEON-NEXT: bl __aeabi_h2f 3401; CHECK-NEON-NEXT: vmov s0, r0 3402; CHECK-NEON-NEXT: vmov r0, s18 3403; CHECK-NEON-NEXT: vcvt.u32.f32 s0, s0 3404; CHECK-NEON-NEXT: vmov s2, r4 3405; CHECK-NEON-NEXT: vmov.i32 q8, #0xffff 3406; CHECK-NEON-NEXT: vcvt.u32.f32 s2, s2 3407; CHECK-NEON-NEXT: vmov.32 d11[0], r0 3408; CHECK-NEON-NEXT: vmov r0, s0 3409; CHECK-NEON-NEXT: vcvt.u32.f32 s0, s16 3410; CHECK-NEON-NEXT: vmov.32 d12[1], r0 3411; CHECK-NEON-NEXT: vmov r0, s0 3412; CHECK-NEON-NEXT: vmin.u32 q9, q6, q8 3413; CHECK-NEON-NEXT: vmov.32 d11[1], r0 3414; CHECK-NEON-NEXT: vmov r0, s2 3415; CHECK-NEON-NEXT: vmovn.i32 d1, q9 3416; CHECK-NEON-NEXT: vmov.32 d10[1], r0 3417; CHECK-NEON-NEXT: vmin.u32 q8, q5, q8 3418; CHECK-NEON-NEXT: vmovn.i32 d0, q8 3419; CHECK-NEON-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14} 3420; CHECK-NEON-NEXT: pop {r4, r5, r6, r7, r11, pc} 3421; 3422; CHECK-FP16-LABEL: utesth_f16i16_mm: 3423; CHECK-FP16: @ %bb.0: @ %entry 3424; CHECK-FP16-NEXT: vmovx.f16 s4, s0 3425; CHECK-FP16-NEXT: vcvt.u32.f16 s12, s0 3426; CHECK-FP16-NEXT: vcvt.u32.f16 s0, s3 3427; CHECK-FP16-NEXT: vcvt.u32.f16 s5, s2 3428; CHECK-FP16-NEXT: vmov r0, s0 3429; CHECK-FP16-NEXT: vcvt.u32.f16 s14, s1 3430; CHECK-FP16-NEXT: vmovx.f16 s10, s3 3431; CHECK-FP16-NEXT: vmovx.f16 s8, s2 3432; CHECK-FP16-NEXT: vcvt.u32.f16 s10, s10 3433; CHECK-FP16-NEXT: vcvt.u32.f16 s8, s8 3434; CHECK-FP16-NEXT: vmovx.f16 s6, s1 3435; CHECK-FP16-NEXT: vcvt.u32.f16 s4, s4 3436; CHECK-FP16-NEXT: vcvt.u32.f16 s6, s6 3437; CHECK-FP16-NEXT: vmov.i32 q10, #0xffff 3438; CHECK-FP16-NEXT: vmov.32 d17[0], r0 3439; CHECK-FP16-NEXT: vmov r0, s5 3440; CHECK-FP16-NEXT: vmov.32 d16[0], r0 3441; CHECK-FP16-NEXT: vmov r0, s14 3442; CHECK-FP16-NEXT: vmov.32 d19[0], r0 3443; CHECK-FP16-NEXT: vmov r0, s12 3444; CHECK-FP16-NEXT: vmov.32 d18[0], r0 3445; CHECK-FP16-NEXT: vmov r0, s10 3446; CHECK-FP16-NEXT: vmov.32 d17[1], r0 3447; CHECK-FP16-NEXT: vmov r0, s8 3448; CHECK-FP16-NEXT: vmov.32 d16[1], r0 3449; CHECK-FP16-NEXT: vmov r0, s6 3450; CHECK-FP16-NEXT: vmin.u32 q8, q8, q10 3451; CHECK-FP16-NEXT: vmovn.i32 d1, q8 3452; CHECK-FP16-NEXT: vmov.32 d19[1], r0 3453; CHECK-FP16-NEXT: vmov r0, s4 3454; CHECK-FP16-NEXT: vmov.32 d18[1], r0 3455; CHECK-FP16-NEXT: vmin.u32 q9, q9, q10 3456; CHECK-FP16-NEXT: vmovn.i32 d0, q9 3457; CHECK-FP16-NEXT: bx lr 3458entry: 3459 %conv = fptoui <8 x half> %x to <8 x i32> 3460 %spec.store.select = call <8 x i32> @llvm.umin.v8i32(<8 x i32> %conv, <8 x i32> <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535>) 3461 %conv6 = trunc <8 x i32> %spec.store.select to <8 x i16> 3462 ret <8 x i16> %conv6 3463} 3464 3465define <8 x i16> @ustest_f16i16_mm(<8 x half> %x) { 3466; CHECK-NEON-LABEL: ustest_f16i16_mm: 3467; CHECK-NEON: @ %bb.0: @ %entry 3468; CHECK-NEON-NEXT: .save {r4, r5, r6, r7, r11, lr} 3469; CHECK-NEON-NEXT: push {r4, r5, r6, r7, r11, lr} 3470; CHECK-NEON-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} 3471; CHECK-NEON-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} 3472; CHECK-NEON-NEXT: vmov r0, s1 3473; CHECK-NEON-NEXT: vmov.f32 s16, s7 3474; CHECK-NEON-NEXT: vmov.f32 s18, s6 3475; CHECK-NEON-NEXT: vmov.f32 s20, s5 3476; CHECK-NEON-NEXT: vmov.f32 s22, s4 3477; CHECK-NEON-NEXT: vmov.f32 s24, s3 3478; CHECK-NEON-NEXT: vmov.f32 s26, s2 3479; CHECK-NEON-NEXT: vmov.f32 s28, s0 3480; CHECK-NEON-NEXT: bl __aeabi_h2f 3481; CHECK-NEON-NEXT: mov r4, r0 3482; CHECK-NEON-NEXT: vmov r0, s26 3483; CHECK-NEON-NEXT: bl __aeabi_h2f 3484; CHECK-NEON-NEXT: mov r5, r0 3485; CHECK-NEON-NEXT: vmov r0, s22 3486; CHECK-NEON-NEXT: bl __aeabi_h2f 3487; CHECK-NEON-NEXT: mov r6, r0 3488; CHECK-NEON-NEXT: vmov r0, s24 3489; CHECK-NEON-NEXT: bl __aeabi_h2f 3490; CHECK-NEON-NEXT: mov r7, r0 3491; CHECK-NEON-NEXT: vmov r0, s18 3492; CHECK-NEON-NEXT: bl __aeabi_h2f 3493; CHECK-NEON-NEXT: vmov s0, r0 3494; CHECK-NEON-NEXT: vcvt.s32.f32 s0, s0 3495; CHECK-NEON-NEXT: vmov r0, s0 3496; CHECK-NEON-NEXT: vmov.32 d13[0], r0 3497; CHECK-NEON-NEXT: vmov r0, s16 3498; CHECK-NEON-NEXT: bl __aeabi_h2f 3499; CHECK-NEON-NEXT: vmov s0, r0 3500; CHECK-NEON-NEXT: vmov s22, r7 3501; CHECK-NEON-NEXT: vcvt.s32.f32 s0, s0 3502; CHECK-NEON-NEXT: vmov s30, r6 3503; CHECK-NEON-NEXT: vmov r0, s0 3504; CHECK-NEON-NEXT: vmov.32 d13[1], r0 3505; CHECK-NEON-NEXT: vmov r0, s28 3506; CHECK-NEON-NEXT: bl __aeabi_h2f 3507; CHECK-NEON-NEXT: vmov s0, r0 3508; CHECK-NEON-NEXT: vmov r1, s20 3509; CHECK-NEON-NEXT: vcvt.s32.f32 s0, s0 3510; CHECK-NEON-NEXT: vmov s2, r5 3511; CHECK-NEON-NEXT: vcvt.s32.f32 s20, s2 3512; CHECK-NEON-NEXT: vmov r0, s0 3513; CHECK-NEON-NEXT: vcvt.s32.f32 s0, s30 3514; CHECK-NEON-NEXT: vmov.32 d8[0], r0 3515; CHECK-NEON-NEXT: vmov r0, s0 3516; CHECK-NEON-NEXT: vmov.32 d12[0], r0 3517; CHECK-NEON-NEXT: mov r0, r1 3518; CHECK-NEON-NEXT: bl __aeabi_h2f 3519; CHECK-NEON-NEXT: vmov s0, r0 3520; CHECK-NEON-NEXT: vmov r0, s20 3521; CHECK-NEON-NEXT: vcvt.s32.f32 s0, s0 3522; CHECK-NEON-NEXT: vmov s2, r4 3523; CHECK-NEON-NEXT: vmov.i32 q8, #0xffff 3524; CHECK-NEON-NEXT: vcvt.s32.f32 s2, s2 3525; CHECK-NEON-NEXT: vmov.i32 q9, #0x0 3526; CHECK-NEON-NEXT: vmov.32 d9[0], r0 3527; CHECK-NEON-NEXT: vmov r0, s0 3528; CHECK-NEON-NEXT: vcvt.s32.f32 s0, s22 3529; CHECK-NEON-NEXT: vmov.32 d12[1], r0 3530; CHECK-NEON-NEXT: vmov r0, s0 3531; CHECK-NEON-NEXT: vmin.s32 q10, q6, q8 3532; CHECK-NEON-NEXT: vmax.s32 q10, q10, q9 3533; CHECK-NEON-NEXT: vmov.32 d9[1], r0 3534; CHECK-NEON-NEXT: vmov r0, s2 3535; CHECK-NEON-NEXT: vmovn.i32 d1, q10 3536; CHECK-NEON-NEXT: vmov.32 d8[1], r0 3537; CHECK-NEON-NEXT: vmin.s32 q8, q4, q8 3538; CHECK-NEON-NEXT: vmax.s32 q8, q8, q9 3539; CHECK-NEON-NEXT: vmovn.i32 d0, q8 3540; CHECK-NEON-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15} 3541; CHECK-NEON-NEXT: pop {r4, r5, r6, r7, r11, pc} 3542; 3543; CHECK-FP16-LABEL: ustest_f16i16_mm: 3544; CHECK-FP16: @ %bb.0: @ %entry 3545; CHECK-FP16-NEXT: vmovx.f16 s4, s0 3546; CHECK-FP16-NEXT: vcvt.s32.f16 s12, s0 3547; CHECK-FP16-NEXT: vcvt.s32.f16 s0, s3 3548; CHECK-FP16-NEXT: vcvt.s32.f16 s5, s2 3549; CHECK-FP16-NEXT: vmov r0, s0 3550; CHECK-FP16-NEXT: vcvt.s32.f16 s14, s1 3551; CHECK-FP16-NEXT: vmovx.f16 s10, s3 3552; CHECK-FP16-NEXT: vmovx.f16 s8, s2 3553; CHECK-FP16-NEXT: vcvt.s32.f16 s10, s10 3554; CHECK-FP16-NEXT: vcvt.s32.f16 s8, s8 3555; CHECK-FP16-NEXT: vmovx.f16 s6, s1 3556; CHECK-FP16-NEXT: vcvt.s32.f16 s4, s4 3557; CHECK-FP16-NEXT: vcvt.s32.f16 s6, s6 3558; CHECK-FP16-NEXT: vmov.i32 q10, #0xffff 3559; CHECK-FP16-NEXT: vmov.i32 q11, #0x0 3560; CHECK-FP16-NEXT: vmov.32 d17[0], r0 3561; CHECK-FP16-NEXT: vmov r0, s5 3562; CHECK-FP16-NEXT: vmov.32 d16[0], r0 3563; CHECK-FP16-NEXT: vmov r0, s14 3564; CHECK-FP16-NEXT: vmov.32 d19[0], r0 3565; CHECK-FP16-NEXT: vmov r0, s12 3566; CHECK-FP16-NEXT: vmov.32 d18[0], r0 3567; CHECK-FP16-NEXT: vmov r0, s10 3568; CHECK-FP16-NEXT: vmov.32 d17[1], r0 3569; CHECK-FP16-NEXT: vmov r0, s8 3570; CHECK-FP16-NEXT: vmov.32 d16[1], r0 3571; CHECK-FP16-NEXT: vmov r0, s6 3572; CHECK-FP16-NEXT: vmin.s32 q8, q8, q10 3573; CHECK-FP16-NEXT: vmax.s32 q8, q8, q11 3574; CHECK-FP16-NEXT: vmovn.i32 d1, q8 3575; CHECK-FP16-NEXT: vmov.32 d19[1], r0 3576; CHECK-FP16-NEXT: vmov r0, s4 3577; CHECK-FP16-NEXT: vmov.32 d18[1], r0 3578; CHECK-FP16-NEXT: vmin.s32 q9, q9, q10 3579; CHECK-FP16-NEXT: vmax.s32 q9, q9, q11 3580; CHECK-FP16-NEXT: vmovn.i32 d0, q9 3581; CHECK-FP16-NEXT: bx lr 3582entry: 3583 %conv = fptosi <8 x half> %x to <8 x i32> 3584 %spec.store.select = call <8 x i32> @llvm.smin.v8i32(<8 x i32> %conv, <8 x i32> <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535>) 3585 %spec.store.select7 = call <8 x i32> @llvm.smax.v8i32(<8 x i32> %spec.store.select, <8 x i32> zeroinitializer) 3586 %conv6 = trunc <8 x i32> %spec.store.select7 to <8 x i16> 3587 ret <8 x i16> %conv6 3588} 3589 3590; i64 saturate 3591 3592define <2 x i64> @stest_f64i64_mm(<2 x double> %x) { 3593; CHECK-LABEL: stest_f64i64_mm: 3594; CHECK: @ %bb.0: @ %entry 3595; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, lr} 3596; CHECK-NEXT: push {r4, r5, r6, r7, r8, r9, r10, lr} 3597; CHECK-NEXT: .vsave {d8, d9} 3598; CHECK-NEXT: vpush {d8, d9} 3599; CHECK-NEXT: vorr q4, q0, q0 3600; CHECK-NEXT: vorr d0, d9, d9 3601; CHECK-NEXT: bl __fixdfti 3602; CHECK-NEXT: mov r4, r1 3603; CHECK-NEXT: mvn r9, #0 3604; CHECK-NEXT: subs r1, r0, r9 3605; CHECK-NEXT: mvn r5, #-2147483648 3606; CHECK-NEXT: sbcs r1, r4, r5 3607; CHECK-NEXT: vorr d0, d8, d8 3608; CHECK-NEXT: sbcs r1, r2, #0 3609; CHECK-NEXT: mov r7, #0 3610; CHECK-NEXT: sbcs r1, r3, #0 3611; CHECK-NEXT: mov r8, #-2147483648 3612; CHECK-NEXT: mov r1, #0 3613; CHECK-NEXT: mov r10, #0 3614; CHECK-NEXT: movwlt r1, #1 3615; CHECK-NEXT: cmp r1, #0 3616; CHECK-NEXT: moveq r3, r1 3617; CHECK-NEXT: movne r1, r2 3618; CHECK-NEXT: moveq r4, r5 3619; CHECK-NEXT: moveq r0, r9 3620; CHECK-NEXT: rsbs r2, r0, #0 3621; CHECK-NEXT: rscs r2, r4, #-2147483648 3622; CHECK-NEXT: sbcs r1, r9, r1 3623; CHECK-NEXT: sbcs r1, r9, r3 3624; CHECK-NEXT: movwlt r7, #1 3625; CHECK-NEXT: cmp r7, #0 3626; CHECK-NEXT: movne r7, r0 3627; CHECK-NEXT: moveq r4, r8 3628; CHECK-NEXT: bl __fixdfti 3629; CHECK-NEXT: subs r6, r0, r9 3630; CHECK-NEXT: vmov.32 d1[0], r7 3631; CHECK-NEXT: sbcs r6, r1, r5 3632; CHECK-NEXT: sbcs r6, r2, #0 3633; CHECK-NEXT: sbcs r6, r3, #0 3634; CHECK-NEXT: mov r6, #0 3635; CHECK-NEXT: movwlt r6, #1 3636; CHECK-NEXT: cmp r6, #0 3637; CHECK-NEXT: moveq r3, r6 3638; CHECK-NEXT: movne r6, r2 3639; CHECK-NEXT: movne r5, r1 3640; CHECK-NEXT: moveq r0, r9 3641; CHECK-NEXT: rsbs r1, r0, #0 3642; CHECK-NEXT: rscs r1, r5, #-2147483648 3643; CHECK-NEXT: sbcs r1, r9, r6 3644; CHECK-NEXT: sbcs r1, r9, r3 3645; CHECK-NEXT: movwlt r10, #1 3646; CHECK-NEXT: cmp r10, #0 3647; CHECK-NEXT: movne r10, r0 3648; CHECK-NEXT: moveq r5, r8 3649; CHECK-NEXT: vmov.32 d0[0], r10 3650; CHECK-NEXT: vmov.32 d1[1], r4 3651; CHECK-NEXT: vmov.32 d0[1], r5 3652; CHECK-NEXT: vpop {d8, d9} 3653; CHECK-NEXT: pop {r4, r5, r6, r7, r8, r9, r10, pc} 3654entry: 3655 %conv = fptosi <2 x double> %x to <2 x i128> 3656 %spec.store.select = call <2 x i128> @llvm.smin.v2i128(<2 x i128> %conv, <2 x i128> <i128 9223372036854775807, i128 9223372036854775807>) 3657 %spec.store.select7 = call <2 x i128> @llvm.smax.v2i128(<2 x i128> %spec.store.select, <2 x i128> <i128 -9223372036854775808, i128 -9223372036854775808>) 3658 %conv6 = trunc <2 x i128> %spec.store.select7 to <2 x i64> 3659 ret <2 x i64> %conv6 3660} 3661 3662define <2 x i64> @utest_f64i64_mm(<2 x double> %x) { 3663; CHECK-LABEL: utest_f64i64_mm: 3664; CHECK: @ %bb.0: @ %entry 3665; CHECK-NEXT: .save {r4, r5, r6, lr} 3666; CHECK-NEXT: push {r4, r5, r6, lr} 3667; CHECK-NEXT: .vsave {d8, d9} 3668; CHECK-NEXT: vpush {d8, d9} 3669; CHECK-NEXT: vorr q4, q0, q0 3670; CHECK-NEXT: vorr d0, d9, d9 3671; CHECK-NEXT: bl __fixunsdfti 3672; CHECK-NEXT: mov r4, r1 3673; CHECK-NEXT: subs r1, r2, #1 3674; CHECK-NEXT: vorr d0, d8, d8 3675; CHECK-NEXT: sbcs r1, r3, #0 3676; CHECK-NEXT: mov r6, #0 3677; CHECK-NEXT: mov r5, #0 3678; CHECK-NEXT: movwlo r6, #1 3679; CHECK-NEXT: cmp r6, #0 3680; CHECK-NEXT: moveq r4, r6 3681; CHECK-NEXT: movne r6, r0 3682; CHECK-NEXT: bl __fixunsdfti 3683; CHECK-NEXT: subs r2, r2, #1 3684; CHECK-NEXT: vmov.32 d1[0], r6 3685; CHECK-NEXT: sbcs r2, r3, #0 3686; CHECK-NEXT: movwlo r5, #1 3687; CHECK-NEXT: cmp r5, #0 3688; CHECK-NEXT: moveq r0, r5 3689; CHECK-NEXT: movne r5, r1 3690; CHECK-NEXT: vmov.32 d0[0], r0 3691; CHECK-NEXT: vmov.32 d1[1], r4 3692; CHECK-NEXT: vmov.32 d0[1], r5 3693; CHECK-NEXT: vpop {d8, d9} 3694; CHECK-NEXT: pop {r4, r5, r6, pc} 3695entry: 3696 %conv = fptoui <2 x double> %x to <2 x i128> 3697 %spec.store.select = call <2 x i128> @llvm.umin.v2i128(<2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>) 3698 %conv6 = trunc <2 x i128> %spec.store.select to <2 x i64> 3699 ret <2 x i64> %conv6 3700} 3701 3702define <2 x i64> @ustest_f64i64_mm(<2 x double> %x) { 3703; CHECK-LABEL: ustest_f64i64_mm: 3704; CHECK: @ %bb.0: @ %entry 3705; CHECK-NEXT: .save {r4, r5, r6, lr} 3706; CHECK-NEXT: push {r4, r5, r6, lr} 3707; CHECK-NEXT: .vsave {d8, d9} 3708; CHECK-NEXT: vpush {d8, d9} 3709; CHECK-NEXT: vorr q4, q0, q0 3710; CHECK-NEXT: vorr d0, d9, d9 3711; CHECK-NEXT: bl __fixdfti 3712; CHECK-NEXT: mov r5, r0 3713; CHECK-NEXT: subs r0, r2, #1 3714; CHECK-NEXT: sbcs r0, r3, #0 3715; CHECK-NEXT: vorr d0, d8, d8 3716; CHECK-NEXT: mov r0, #0 3717; CHECK-NEXT: mov r4, r1 3718; CHECK-NEXT: movwlt r0, #1 3719; CHECK-NEXT: cmp r0, #0 3720; CHECK-NEXT: moveq r5, r0 3721; CHECK-NEXT: moveq r4, r0 3722; CHECK-NEXT: movne r0, r3 3723; CHECK-NEXT: cmp r0, #0 3724; CHECK-NEXT: mov r6, #0 3725; CHECK-NEXT: movwmi r4, #0 3726; CHECK-NEXT: movwmi r5, #0 3727; CHECK-NEXT: bl __fixdfti 3728; CHECK-NEXT: subs r2, r2, #1 3729; CHECK-NEXT: vmov.32 d1[0], r5 3730; CHECK-NEXT: sbcs r2, r3, #0 3731; CHECK-NEXT: movwlt r6, #1 3732; CHECK-NEXT: cmp r6, #0 3733; CHECK-NEXT: moveq r1, r6 3734; CHECK-NEXT: moveq r0, r6 3735; CHECK-NEXT: movne r6, r3 3736; CHECK-NEXT: cmp r6, #0 3737; CHECK-NEXT: movwmi r0, #0 3738; CHECK-NEXT: movwmi r1, #0 3739; CHECK-NEXT: vmov.32 d0[0], r0 3740; CHECK-NEXT: vmov.32 d1[1], r4 3741; CHECK-NEXT: vmov.32 d0[1], r1 3742; CHECK-NEXT: vpop {d8, d9} 3743; CHECK-NEXT: pop {r4, r5, r6, pc} 3744entry: 3745 %conv = fptosi <2 x double> %x to <2 x i128> 3746 %spec.store.select = call <2 x i128> @llvm.smin.v2i128(<2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>) 3747 %spec.store.select7 = call <2 x i128> @llvm.smax.v2i128(<2 x i128> %spec.store.select, <2 x i128> zeroinitializer) 3748 %conv6 = trunc <2 x i128> %spec.store.select7 to <2 x i64> 3749 ret <2 x i64> %conv6 3750} 3751 3752define <2 x i64> @stest_f32i64_mm(<2 x float> %x) { 3753; CHECK-LABEL: stest_f32i64_mm: 3754; CHECK: @ %bb.0: @ %entry 3755; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, lr} 3756; CHECK-NEXT: push {r4, r5, r6, r7, r8, r9, r10, lr} 3757; CHECK-NEXT: .vsave {d8} 3758; CHECK-NEXT: vpush {d8} 3759; CHECK-NEXT: vmov.f64 d8, d0 3760; CHECK-NEXT: vmov.f32 s0, s17 3761; CHECK-NEXT: bl __fixsfti 3762; CHECK-NEXT: mov r4, r1 3763; CHECK-NEXT: mvn r9, #0 3764; CHECK-NEXT: subs r1, r0, r9 3765; CHECK-NEXT: mvn r5, #-2147483648 3766; CHECK-NEXT: sbcs r1, r4, r5 3767; CHECK-NEXT: vmov.f32 s0, s16 3768; CHECK-NEXT: sbcs r1, r2, #0 3769; CHECK-NEXT: mov r7, #0 3770; CHECK-NEXT: sbcs r1, r3, #0 3771; CHECK-NEXT: mov r8, #-2147483648 3772; CHECK-NEXT: mov r1, #0 3773; CHECK-NEXT: mov r10, #0 3774; CHECK-NEXT: movwlt r1, #1 3775; CHECK-NEXT: cmp r1, #0 3776; CHECK-NEXT: moveq r3, r1 3777; CHECK-NEXT: movne r1, r2 3778; CHECK-NEXT: moveq r4, r5 3779; CHECK-NEXT: moveq r0, r9 3780; CHECK-NEXT: rsbs r2, r0, #0 3781; CHECK-NEXT: rscs r2, r4, #-2147483648 3782; CHECK-NEXT: sbcs r1, r9, r1 3783; CHECK-NEXT: sbcs r1, r9, r3 3784; CHECK-NEXT: movwlt r7, #1 3785; CHECK-NEXT: cmp r7, #0 3786; CHECK-NEXT: movne r7, r0 3787; CHECK-NEXT: moveq r4, r8 3788; CHECK-NEXT: bl __fixsfti 3789; CHECK-NEXT: subs r6, r0, r9 3790; CHECK-NEXT: vmov.32 d1[0], r7 3791; CHECK-NEXT: sbcs r6, r1, r5 3792; CHECK-NEXT: sbcs r6, r2, #0 3793; CHECK-NEXT: sbcs r6, r3, #0 3794; CHECK-NEXT: mov r6, #0 3795; CHECK-NEXT: movwlt r6, #1 3796; CHECK-NEXT: cmp r6, #0 3797; CHECK-NEXT: moveq r3, r6 3798; CHECK-NEXT: movne r6, r2 3799; CHECK-NEXT: movne r5, r1 3800; CHECK-NEXT: moveq r0, r9 3801; CHECK-NEXT: rsbs r1, r0, #0 3802; CHECK-NEXT: rscs r1, r5, #-2147483648 3803; CHECK-NEXT: sbcs r1, r9, r6 3804; CHECK-NEXT: sbcs r1, r9, r3 3805; CHECK-NEXT: movwlt r10, #1 3806; CHECK-NEXT: cmp r10, #0 3807; CHECK-NEXT: movne r10, r0 3808; CHECK-NEXT: moveq r5, r8 3809; CHECK-NEXT: vmov.32 d0[0], r10 3810; CHECK-NEXT: vmov.32 d1[1], r4 3811; CHECK-NEXT: vmov.32 d0[1], r5 3812; CHECK-NEXT: vpop {d8} 3813; CHECK-NEXT: pop {r4, r5, r6, r7, r8, r9, r10, pc} 3814entry: 3815 %conv = fptosi <2 x float> %x to <2 x i128> 3816 %spec.store.select = call <2 x i128> @llvm.smin.v2i128(<2 x i128> %conv, <2 x i128> <i128 9223372036854775807, i128 9223372036854775807>) 3817 %spec.store.select7 = call <2 x i128> @llvm.smax.v2i128(<2 x i128> %spec.store.select, <2 x i128> <i128 -9223372036854775808, i128 -9223372036854775808>) 3818 %conv6 = trunc <2 x i128> %spec.store.select7 to <2 x i64> 3819 ret <2 x i64> %conv6 3820} 3821 3822define <2 x i64> @utest_f32i64_mm(<2 x float> %x) { 3823; CHECK-LABEL: utest_f32i64_mm: 3824; CHECK: @ %bb.0: @ %entry 3825; CHECK-NEXT: .save {r4, r5, r6, lr} 3826; CHECK-NEXT: push {r4, r5, r6, lr} 3827; CHECK-NEXT: .vsave {d8} 3828; CHECK-NEXT: vpush {d8} 3829; CHECK-NEXT: vmov.f64 d8, d0 3830; CHECK-NEXT: vmov.f32 s0, s17 3831; CHECK-NEXT: bl __fixunssfti 3832; CHECK-NEXT: vmov.f32 s0, s16 3833; CHECK-NEXT: mov r4, r1 3834; CHECK-NEXT: subs r1, r2, #1 3835; CHECK-NEXT: mov r6, #0 3836; CHECK-NEXT: sbcs r1, r3, #0 3837; CHECK-NEXT: mov r5, #0 3838; CHECK-NEXT: movwlo r6, #1 3839; CHECK-NEXT: cmp r6, #0 3840; CHECK-NEXT: moveq r4, r6 3841; CHECK-NEXT: movne r6, r0 3842; CHECK-NEXT: bl __fixunssfti 3843; CHECK-NEXT: subs r2, r2, #1 3844; CHECK-NEXT: vmov.32 d1[0], r6 3845; CHECK-NEXT: sbcs r2, r3, #0 3846; CHECK-NEXT: movwlo r5, #1 3847; CHECK-NEXT: cmp r5, #0 3848; CHECK-NEXT: moveq r0, r5 3849; CHECK-NEXT: movne r5, r1 3850; CHECK-NEXT: vmov.32 d0[0], r0 3851; CHECK-NEXT: vmov.32 d1[1], r4 3852; CHECK-NEXT: vmov.32 d0[1], r5 3853; CHECK-NEXT: vpop {d8} 3854; CHECK-NEXT: pop {r4, r5, r6, pc} 3855entry: 3856 %conv = fptoui <2 x float> %x to <2 x i128> 3857 %spec.store.select = call <2 x i128> @llvm.umin.v2i128(<2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>) 3858 %conv6 = trunc <2 x i128> %spec.store.select to <2 x i64> 3859 ret <2 x i64> %conv6 3860} 3861 3862define <2 x i64> @ustest_f32i64_mm(<2 x float> %x) { 3863; CHECK-LABEL: ustest_f32i64_mm: 3864; CHECK: @ %bb.0: @ %entry 3865; CHECK-NEXT: .save {r4, r5, r6, lr} 3866; CHECK-NEXT: push {r4, r5, r6, lr} 3867; CHECK-NEXT: .vsave {d8} 3868; CHECK-NEXT: vpush {d8} 3869; CHECK-NEXT: vmov.f64 d8, d0 3870; CHECK-NEXT: vmov.f32 s0, s17 3871; CHECK-NEXT: bl __fixsfti 3872; CHECK-NEXT: vmov.f32 s0, s16 3873; CHECK-NEXT: mov r5, r0 3874; CHECK-NEXT: subs r0, r2, #1 3875; CHECK-NEXT: mov r4, r1 3876; CHECK-NEXT: sbcs r0, r3, #0 3877; CHECK-NEXT: mov r6, #0 3878; CHECK-NEXT: mov r0, #0 3879; CHECK-NEXT: movwlt r0, #1 3880; CHECK-NEXT: cmp r0, #0 3881; CHECK-NEXT: moveq r5, r0 3882; CHECK-NEXT: moveq r4, r0 3883; CHECK-NEXT: movne r0, r3 3884; CHECK-NEXT: cmp r0, #0 3885; CHECK-NEXT: movwmi r4, #0 3886; CHECK-NEXT: movwmi r5, #0 3887; CHECK-NEXT: bl __fixsfti 3888; CHECK-NEXT: subs r2, r2, #1 3889; CHECK-NEXT: vmov.32 d1[0], r5 3890; CHECK-NEXT: sbcs r2, r3, #0 3891; CHECK-NEXT: movwlt r6, #1 3892; CHECK-NEXT: cmp r6, #0 3893; CHECK-NEXT: moveq r1, r6 3894; CHECK-NEXT: moveq r0, r6 3895; CHECK-NEXT: movne r6, r3 3896; CHECK-NEXT: cmp r6, #0 3897; CHECK-NEXT: movwmi r0, #0 3898; CHECK-NEXT: movwmi r1, #0 3899; CHECK-NEXT: vmov.32 d0[0], r0 3900; CHECK-NEXT: vmov.32 d1[1], r4 3901; CHECK-NEXT: vmov.32 d0[1], r1 3902; CHECK-NEXT: vpop {d8} 3903; CHECK-NEXT: pop {r4, r5, r6, pc} 3904entry: 3905 %conv = fptosi <2 x float> %x to <2 x i128> 3906 %spec.store.select = call <2 x i128> @llvm.smin.v2i128(<2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>) 3907 %spec.store.select7 = call <2 x i128> @llvm.smax.v2i128(<2 x i128> %spec.store.select, <2 x i128> zeroinitializer) 3908 %conv6 = trunc <2 x i128> %spec.store.select7 to <2 x i64> 3909 ret <2 x i64> %conv6 3910} 3911 3912define <2 x i64> @stest_f16i64_mm(<2 x half> %x) { 3913; CHECK-NEON-LABEL: stest_f16i64_mm: 3914; CHECK-NEON: @ %bb.0: @ %entry 3915; CHECK-NEON-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, lr} 3916; CHECK-NEON-NEXT: push {r4, r5, r6, r7, r8, r9, r10, lr} 3917; CHECK-NEON-NEXT: .vsave {d8} 3918; CHECK-NEON-NEXT: vpush {d8} 3919; CHECK-NEON-NEXT: vmov r0, s0 3920; CHECK-NEON-NEXT: vmov.f32 s16, s1 3921; CHECK-NEON-NEXT: bl __aeabi_h2f 3922; CHECK-NEON-NEXT: mov r8, r0 3923; CHECK-NEON-NEXT: vmov r0, s16 3924; CHECK-NEON-NEXT: bl __aeabi_h2f 3925; CHECK-NEON-NEXT: vmov s0, r0 3926; CHECK-NEON-NEXT: bl __fixsfti 3927; CHECK-NEON-NEXT: mov r4, r1 3928; CHECK-NEON-NEXT: mvn r9, #0 3929; CHECK-NEON-NEXT: subs r1, r0, r9 3930; CHECK-NEON-NEXT: mvn r6, #-2147483648 3931; CHECK-NEON-NEXT: sbcs r1, r4, r6 3932; CHECK-NEON-NEXT: vmov s0, r8 3933; CHECK-NEON-NEXT: sbcs r1, r2, #0 3934; CHECK-NEON-NEXT: mov r5, #0 3935; CHECK-NEON-NEXT: sbcs r1, r3, #0 3936; CHECK-NEON-NEXT: mov r8, #-2147483648 3937; CHECK-NEON-NEXT: mov r1, #0 3938; CHECK-NEON-NEXT: mov r10, #0 3939; CHECK-NEON-NEXT: movwlt r1, #1 3940; CHECK-NEON-NEXT: cmp r1, #0 3941; CHECK-NEON-NEXT: moveq r3, r1 3942; CHECK-NEON-NEXT: movne r1, r2 3943; CHECK-NEON-NEXT: moveq r4, r6 3944; CHECK-NEON-NEXT: moveq r0, r9 3945; CHECK-NEON-NEXT: rsbs r2, r0, #0 3946; CHECK-NEON-NEXT: rscs r2, r4, #-2147483648 3947; CHECK-NEON-NEXT: sbcs r1, r9, r1 3948; CHECK-NEON-NEXT: sbcs r1, r9, r3 3949; CHECK-NEON-NEXT: movwlt r5, #1 3950; CHECK-NEON-NEXT: cmp r5, #0 3951; CHECK-NEON-NEXT: movne r5, r0 3952; CHECK-NEON-NEXT: moveq r4, r8 3953; CHECK-NEON-NEXT: bl __fixsfti 3954; CHECK-NEON-NEXT: subs r7, r0, r9 3955; CHECK-NEON-NEXT: vmov.32 d1[0], r5 3956; CHECK-NEON-NEXT: sbcs r7, r1, r6 3957; CHECK-NEON-NEXT: sbcs r7, r2, #0 3958; CHECK-NEON-NEXT: sbcs r7, r3, #0 3959; CHECK-NEON-NEXT: mov r7, #0 3960; CHECK-NEON-NEXT: movwlt r7, #1 3961; CHECK-NEON-NEXT: cmp r7, #0 3962; CHECK-NEON-NEXT: moveq r3, r7 3963; CHECK-NEON-NEXT: movne r7, r2 3964; CHECK-NEON-NEXT: movne r6, r1 3965; CHECK-NEON-NEXT: moveq r0, r9 3966; CHECK-NEON-NEXT: rsbs r1, r0, #0 3967; CHECK-NEON-NEXT: rscs r1, r6, #-2147483648 3968; CHECK-NEON-NEXT: sbcs r1, r9, r7 3969; CHECK-NEON-NEXT: sbcs r1, r9, r3 3970; CHECK-NEON-NEXT: movwlt r10, #1 3971; CHECK-NEON-NEXT: cmp r10, #0 3972; CHECK-NEON-NEXT: movne r10, r0 3973; CHECK-NEON-NEXT: moveq r6, r8 3974; CHECK-NEON-NEXT: vmov.32 d0[0], r10 3975; CHECK-NEON-NEXT: vmov.32 d1[1], r4 3976; CHECK-NEON-NEXT: vmov.32 d0[1], r6 3977; CHECK-NEON-NEXT: vpop {d8} 3978; CHECK-NEON-NEXT: pop {r4, r5, r6, r7, r8, r9, r10, pc} 3979; 3980; CHECK-FP16-LABEL: stest_f16i64_mm: 3981; CHECK-FP16: @ %bb.0: @ %entry 3982; CHECK-FP16-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, lr} 3983; CHECK-FP16-NEXT: push {r4, r5, r6, r7, r8, r9, r10, lr} 3984; CHECK-FP16-NEXT: vmov.u16 r0, d0[1] 3985; CHECK-FP16-NEXT: vmov.u16 r7, d0[0] 3986; CHECK-FP16-NEXT: vmov s0, r0 3987; CHECK-FP16-NEXT: bl __fixhfti 3988; CHECK-FP16-NEXT: mov r4, r1 3989; CHECK-FP16-NEXT: mvn r9, #0 3990; CHECK-FP16-NEXT: subs r1, r0, r9 3991; CHECK-FP16-NEXT: mvn r5, #-2147483648 3992; CHECK-FP16-NEXT: sbcs r1, r4, r5 3993; CHECK-FP16-NEXT: vmov s0, r7 3994; CHECK-FP16-NEXT: sbcs r1, r2, #0 3995; CHECK-FP16-NEXT: mov r7, #0 3996; CHECK-FP16-NEXT: sbcs r1, r3, #0 3997; CHECK-FP16-NEXT: mov r8, #-2147483648 3998; CHECK-FP16-NEXT: mov r1, #0 3999; CHECK-FP16-NEXT: mov r10, #0 4000; CHECK-FP16-NEXT: movwlt r1, #1 4001; CHECK-FP16-NEXT: cmp r1, #0 4002; CHECK-FP16-NEXT: moveq r3, r1 4003; CHECK-FP16-NEXT: movne r1, r2 4004; CHECK-FP16-NEXT: moveq r4, r5 4005; CHECK-FP16-NEXT: moveq r0, r9 4006; CHECK-FP16-NEXT: rsbs r2, r0, #0 4007; CHECK-FP16-NEXT: rscs r2, r4, #-2147483648 4008; CHECK-FP16-NEXT: sbcs r1, r9, r1 4009; CHECK-FP16-NEXT: sbcs r1, r9, r3 4010; CHECK-FP16-NEXT: movwlt r7, #1 4011; CHECK-FP16-NEXT: cmp r7, #0 4012; CHECK-FP16-NEXT: movne r7, r0 4013; CHECK-FP16-NEXT: moveq r4, r8 4014; CHECK-FP16-NEXT: bl __fixhfti 4015; CHECK-FP16-NEXT: subs r6, r0, r9 4016; CHECK-FP16-NEXT: vmov.32 d1[0], r7 4017; CHECK-FP16-NEXT: sbcs r6, r1, r5 4018; CHECK-FP16-NEXT: sbcs r6, r2, #0 4019; CHECK-FP16-NEXT: sbcs r6, r3, #0 4020; CHECK-FP16-NEXT: mov r6, #0 4021; CHECK-FP16-NEXT: movwlt r6, #1 4022; CHECK-FP16-NEXT: cmp r6, #0 4023; CHECK-FP16-NEXT: moveq r3, r6 4024; CHECK-FP16-NEXT: movne r6, r2 4025; CHECK-FP16-NEXT: movne r5, r1 4026; CHECK-FP16-NEXT: moveq r0, r9 4027; CHECK-FP16-NEXT: rsbs r1, r0, #0 4028; CHECK-FP16-NEXT: rscs r1, r5, #-2147483648 4029; CHECK-FP16-NEXT: sbcs r1, r9, r6 4030; CHECK-FP16-NEXT: sbcs r1, r9, r3 4031; CHECK-FP16-NEXT: movwlt r10, #1 4032; CHECK-FP16-NEXT: cmp r10, #0 4033; CHECK-FP16-NEXT: movne r10, r0 4034; CHECK-FP16-NEXT: moveq r5, r8 4035; CHECK-FP16-NEXT: vmov.32 d0[0], r10 4036; CHECK-FP16-NEXT: vmov.32 d1[1], r4 4037; CHECK-FP16-NEXT: vmov.32 d0[1], r5 4038; CHECK-FP16-NEXT: pop {r4, r5, r6, r7, r8, r9, r10, pc} 4039entry: 4040 %conv = fptosi <2 x half> %x to <2 x i128> 4041 %spec.store.select = call <2 x i128> @llvm.smin.v2i128(<2 x i128> %conv, <2 x i128> <i128 9223372036854775807, i128 9223372036854775807>) 4042 %spec.store.select7 = call <2 x i128> @llvm.smax.v2i128(<2 x i128> %spec.store.select, <2 x i128> <i128 -9223372036854775808, i128 -9223372036854775808>) 4043 %conv6 = trunc <2 x i128> %spec.store.select7 to <2 x i64> 4044 ret <2 x i64> %conv6 4045} 4046 4047define <2 x i64> @utesth_f16i64_mm(<2 x half> %x) { 4048; CHECK-NEON-LABEL: utesth_f16i64_mm: 4049; CHECK-NEON: @ %bb.0: @ %entry 4050; CHECK-NEON-NEXT: .save {r4, r5, r6, lr} 4051; CHECK-NEON-NEXT: push {r4, r5, r6, lr} 4052; CHECK-NEON-NEXT: .vsave {d8} 4053; CHECK-NEON-NEXT: vpush {d8} 4054; CHECK-NEON-NEXT: vmov r0, s0 4055; CHECK-NEON-NEXT: vmov.f32 s16, s1 4056; CHECK-NEON-NEXT: bl __aeabi_h2f 4057; CHECK-NEON-NEXT: mov r5, r0 4058; CHECK-NEON-NEXT: vmov r0, s16 4059; CHECK-NEON-NEXT: bl __aeabi_h2f 4060; CHECK-NEON-NEXT: vmov s0, r0 4061; CHECK-NEON-NEXT: bl __fixunssfti 4062; CHECK-NEON-NEXT: mov r4, r1 4063; CHECK-NEON-NEXT: subs r1, r2, #1 4064; CHECK-NEON-NEXT: vmov s0, r5 4065; CHECK-NEON-NEXT: sbcs r1, r3, #0 4066; CHECK-NEON-NEXT: mov r5, #0 4067; CHECK-NEON-NEXT: mov r6, #0 4068; CHECK-NEON-NEXT: movwlo r5, #1 4069; CHECK-NEON-NEXT: cmp r5, #0 4070; CHECK-NEON-NEXT: moveq r4, r5 4071; CHECK-NEON-NEXT: movne r5, r0 4072; CHECK-NEON-NEXT: bl __fixunssfti 4073; CHECK-NEON-NEXT: subs r2, r2, #1 4074; CHECK-NEON-NEXT: vmov.32 d1[0], r5 4075; CHECK-NEON-NEXT: sbcs r2, r3, #0 4076; CHECK-NEON-NEXT: movwlo r6, #1 4077; CHECK-NEON-NEXT: cmp r6, #0 4078; CHECK-NEON-NEXT: moveq r0, r6 4079; CHECK-NEON-NEXT: movne r6, r1 4080; CHECK-NEON-NEXT: vmov.32 d0[0], r0 4081; CHECK-NEON-NEXT: vmov.32 d1[1], r4 4082; CHECK-NEON-NEXT: vmov.32 d0[1], r6 4083; CHECK-NEON-NEXT: vpop {d8} 4084; CHECK-NEON-NEXT: pop {r4, r5, r6, pc} 4085; 4086; CHECK-FP16-LABEL: utesth_f16i64_mm: 4087; CHECK-FP16: @ %bb.0: @ %entry 4088; CHECK-FP16-NEXT: .save {r4, r5, r6, lr} 4089; CHECK-FP16-NEXT: push {r4, r5, r6, lr} 4090; CHECK-FP16-NEXT: vmov.u16 r0, d0[1] 4091; CHECK-FP16-NEXT: vmov.u16 r6, d0[0] 4092; CHECK-FP16-NEXT: vmov s0, r0 4093; CHECK-FP16-NEXT: bl __fixunshfti 4094; CHECK-FP16-NEXT: mov r4, r1 4095; CHECK-FP16-NEXT: subs r1, r2, #1 4096; CHECK-FP16-NEXT: vmov s0, r6 4097; CHECK-FP16-NEXT: sbcs r1, r3, #0 4098; CHECK-FP16-NEXT: mov r6, #0 4099; CHECK-FP16-NEXT: mov r5, #0 4100; CHECK-FP16-NEXT: movwlo r6, #1 4101; CHECK-FP16-NEXT: cmp r6, #0 4102; CHECK-FP16-NEXT: moveq r4, r6 4103; CHECK-FP16-NEXT: movne r6, r0 4104; CHECK-FP16-NEXT: bl __fixunshfti 4105; CHECK-FP16-NEXT: subs r2, r2, #1 4106; CHECK-FP16-NEXT: vmov.32 d1[0], r6 4107; CHECK-FP16-NEXT: sbcs r2, r3, #0 4108; CHECK-FP16-NEXT: movwlo r5, #1 4109; CHECK-FP16-NEXT: cmp r5, #0 4110; CHECK-FP16-NEXT: moveq r0, r5 4111; CHECK-FP16-NEXT: movne r5, r1 4112; CHECK-FP16-NEXT: vmov.32 d0[0], r0 4113; CHECK-FP16-NEXT: vmov.32 d1[1], r4 4114; CHECK-FP16-NEXT: vmov.32 d0[1], r5 4115; CHECK-FP16-NEXT: pop {r4, r5, r6, pc} 4116entry: 4117 %conv = fptoui <2 x half> %x to <2 x i128> 4118 %spec.store.select = call <2 x i128> @llvm.umin.v2i128(<2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>) 4119 %conv6 = trunc <2 x i128> %spec.store.select to <2 x i64> 4120 ret <2 x i64> %conv6 4121} 4122 4123define <2 x i64> @ustest_f16i64_mm(<2 x half> %x) { 4124; CHECK-NEON-LABEL: ustest_f16i64_mm: 4125; CHECK-NEON: @ %bb.0: @ %entry 4126; CHECK-NEON-NEXT: .save {r4, r5, r6, r7, r11, lr} 4127; CHECK-NEON-NEXT: push {r4, r5, r6, r7, r11, lr} 4128; CHECK-NEON-NEXT: .vsave {d8} 4129; CHECK-NEON-NEXT: vpush {d8} 4130; CHECK-NEON-NEXT: vmov r0, s0 4131; CHECK-NEON-NEXT: vmov.f32 s16, s1 4132; CHECK-NEON-NEXT: bl __aeabi_h2f 4133; CHECK-NEON-NEXT: mov r6, r0 4134; CHECK-NEON-NEXT: vmov r0, s16 4135; CHECK-NEON-NEXT: bl __aeabi_h2f 4136; CHECK-NEON-NEXT: vmov s0, r0 4137; CHECK-NEON-NEXT: bl __fixsfti 4138; CHECK-NEON-NEXT: mov r5, r0 4139; CHECK-NEON-NEXT: subs r0, r2, #1 4140; CHECK-NEON-NEXT: sbcs r0, r3, #0 4141; CHECK-NEON-NEXT: vmov s0, r6 4142; CHECK-NEON-NEXT: mov r0, #0 4143; CHECK-NEON-NEXT: mov r4, r1 4144; CHECK-NEON-NEXT: movwlt r0, #1 4145; CHECK-NEON-NEXT: cmp r0, #0 4146; CHECK-NEON-NEXT: moveq r5, r0 4147; CHECK-NEON-NEXT: moveq r4, r0 4148; CHECK-NEON-NEXT: movne r0, r3 4149; CHECK-NEON-NEXT: cmp r0, #0 4150; CHECK-NEON-NEXT: mov r7, #0 4151; CHECK-NEON-NEXT: movwmi r4, #0 4152; CHECK-NEON-NEXT: movwmi r5, #0 4153; CHECK-NEON-NEXT: bl __fixsfti 4154; CHECK-NEON-NEXT: subs r2, r2, #1 4155; CHECK-NEON-NEXT: vmov.32 d1[0], r5 4156; CHECK-NEON-NEXT: sbcs r2, r3, #0 4157; CHECK-NEON-NEXT: movwlt r7, #1 4158; CHECK-NEON-NEXT: cmp r7, #0 4159; CHECK-NEON-NEXT: moveq r1, r7 4160; CHECK-NEON-NEXT: moveq r0, r7 4161; CHECK-NEON-NEXT: movne r7, r3 4162; CHECK-NEON-NEXT: cmp r7, #0 4163; CHECK-NEON-NEXT: movwmi r0, #0 4164; CHECK-NEON-NEXT: movwmi r1, #0 4165; CHECK-NEON-NEXT: vmov.32 d0[0], r0 4166; CHECK-NEON-NEXT: vmov.32 d1[1], r4 4167; CHECK-NEON-NEXT: vmov.32 d0[1], r1 4168; CHECK-NEON-NEXT: vpop {d8} 4169; CHECK-NEON-NEXT: pop {r4, r5, r6, r7, r11, pc} 4170; 4171; CHECK-FP16-LABEL: ustest_f16i64_mm: 4172; CHECK-FP16: @ %bb.0: @ %entry 4173; CHECK-FP16-NEXT: .save {r4, r5, r6, r7, r11, lr} 4174; CHECK-FP16-NEXT: push {r4, r5, r6, r7, r11, lr} 4175; CHECK-FP16-NEXT: vmov.u16 r0, d0[1] 4176; CHECK-FP16-NEXT: vmov.u16 r7, d0[0] 4177; CHECK-FP16-NEXT: vmov s0, r0 4178; CHECK-FP16-NEXT: bl __fixhfti 4179; CHECK-FP16-NEXT: mov r5, r0 4180; CHECK-FP16-NEXT: subs r0, r2, #1 4181; CHECK-FP16-NEXT: sbcs r0, r3, #0 4182; CHECK-FP16-NEXT: vmov s0, r7 4183; CHECK-FP16-NEXT: mov r0, #0 4184; CHECK-FP16-NEXT: mov r4, r1 4185; CHECK-FP16-NEXT: movwlt r0, #1 4186; CHECK-FP16-NEXT: cmp r0, #0 4187; CHECK-FP16-NEXT: moveq r5, r0 4188; CHECK-FP16-NEXT: moveq r4, r0 4189; CHECK-FP16-NEXT: movne r0, r3 4190; CHECK-FP16-NEXT: cmp r0, #0 4191; CHECK-FP16-NEXT: mov r6, #0 4192; CHECK-FP16-NEXT: movwmi r4, #0 4193; CHECK-FP16-NEXT: movwmi r5, #0 4194; CHECK-FP16-NEXT: bl __fixhfti 4195; CHECK-FP16-NEXT: subs r2, r2, #1 4196; CHECK-FP16-NEXT: vmov.32 d1[0], r5 4197; CHECK-FP16-NEXT: sbcs r2, r3, #0 4198; CHECK-FP16-NEXT: movwlt r6, #1 4199; CHECK-FP16-NEXT: cmp r6, #0 4200; CHECK-FP16-NEXT: moveq r1, r6 4201; CHECK-FP16-NEXT: moveq r0, r6 4202; CHECK-FP16-NEXT: movne r6, r3 4203; CHECK-FP16-NEXT: cmp r6, #0 4204; CHECK-FP16-NEXT: movwmi r0, #0 4205; CHECK-FP16-NEXT: movwmi r1, #0 4206; CHECK-FP16-NEXT: vmov.32 d0[0], r0 4207; CHECK-FP16-NEXT: vmov.32 d1[1], r4 4208; CHECK-FP16-NEXT: vmov.32 d0[1], r1 4209; CHECK-FP16-NEXT: pop {r4, r5, r6, r7, r11, pc} 4210entry: 4211 %conv = fptosi <2 x half> %x to <2 x i128> 4212 %spec.store.select = call <2 x i128> @llvm.smin.v2i128(<2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>) 4213 %spec.store.select7 = call <2 x i128> @llvm.smax.v2i128(<2 x i128> %spec.store.select, <2 x i128> zeroinitializer) 4214 %conv6 = trunc <2 x i128> %spec.store.select7 to <2 x i64> 4215 ret <2 x i64> %conv6 4216} 4217 4218declare <2 x i32> @llvm.smin.v2i32(<2 x i32>, <2 x i32>) 4219declare <2 x i32> @llvm.smax.v2i32(<2 x i32>, <2 x i32>) 4220declare <2 x i32> @llvm.umin.v2i32(<2 x i32>, <2 x i32>) 4221declare <4 x i32> @llvm.smin.v4i32(<4 x i32>, <4 x i32>) 4222declare <4 x i32> @llvm.smax.v4i32(<4 x i32>, <4 x i32>) 4223declare <4 x i32> @llvm.umin.v4i32(<4 x i32>, <4 x i32>) 4224declare <8 x i32> @llvm.smin.v8i32(<8 x i32>, <8 x i32>) 4225declare <8 x i32> @llvm.smax.v8i32(<8 x i32>, <8 x i32>) 4226declare <8 x i32> @llvm.umin.v8i32(<8 x i32>, <8 x i32>) 4227declare <2 x i64> @llvm.smin.v2i64(<2 x i64>, <2 x i64>) 4228declare <2 x i64> @llvm.smax.v2i64(<2 x i64>, <2 x i64>) 4229declare <2 x i64> @llvm.umin.v2i64(<2 x i64>, <2 x i64>) 4230declare <4 x i64> @llvm.smin.v4i64(<4 x i64>, <4 x i64>) 4231declare <4 x i64> @llvm.smax.v4i64(<4 x i64>, <4 x i64>) 4232declare <4 x i64> @llvm.umin.v4i64(<4 x i64>, <4 x i64>) 4233declare <2 x i128> @llvm.smin.v2i128(<2 x i128>, <2 x i128>) 4234declare <2 x i128> @llvm.smax.v2i128(<2 x i128>, <2 x i128>) 4235declare <2 x i128> @llvm.umin.v2i128(<2 x i128>, <2 x i128>) 4236