1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple armv8a-none-none-eabihf -mattr=fullfp16 < %s | FileCheck %s 3 4define <4 x half> @fptrunc_vector_f32_f16(<4 x float> %a) { 5; CHECK-LABEL: fptrunc_vector_f32_f16: 6; CHECK: @ %bb.0: @ %bb 7; CHECK-NEXT: vcvt.f16.f32 d0, q0 8; CHECK-NEXT: bx lr 9bb: 10 %z = fptrunc <4 x float> %a to <4 x half> 11 ret <4 x half> %z 12} 13 14define <4 x half> @fptrunc_vector_f64_f16(<4 x double> %a) { 15; CHECK-LABEL: fptrunc_vector_f64_f16: 16; CHECK: @ %bb.0: @ %bb 17; CHECK-NEXT: vcvtb.f16.f64 s0, d0 18; CHECK-NEXT: vcvtb.f16.f64 s8, d1 19; CHECK-NEXT: vmov r1, s0 20; CHECK-NEXT: vcvtb.f16.f64 s2, d2 21; CHECK-NEXT: vmov r0, s8 22; CHECK-NEXT: vmov.16 d0[0], r1 23; CHECK-NEXT: vmov.16 d0[1], r0 24; CHECK-NEXT: vmov r0, s2 25; CHECK-NEXT: vcvtb.f16.f64 s2, d3 26; CHECK-NEXT: vmov.16 d0[2], r0 27; CHECK-NEXT: vmov r0, s2 28; CHECK-NEXT: vmov.16 d0[3], r0 29; CHECK-NEXT: bx lr 30bb: 31 %z = fptrunc <4 x double> %a to <4 x half> 32 ret <4 x half> %z 33} 34 35define <4 x float> @fpext_vector_f16_f32(<4 x half> %a) { 36; CHECK-LABEL: fpext_vector_f16_f32: 37; CHECK: @ %bb.0: @ %bb 38; CHECK-NEXT: vcvt.f32.f16 q0, d0 39; CHECK-NEXT: bx lr 40bb: 41 %z = fpext <4 x half> %a to <4 x float> 42 ret <4 x float> %z 43} 44 45define <4 x double> @fpext_vector_f16_f64(<4 x half> %a) { 46; CHECK-LABEL: fpext_vector_f16_f64: 47; CHECK: @ %bb.0: @ %bb 48; CHECK-NEXT: vmovx.f16 s4, s0 49; CHECK-NEXT: vmovx.f16 s2, s1 50; CHECK-NEXT: vcvtb.f64.f16 d17, s4 51; CHECK-NEXT: vcvtb.f64.f16 d3, s2 52; CHECK-NEXT: vcvtb.f64.f16 d16, s0 53; CHECK-NEXT: vcvtb.f64.f16 d2, s1 54; CHECK-NEXT: vorr q0, q8, q8 55; CHECK-NEXT: bx lr 56bb: 57 %z = fpext <4 x half> %a to <4 x double> 58 ret <4 x double> %z 59} 60