xref: /llvm-project/llvm/test/CodeGen/ARM/fast-isel-ldrh-strh-arm.ll (revision bed1c7f061aa12417aa081e334afdba45767b938) 
1; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
2; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM
3; rdar://10418009
4
5define zeroext i16 @t1(ptr nocapture %a) nounwind uwtable readonly ssp {
6entry:
7; ARM-LABEL: t1:
8  %add.ptr = getelementptr inbounds i16, ptr %a, i64 -8
9  %0 = load i16, ptr %add.ptr, align 2
10; ARM: ldrh r0, [r0, #-16]
11  ret i16 %0
12}
13
14define zeroext i16 @t2(ptr nocapture %a) nounwind uwtable readonly ssp {
15entry:
16; ARM-LABEL: t2:
17  %add.ptr = getelementptr inbounds i16, ptr %a, i64 -16
18  %0 = load i16, ptr %add.ptr, align 2
19; ARM: ldrh r0, [r0, #-32]
20  ret i16 %0
21}
22
23define zeroext i16 @t3(ptr nocapture %a) nounwind uwtable readonly ssp {
24entry:
25; ARM-LABEL: t3:
26  %add.ptr = getelementptr inbounds i16, ptr %a, i64 -127
27  %0 = load i16, ptr %add.ptr, align 2
28; ARM: ldrh r0, [r0, #-254]
29  ret i16 %0
30}
31
32define zeroext i16 @t4(ptr nocapture %a) nounwind uwtable readonly ssp {
33entry:
34; ARM-LABEL: t4:
35  %add.ptr = getelementptr inbounds i16, ptr %a, i64 -128
36  %0 = load i16, ptr %add.ptr, align 2
37; ARM: mvn r{{[1-9]}}, #255
38; ARM: add r0, r0, r{{[1-9]}}
39; ARM: ldrh r0, [r0]
40  ret i16 %0
41}
42
43define zeroext i16 @t5(ptr nocapture %a) nounwind uwtable readonly ssp {
44entry:
45; ARM-LABEL: t5:
46  %add.ptr = getelementptr inbounds i16, ptr %a, i64 8
47  %0 = load i16, ptr %add.ptr, align 2
48; ARM: ldrh r0, [r0, #16]
49  ret i16 %0
50}
51
52define zeroext i16 @t6(ptr nocapture %a) nounwind uwtable readonly ssp {
53entry:
54; ARM-LABEL: t6:
55  %add.ptr = getelementptr inbounds i16, ptr %a, i64 16
56  %0 = load i16, ptr %add.ptr, align 2
57; ARM: ldrh r0, [r0, #32]
58  ret i16 %0
59}
60
61define zeroext i16 @t7(ptr nocapture %a) nounwind uwtable readonly ssp {
62entry:
63; ARM-LABEL: t7:
64  %add.ptr = getelementptr inbounds i16, ptr %a, i64 127
65  %0 = load i16, ptr %add.ptr, align 2
66; ARM: ldrh r0, [r0, #254]
67  ret i16 %0
68}
69
70define zeroext i16 @t8(ptr nocapture %a) nounwind uwtable readonly ssp {
71entry:
72; ARM-LABEL: t8:
73  %add.ptr = getelementptr inbounds i16, ptr %a, i64 128
74  %0 = load i16, ptr %add.ptr, align 2
75; ARM: add r0, r0, #256
76; ARM: ldrh r0, [r0]
77  ret i16 %0
78}
79
80define void @t9(ptr nocapture %a) nounwind uwtable ssp {
81entry:
82; ARM-LABEL: t9:
83  %add.ptr = getelementptr inbounds i16, ptr %a, i64 -8
84  store i16 0, ptr %add.ptr, align 2
85; ARM: movw [[REG0:r[0-9]+]], #0
86; ARM: strh [[REG0]], [{{r[0-9]+}}, #-16]
87  ret void
88}
89
90; mvn r1, #255
91; strh r2, [r0, r1]
92define void @t10(ptr nocapture %a) nounwind uwtable ssp {
93entry:
94; ARM-LABEL: t10:
95  %add.ptr = getelementptr inbounds i16, ptr %a, i64 -128
96  store i16 0, ptr %add.ptr, align 2
97; ARM: mov r1, r0
98; ARM: movw [[REG1:r[0-9]+]], #0
99; ARM: mvn [[REG2:r[0-9]+]], #255
100; ARM: add [[REG0:r[0-9]+]], r1, [[REG2]]
101; ARM: strh [[REG1]], [[[REG0]]]
102  ret void
103}
104
105define void @t11(ptr nocapture %a) nounwind uwtable ssp {
106entry:
107; ARM-LABEL: t11:
108  %add.ptr = getelementptr inbounds i16, ptr %a, i64 8
109  store i16 0, ptr %add.ptr, align 2
110; ARM: movw [[REG1:r[0-9]+]], #0
111; ARM: strh [[REG1]], [{{r[0-9]+}}, #16]
112  ret void
113}
114
115; mov r1, #256
116; strh r2, [r0, r1]
117define void @t12(ptr nocapture %a) nounwind uwtable ssp {
118entry:
119; ARM-LABEL: t12:
120  %add.ptr = getelementptr inbounds i16, ptr %a, i64 128
121  store i16 0, ptr %add.ptr, align 2
122; ARM: mov r1, r0
123; ARM: movw [[REG1:r[0-9]+]], #0
124; ARM: add [[REG0:r[0-9]+]], r1, #256
125; ARM: strh [[REG1]], [[[REG0]]]
126  ret void
127}
128
129define signext i8 @t13(ptr nocapture %a) nounwind uwtable readonly ssp {
130entry:
131; ARM-LABEL: t13:
132  %add.ptr = getelementptr inbounds i8, ptr %a, i64 -8
133  %0 = load i8, ptr %add.ptr, align 2
134; ARM: ldrsb r0, [r0, #-8]
135  ret i8 %0
136}
137
138define signext i8 @t14(ptr nocapture %a) nounwind uwtable readonly ssp {
139entry:
140; ARM-LABEL: t14:
141  %add.ptr = getelementptr inbounds i8, ptr %a, i64 -255
142  %0 = load i8, ptr %add.ptr, align 2
143; ARM: ldrsb r0, [r0, #-255]
144  ret i8 %0
145}
146
147define signext i8 @t15(ptr nocapture %a) nounwind uwtable readonly ssp {
148entry:
149; ARM-LABEL: t15:
150  %add.ptr = getelementptr inbounds i8, ptr %a, i64 -256
151  %0 = load i8, ptr %add.ptr, align 2
152; ARM: mvn r{{[1-9]}}, #255
153; ARM: add r0, r0, r{{[1-9]}}
154; ARM: ldrsb r0, [r0]
155  ret i8 %0
156}
157