xref: /llvm-project/llvm/test/CodeGen/ARM/expand-pseudos.mir (revision 5ca09d617da89c4466347030e2949dc5713eabcb) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -run-pass=arm-pseudo -verify-machineinstrs %s -o - | FileCheck %s
3--- |
4  target triple = "armv7---gnueabi"
5
6  define i32 @test1(i32 %x) {
7  entry:
8    unreachable
9  }
10  define i32 @test2(i32 %x) {
11  entry:
12    unreachable
13  }
14  define i32 @test3(i32 %x) {
15  entry:
16    unreachable
17  }
18  define i32 @test4(i32 %x) {
19  entry:
20    unreachable
21  }
22  @var = global i32 0
23  define i32 @test5(i32 %x) {
24  entry:
25    unreachable
26  }
27  define i32 @vbsl_kill_flags(i32 %x) {
28    unreachable
29  }
30...
31---
32name:            test1
33alignment:       4
34tracksRegLiveness: true
35liveins:
36  - { reg: '$r0', virtual-reg: '' }
37body:             |
38  bb.0.entry:
39    liveins: $r0
40
41    ; CHECK-LABEL: name: test1
42    ; CHECK: liveins: $r0
43    ; CHECK-NEXT: {{  $}}
44    ; CHECK-NEXT: $r1 = MOVi 2, 14 /* CC::al */, $noreg, $noreg
45    ; CHECK-NEXT: CMPri killed $r0, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
46    ; CHECK-NEXT: $r1 = MOVi16 500, 0 /* CC::eq */, killed $cpsr, implicit killed $r1
47    ; CHECK-NEXT: $r0 = MOVr killed $r1, 14 /* CC::al */, $noreg, $noreg
48    ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
49    $r1 = MOVi 2, 14, $noreg, $noreg
50    CMPri killed $r0, 0, 14, $noreg, implicit-def $cpsr
51    $r1 = MOVCCi16 killed $r1, 500, 0, killed $cpsr
52    $r0 = MOVr killed $r1, 14, $noreg, $noreg
53    BX_RET 14, $noreg, implicit $r0
54
55...
56---
57name:            test2
58alignment:       4
59tracksRegLiveness: true
60liveins:
61  - { reg: '$r0', virtual-reg: '' }
62body:             |
63  bb.0.entry:
64    liveins: $r0
65
66    ; CHECK-LABEL: name: test2
67    ; CHECK: liveins: $r0
68    ; CHECK-NEXT: {{  $}}
69    ; CHECK-NEXT: $r1 = MOVi 2, 14 /* CC::al */, $noreg, $noreg
70    ; CHECK-NEXT: CMPri killed $r0, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
71    ; CHECK-NEXT: $r1 = MOVi16 2068, 0 /* CC::eq */, $cpsr, implicit killed $r1
72    ; CHECK-NEXT: $r1 = MOVTi16 $r1, 7637, 0 /* CC::eq */, $cpsr
73    ; CHECK-NEXT: $r0 = MOVr killed $r1, 14 /* CC::al */, $noreg, $noreg
74    ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
75    $r1 = MOVi 2, 14, $noreg, $noreg
76    CMPri killed $r0, 0, 14, $noreg, implicit-def $cpsr
77    $r1 = MOVCCi32imm killed $r1, 500500500, 0, killed $cpsr
78    $r0 = MOVr killed $r1, 14, $noreg, $noreg
79    BX_RET 14, $noreg, implicit $r0
80
81...
82---
83name:            test3
84alignment:       4
85tracksRegLiveness: true
86liveins:
87  - { reg: '$r0', virtual-reg: '' }
88  - { reg: '$r1', virtual-reg: '' }
89body:             |
90  bb.0.entry:
91    liveins: $r0, $r1
92
93    ; CHECK-LABEL: name: test3
94    ; CHECK: liveins: $r0, $r1
95    ; CHECK-NEXT: {{  $}}
96    ; CHECK-NEXT: CMPri $r1, 500, 14 /* CC::al */, $noreg, implicit-def $cpsr
97    ; CHECK-NEXT: $r0 = MOVr killed $r1, 12 /* CC::gt */, killed $cpsr, $noreg, implicit killed $r0
98    ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
99    CMPri $r1, 500, 14, $noreg, implicit-def $cpsr
100    $r0 = MOVCCr killed $r0, killed $r1, 12, killed $cpsr
101    BX_RET 14, $noreg, implicit $r0
102
103...
104---
105name:            test4
106alignment:       4
107tracksRegLiveness: true
108liveins:
109  - { reg: '$r0', virtual-reg: '' }
110  - { reg: '$r0_r1', virtual-reg: '' }
111body:             |
112  bb.0.entry:
113    liveins: $r0, $r0_r1
114
115    ; CHECK-LABEL: name: test4
116    ; CHECK: liveins: $r0, $r0_r1
117    ; CHECK-NEXT: {{  $}}
118    ; CHECK-NEXT: $r0 = MOVi16 51712, 14 /* CC::al */, $noreg, implicit-def $r0_r1
119    ; CHECK-NEXT: $r0 = MOVTi16 $r0, 15258, 14 /* CC::al */, $noreg, implicit-def $r0_r1
120    ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
121    $r0 = MOVi32imm 1000000000, implicit-def $r0_r1
122    BX_RET 14, $noreg, implicit $r0
123
124...
125---
126name:            test5
127alignment:       4
128tracksRegLiveness: true
129liveins:
130  - { reg: '$r0', virtual-reg: '' }
131  - { reg: '$r0_r1', virtual-reg: '' }
132body:             |
133  bb.0.entry:
134    liveins: $r0, $r0_r1
135
136    ; CHECK-LABEL: name: test5
137    ; CHECK: liveins: $r0, $r0_r1
138    ; CHECK-NEXT: {{  $}}
139    ; CHECK-NEXT: $r0 = MOVi16_ga_pcrel target-flags(arm-lo16) @var, 0, implicit-def $r0_r1
140    ; CHECK-NEXT: $r0 = MOVTi16_ga_pcrel $r0, target-flags(arm-hi16) @var, 0, implicit-def $r0_r1
141    ; CHECK-NEXT: $r0 = PICLDR $r0, 0, 14 /* CC::al */, $noreg, implicit-def $r0_r1
142    ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
143    $r0 = MOV_ga_pcrel_ldr @var, implicit-def $r0_r1
144    BX_RET 14, $noreg, implicit $r0
145
146...
147---
148name:            vbsl_kill_flags
149alignment:       4
150tracksRegLiveness: true
151body:             |
152  bb.0 (%ir-block.0):
153    liveins: $d1
154
155    ; CHECK-LABEL: name: vbsl_kill_flags
156    ; CHECK: liveins: $d1
157    ; CHECK-NEXT: {{  $}}
158    ; CHECK-NEXT: renamable $d0 = VORRd renamable $d1, renamable $d1, 14 /* CC::al */, $noreg
159    ; CHECK-NEXT: renamable $d0 = VBSLd killed renamable $d0, renamable $d1, renamable $d1, 14 /* CC::al */, $noreg
160    ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $d0
161    renamable $d0 = VBSPd killed renamable $d1, renamable $d1, renamable $d1, 14 /* CC::al */, $noreg
162    BX_RET 14 /* CC::al */, $noreg, implicit $d0
163
164...
165