1; RUN: llc -filetype=obj -relocation-model=pic --verify-machineinstrs -print-after=postrapseudos < %s 2>&1 | FileCheck -check-prefix=CHECK-POST-RA %s 2; RUN: llc -filetype=obj -relocation-model=pic --verify-machineinstrs -print-after=arm-pseudo < %s 2>&1 | FileCheck -check-prefix=CHECK-POST-AP %s 3 4; CHECK-POST-RA: $r12 = t2LDRLIT_ga_pcrel target-flags(arm-got) @__stack_chk_guard 5; CHECK-POST-AP: $r12 = t2LDRpci %const.0, 14, $noreg 6 7target triple = "thumbv7-unknown-linux-android23" 8 9%"class.v8::internal::Assembler" = type {} 10%"class.v8::internal::Operand" = type { %"class.v8::internal::Register", %"class.v8::internal::Register", i32, i32, %"union.v8::internal::Operand::Value" } 11%"class.v8::internal::Register" = type {} 12%"union.v8::internal::Operand::Value" = type { i32, [20 x i8] } 13%"class.v8::internal::wasm::LiftoffAssembler" = type {} 14 15declare void @_ZN2v88internal9Assembler3addENS0_8RegisterES2_RKNS0_7OperandENS0_4SBitENS0_9ConditionE(ptr, [1 x i32], [1 x i32], ptr, i32, i32) 16 17; Function Attrs: ssp 18define void @_ZN2v88internal4wasm16LiftoffAssembler13emit_i32_addiENS0_8RegisterES3_i(ptr %0, [1 x i32] %1, [1 x i32] %2, i32 %3) #0 { 19 %5 = alloca %"class.v8::internal::Operand", align 8 20 %6 = getelementptr %"class.v8::internal::Operand", ptr %5 21 %7 = getelementptr %"class.v8::internal::Operand", ptr %5 22 %8 = getelementptr %"class.v8::internal::Operand", ptr %5 23 %9 = getelementptr %"class.v8::internal::Operand", ptr %5 24 %10 = getelementptr %"class.v8::internal::Operand", ptr %5, i32 0, i32 4, i32 0 25 store i32 %3, ptr %10, align 4 26 call void @_ZN2v88internal9Assembler3addENS0_8RegisterES2_RKNS0_7OperandENS0_4SBitENS0_9ConditionE(ptr %0, [1 x i32] %1, [1 x i32] %2, ptr %5, i32 0, i32 2) 27 ret void 28} 29 30attributes #0 = { ssp } 31 32!llvm.module.flags = !{!0} 33!0 = !{i32 7, !"PIC Level", i32 2} 34