xref: /llvm-project/llvm/test/CodeGen/ARM/execute-only-big-stack-frame.ll (revision 1b12b1a33520fc3a1cb7b22274312a86ce7a3718)
1; RUN: llc < %s -mtriple=thumbv7m -mattr=+execute-only -O0 %s -o - \
2; RUN:  | FileCheck --check-prefix=CHECK-SUBW-ADDW %s
3; RUN: llc < %s -mtriple=thumbv8m.base -mattr=+execute-only -O0 %s -o - \
4; RUN:  | FileCheck --check-prefix=CHECK-MOVW-MOVT-ADD %s
5; RUN: llc < %s -mtriple=thumbv8m.base -mcpu=cortex-m23 -mattr=+execute-only -O0 %s -o - \
6; RUN:  | FileCheck --check-prefix=CHECK-MOVW-MOVT-ADD %s
7; RUN: llc < %s -mtriple=thumbv8m.main -mattr=+execute-only -O0 %s -o - \
8; RUN:  | FileCheck --check-prefix=CHECK-SUBW-ADDW %s
9
10define i8 @test_big_stack_frame() {
11; CHECK-SUBW-ADDW-LABEL: test_big_stack_frame:
12; CHECK-SUBW-ADDW-NOT:   ldr {{r[0-9]+}}, .{{.*}}
13; CHECK-SUBW-ADDW:       sub.w sp, sp, #65536
14; CHECK-SUBW-ADDW-NOT:   ldr {{r[0-9]+}}, .{{.*}}
15; CHECK-SUBW-ADDW:       add.w [[REG1:r[0-9]+|lr]], sp, #255
16; CHECK-SUBW-ADDW:       add.w {{r[0-9]+}}, [[REG1]], #65280
17; CHECK-SUBW-ADDW-NOT:   ldr {{r[0-9]+}}, .{{.*}}
18; CHECK-SUBW-ADDW:       add.w [[REGX:r[0-9]+|lr]], sp, #61440
19; CHECK-SUBW-ADDW-NOT:   ldr {{r[0-9]+}}, .{{.*}}
20; CHECK-SUBW-ADDW:       add.w sp, sp, #65536
21
22; CHECK-MOVW-MOVT-ADD-LABEL: test_big_stack_frame:
23; CHECK-MOVW-MOVT-ADD-NOT:   ldr {{r[0-9]+}}, .{{.*}}
24; CHECK-MOVW-MOVT-ADD:       movw [[REG1:r[0-9]+]], #0
25; CHECK-MOVW-MOVT-ADD:       movt [[REG1]], #65535
26; CHECK-MOVW-MOVT-ADD:       add sp, [[REG1]]
27; CHECK-MOVW-MOVT-ADD-NOT:   ldr {{r[0-9]+}}, .{{.*}}
28; CHECK-MOVW-MOVT-ADD:       movw [[REG2:r[0-9]+]], #65532
29; CHECK-MOVW-MOVT-ADD:       add [[REG2]], sp
30; CHECK-MOVW-MOVT-ADD-NOT:   ldr {{r[0-9]+}}, .{{.*}}
31; CHECK-MOVW-MOVT-ADD:       movw [[REG3:r[0-9]+]], #65532
32; CHECK-MOVW-MOVT-ADD:       add [[REG3]], sp
33; CHECK-MOVW-MOVT-ADD-NOT:   ldr {{r[0-9]+}}, .{{.*}}
34; CHECK-MOVW-MOVT-ADD:       movw [[REG4:r[0-9]+]], #0
35; CHECK-MOVW-MOVT-ADD:       movt [[REG4]], #1
36; CHECK-MOVW-MOVT-ADD:       add sp, [[REG4]]
37
38entry:
39  %s1 = alloca i8
40  %buffer = alloca [65528 x i8], align 1
41  call void @foo(ptr %s1)
42  %load = load i8, ptr %s1
43  ret i8 %load
44}
45
46declare void @foo(ptr)
47