1; REQUIRES: asserts 2; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-r52 -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s --check-prefix=CHECK --check-prefix=R52_SCHED 3; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-r52plus -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s --check-prefix=CHECK --check-prefix=R52_SCHED 4; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=generic -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s --check-prefix=CHECK --check-prefix=GENERIC 5; 6; Check the latency for instructions for both generic and cortex-r52. 7; Cortex-r52 machine model will cause the div to be sceduled before eor 8; as div takes more cycles to compute than eor. 9; 10; CHECK: ********** MI Scheduling ********** 11; CHECK: foo:%bb.0 entry 12; CHECK: EORrr 13; GENERIC: Latency : 1 14; R52_SCHED: Latency : 3 15; CHECK: MLA 16; GENERIC: Latency : 2 17; R52_SCHED: Latency : 4 18; CHECK: SDIV 19; GENERIC: Latency : 0 20; R52_SCHED: Latency : 8 21; CHECK: ** Final schedule for %bb.0 *** 22; GENERIC: EORrr 23; GENERIC: SDIV 24; R52_SCHED: SDIV 25; R52_SCHED: EORrr 26; CHECK: ********** INTERVALS ********** 27 28target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 29target triple = "armv8r-arm-none-eabi" 30 31; Function Attrs: norecurse nounwind readnone 32define hidden i32 @foo(i32 %a, i32 %b, i32 %c) local_unnamed_addr #0 { 33entry: 34 %xor = xor i32 %c, %b 35 %mul = mul nsw i32 %xor, %c 36 %add = add nsw i32 %mul, %a 37 %div = sdiv i32 %a, %b 38 %sub = sub i32 %add, %div 39 ret i32 %sub 40} 41