1; REQUIRES: asserts 2; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -mattr=use-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s 3; N=3 STMIB should have latency 2cyc 4 5; CHECK: ********** MI Scheduling ********** 6; We need second, post-ra scheduling to have STM instruction combined from single-stores 7; CHECK: ********** MI Scheduling ********** 8; CHECK: schedule starting 9; CHECK: STMIB 10; CHECK: rdefs left 11; CHECK-NEXT: Latency : 2 12 13define i32 @test_stm(i32 %v0, i32 %v1, ptr %addr) { 14 15 %addr.1 = getelementptr i32, ptr %addr, i32 1 16 store i32 %v0, ptr %addr.1 17 18 %addr.2 = getelementptr i32, ptr %addr, i32 2 19 store i32 %v1, ptr %addr.2 20 21 %addr.3 = getelementptr i32, ptr %addr, i32 3 22 %val = ptrtoint ptr %addr to i32 23 store i32 %val, ptr %addr.3 24 25 %rv = add i32 %v0, %v1 26 27 ret i32 %rv 28} 29 30