xref: /llvm-project/llvm/test/CodeGen/ARM/consthoist-icmpimm.ll (revision 945a1468c922573a07b334a130d05f0ecca40926) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=thumbv6m-none-eabi | FileCheck %s --check-prefix=CHECKV6M
3; RUN: llc < %s -mtriple=thumbv7m-none-eabi | FileCheck %s --check-prefix=CHECKV7M
4; RUN: llc < %s -mtriple=thumbv7a-none-eabi | FileCheck %s --check-prefix=CHECKV7A
5
6define i32 @icmp64_sge_0(i64 %x, i64 %y, i32 %a, i32 %b, i1 %c) {
7; CHECKV6M-LABEL: icmp64_sge_0:
8; CHECKV6M:       @ %bb.0:
9; CHECKV6M-NEXT:    ldr r0, [sp, #8]
10; CHECKV6M-NEXT:    lsls r0, r0, #31
11; CHECKV6M-NEXT:    ldr r2, [sp, #4]
12; CHECKV6M-NEXT:    ldr r0, [sp]
13; CHECKV6M-NEXT:    beq .LBB0_4
14; CHECKV6M-NEXT:  @ %bb.1: @ %then
15; CHECKV6M-NEXT:    cmp r3, #0
16; CHECKV6M-NEXT:    mov r3, r0
17; CHECKV6M-NEXT:    blt .LBB0_7
18; CHECKV6M-NEXT:  @ %bb.2: @ %then
19; CHECKV6M-NEXT:    cmp r1, #0
20; CHECKV6M-NEXT:    blt .LBB0_8
21; CHECKV6M-NEXT:  .LBB0_3: @ %then
22; CHECKV6M-NEXT:    adds r0, r0, r3
23; CHECKV6M-NEXT:    bx lr
24; CHECKV6M-NEXT:  .LBB0_4: @ %else
25; CHECKV6M-NEXT:    cmp r1, #0
26; CHECKV6M-NEXT:    bge .LBB0_6
27; CHECKV6M-NEXT:  @ %bb.5: @ %else
28; CHECKV6M-NEXT:    mov r0, r2
29; CHECKV6M-NEXT:  .LBB0_6: @ %else
30; CHECKV6M-NEXT:    bx lr
31; CHECKV6M-NEXT:  .LBB0_7: @ %then
32; CHECKV6M-NEXT:    mov r3, r2
33; CHECKV6M-NEXT:    cmp r1, #0
34; CHECKV6M-NEXT:    bge .LBB0_3
35; CHECKV6M-NEXT:  .LBB0_8: @ %then
36; CHECKV6M-NEXT:    mov r0, r2
37; CHECKV6M-NEXT:    adds r0, r0, r3
38; CHECKV6M-NEXT:    bx lr
39;
40; CHECKV7M-LABEL: icmp64_sge_0:
41; CHECKV7M:       @ %bb.0:
42; CHECKV7M-NEXT:    ldr r0, [sp, #8]
43; CHECKV7M-NEXT:    lsls r0, r0, #31
44; CHECKV7M-NEXT:    ldrd r2, r0, [sp]
45; CHECKV7M-NEXT:    beq .LBB0_2
46; CHECKV7M-NEXT:  @ %bb.1: @ %then
47; CHECKV7M-NEXT:    cmp.w r3, #-1
48; CHECKV7M-NEXT:    mov r3, r0
49; CHECKV7M-NEXT:    it gt
50; CHECKV7M-NEXT:    movgt r3, r2
51; CHECKV7M-NEXT:    cmp.w r1, #-1
52; CHECKV7M-NEXT:    it gt
53; CHECKV7M-NEXT:    movgt r0, r2
54; CHECKV7M-NEXT:    add r0, r3
55; CHECKV7M-NEXT:    bx lr
56; CHECKV7M-NEXT:  .LBB0_2: @ %else
57; CHECKV7M-NEXT:    cmp.w r1, #-1
58; CHECKV7M-NEXT:    it gt
59; CHECKV7M-NEXT:    movgt r0, r2
60; CHECKV7M-NEXT:    bx lr
61;
62; CHECKV7A-LABEL: icmp64_sge_0:
63; CHECKV7A:       @ %bb.0:
64; CHECKV7A-NEXT:    ldr r2, [sp, #8]
65; CHECKV7A-NEXT:    ldrd r12, r0, [sp]
66; CHECKV7A-NEXT:    lsls r2, r2, #31
67; CHECKV7A-NEXT:    beq .LBB0_2
68; CHECKV7A-NEXT:  @ %bb.1: @ %then
69; CHECKV7A-NEXT:    cmp.w r3, #-1
70; CHECKV7A-NEXT:    mov r2, r0
71; CHECKV7A-NEXT:    it gt
72; CHECKV7A-NEXT:    movgt r2, r12
73; CHECKV7A-NEXT:    cmp.w r1, #-1
74; CHECKV7A-NEXT:    it gt
75; CHECKV7A-NEXT:    movgt r0, r12
76; CHECKV7A-NEXT:    add r0, r2
77; CHECKV7A-NEXT:    bx lr
78; CHECKV7A-NEXT:  .LBB0_2: @ %else
79; CHECKV7A-NEXT:    cmp.w r1, #-1
80; CHECKV7A-NEXT:    it gt
81; CHECKV7A-NEXT:    movgt r0, r12
82; CHECKV7A-NEXT:    bx lr
83  br i1 %c, label %then, label %else
84then:
85  %c1 = icmp sge i64 %x, 0
86  %c2 = icmp sge i64 %y, 0
87  %s1 = select i1 %c1, i32 %a, i32 %b
88  %s2 = select i1 %c2, i32 %a, i32 %b
89  %r = add i32 %s1, %s2
90  ret i32 %r
91else:
92  %c3 = icmp sge i64 %x, 0
93  %s3 = select i1 %c3, i32 %a, i32 %b
94  ret i32 %s3
95}
96
97define i32 @icmp64_sgt_m1(i64 %x, i64 %y, i32 %a, i32 %b, i1 %c) {
98; CHECKV6M-LABEL: icmp64_sgt_m1:
99; CHECKV6M:       @ %bb.0:
100; CHECKV6M-NEXT:    ldr r0, [sp, #8]
101; CHECKV6M-NEXT:    lsls r0, r0, #31
102; CHECKV6M-NEXT:    ldr r2, [sp, #4]
103; CHECKV6M-NEXT:    ldr r0, [sp]
104; CHECKV6M-NEXT:    beq .LBB1_4
105; CHECKV6M-NEXT:  @ %bb.1: @ %then
106; CHECKV6M-NEXT:    cmp r3, #0
107; CHECKV6M-NEXT:    mov r3, r0
108; CHECKV6M-NEXT:    blt .LBB1_7
109; CHECKV6M-NEXT:  @ %bb.2: @ %then
110; CHECKV6M-NEXT:    cmp r1, #0
111; CHECKV6M-NEXT:    blt .LBB1_8
112; CHECKV6M-NEXT:  .LBB1_3: @ %then
113; CHECKV6M-NEXT:    adds r0, r0, r3
114; CHECKV6M-NEXT:    bx lr
115; CHECKV6M-NEXT:  .LBB1_4: @ %else
116; CHECKV6M-NEXT:    cmp r3, #0
117; CHECKV6M-NEXT:    bge .LBB1_6
118; CHECKV6M-NEXT:  @ %bb.5: @ %else
119; CHECKV6M-NEXT:    mov r0, r2
120; CHECKV6M-NEXT:  .LBB1_6: @ %else
121; CHECKV6M-NEXT:    bx lr
122; CHECKV6M-NEXT:  .LBB1_7: @ %then
123; CHECKV6M-NEXT:    mov r3, r2
124; CHECKV6M-NEXT:    cmp r1, #0
125; CHECKV6M-NEXT:    bge .LBB1_3
126; CHECKV6M-NEXT:  .LBB1_8: @ %then
127; CHECKV6M-NEXT:    mov r0, r2
128; CHECKV6M-NEXT:    adds r0, r0, r3
129; CHECKV6M-NEXT:    bx lr
130;
131; CHECKV7M-LABEL: icmp64_sgt_m1:
132; CHECKV7M:       @ %bb.0:
133; CHECKV7M-NEXT:    ldr r0, [sp, #8]
134; CHECKV7M-NEXT:    lsls r0, r0, #31
135; CHECKV7M-NEXT:    ldrd r2, r0, [sp]
136; CHECKV7M-NEXT:    beq .LBB1_2
137; CHECKV7M-NEXT:  @ %bb.1: @ %then
138; CHECKV7M-NEXT:    cmp.w r3, #-1
139; CHECKV7M-NEXT:    mov r3, r0
140; CHECKV7M-NEXT:    it gt
141; CHECKV7M-NEXT:    movgt r3, r2
142; CHECKV7M-NEXT:    cmp.w r1, #-1
143; CHECKV7M-NEXT:    it gt
144; CHECKV7M-NEXT:    movgt r0, r2
145; CHECKV7M-NEXT:    add r0, r3
146; CHECKV7M-NEXT:    bx lr
147; CHECKV7M-NEXT:  .LBB1_2: @ %else
148; CHECKV7M-NEXT:    cmp.w r3, #-1
149; CHECKV7M-NEXT:    it gt
150; CHECKV7M-NEXT:    movgt r0, r2
151; CHECKV7M-NEXT:    bx lr
152;
153; CHECKV7A-LABEL: icmp64_sgt_m1:
154; CHECKV7A:       @ %bb.0:
155; CHECKV7A-NEXT:    ldr r2, [sp, #8]
156; CHECKV7A-NEXT:    ldrd r12, r0, [sp]
157; CHECKV7A-NEXT:    lsls r2, r2, #31
158; CHECKV7A-NEXT:    beq .LBB1_2
159; CHECKV7A-NEXT:  @ %bb.1: @ %then
160; CHECKV7A-NEXT:    cmp.w r3, #-1
161; CHECKV7A-NEXT:    mov r2, r0
162; CHECKV7A-NEXT:    it gt
163; CHECKV7A-NEXT:    movgt r2, r12
164; CHECKV7A-NEXT:    cmp.w r1, #-1
165; CHECKV7A-NEXT:    it gt
166; CHECKV7A-NEXT:    movgt r0, r12
167; CHECKV7A-NEXT:    add r0, r2
168; CHECKV7A-NEXT:    bx lr
169; CHECKV7A-NEXT:  .LBB1_2: @ %else
170; CHECKV7A-NEXT:    cmp.w r3, #-1
171; CHECKV7A-NEXT:    it gt
172; CHECKV7A-NEXT:    movgt r0, r12
173; CHECKV7A-NEXT:    bx lr
174  br i1 %c, label %then, label %else
175then:
176  %c1 = icmp sgt i64 %x, -1
177  %c2 = icmp sgt i64 %y, -1
178  %s1 = select i1 %c1, i32 %a, i32 %b
179  %s2 = select i1 %c2, i32 %a, i32 %b
180  %r = add i32 %s1, %s2
181  ret i32 %r
182else:
183  %c3 = icmp sgt i64 %y, -1
184  %s3 = select i1 %c3, i32 %a, i32 %b
185  ret i32 %s3
186}
187
188define i32 @icmp32_sge_0(i32 %x, i32 %y, i32 %a, i32 %b, i1 %c) {
189; CHECKV6M-LABEL: icmp32_sge_0:
190; CHECKV6M:       @ %bb.0:
191; CHECKV6M-NEXT:    .save {r4, lr}
192; CHECKV6M-NEXT:    push {r4, lr}
193; CHECKV6M-NEXT:    ldr r4, [sp, #8]
194; CHECKV6M-NEXT:    lsls r4, r4, #31
195; CHECKV6M-NEXT:    beq .LBB2_4
196; CHECKV6M-NEXT:  @ %bb.1: @ %then
197; CHECKV6M-NEXT:    cmp r1, #0
198; CHECKV6M-NEXT:    mov r1, r2
199; CHECKV6M-NEXT:    blt .LBB2_7
200; CHECKV6M-NEXT:  @ %bb.2: @ %then
201; CHECKV6M-NEXT:    cmp r0, #0
202; CHECKV6M-NEXT:    blt .LBB2_8
203; CHECKV6M-NEXT:  .LBB2_3: @ %then
204; CHECKV6M-NEXT:    adds r0, r2, r1
205; CHECKV6M-NEXT:    pop {r4, pc}
206; CHECKV6M-NEXT:  .LBB2_4: @ %else
207; CHECKV6M-NEXT:    cmp r0, #0
208; CHECKV6M-NEXT:    bge .LBB2_6
209; CHECKV6M-NEXT:  @ %bb.5: @ %else
210; CHECKV6M-NEXT:    mov r2, r3
211; CHECKV6M-NEXT:  .LBB2_6: @ %else
212; CHECKV6M-NEXT:    mov r0, r2
213; CHECKV6M-NEXT:    pop {r4, pc}
214; CHECKV6M-NEXT:  .LBB2_7: @ %then
215; CHECKV6M-NEXT:    mov r1, r3
216; CHECKV6M-NEXT:    cmp r0, #0
217; CHECKV6M-NEXT:    bge .LBB2_3
218; CHECKV6M-NEXT:  .LBB2_8: @ %then
219; CHECKV6M-NEXT:    mov r2, r3
220; CHECKV6M-NEXT:    adds r0, r2, r1
221; CHECKV6M-NEXT:    pop {r4, pc}
222;
223; CHECKV7M-LABEL: icmp32_sge_0:
224; CHECKV7M:       @ %bb.0:
225; CHECKV7M-NEXT:    mov r12, r3
226; CHECKV7M-NEXT:    ldr r3, [sp]
227; CHECKV7M-NEXT:    lsls r3, r3, #31
228; CHECKV7M-NEXT:    beq .LBB2_2
229; CHECKV7M-NEXT:  @ %bb.1: @ %then
230; CHECKV7M-NEXT:    cmp.w r1, #-1
231; CHECKV7M-NEXT:    mov r1, r12
232; CHECKV7M-NEXT:    it gt
233; CHECKV7M-NEXT:    movgt r1, r2
234; CHECKV7M-NEXT:    cmp.w r0, #-1
235; CHECKV7M-NEXT:    it gt
236; CHECKV7M-NEXT:    movgt r12, r2
237; CHECKV7M-NEXT:    add.w r0, r12, r1
238; CHECKV7M-NEXT:    bx lr
239; CHECKV7M-NEXT:  .LBB2_2: @ %else
240; CHECKV7M-NEXT:    cmp.w r0, #-1
241; CHECKV7M-NEXT:    it gt
242; CHECKV7M-NEXT:    movgt r12, r2
243; CHECKV7M-NEXT:    mov r0, r12
244; CHECKV7M-NEXT:    bx lr
245;
246; CHECKV7A-LABEL: icmp32_sge_0:
247; CHECKV7A:       @ %bb.0:
248; CHECKV7A-NEXT:    mov r12, r3
249; CHECKV7A-NEXT:    ldr r3, [sp]
250; CHECKV7A-NEXT:    lsls r3, r3, #31
251; CHECKV7A-NEXT:    beq .LBB2_2
252; CHECKV7A-NEXT:  @ %bb.1: @ %then
253; CHECKV7A-NEXT:    cmp.w r1, #-1
254; CHECKV7A-NEXT:    mov r1, r12
255; CHECKV7A-NEXT:    it gt
256; CHECKV7A-NEXT:    movgt r1, r2
257; CHECKV7A-NEXT:    cmp.w r0, #-1
258; CHECKV7A-NEXT:    it gt
259; CHECKV7A-NEXT:    movgt r12, r2
260; CHECKV7A-NEXT:    add.w r0, r12, r1
261; CHECKV7A-NEXT:    bx lr
262; CHECKV7A-NEXT:  .LBB2_2: @ %else
263; CHECKV7A-NEXT:    cmp.w r0, #-1
264; CHECKV7A-NEXT:    it gt
265; CHECKV7A-NEXT:    movgt r12, r2
266; CHECKV7A-NEXT:    mov r0, r12
267; CHECKV7A-NEXT:    bx lr
268  br i1 %c, label %then, label %else
269then:
270  %c1 = icmp sge i32 %x, 0
271  %c2 = icmp sge i32 %y, 0
272  %s1 = select i1 %c1, i32 %a, i32 %b
273  %s2 = select i1 %c2, i32 %a, i32 %b
274  %r = add i32 %s1, %s2
275  ret i32 %r
276else:
277  %c3 = icmp sge i32 %x, 0
278  %s3 = select i1 %c3, i32 %a, i32 %b
279  ret i32 %s3
280}
281
282define i32 @icmp32_sgt_m1(i32 %x, i32 %y, i32 %a, i32 %b, i1 %c) {
283; CHECKV6M-LABEL: icmp32_sgt_m1:
284; CHECKV6M:       @ %bb.0:
285; CHECKV6M-NEXT:    .save {r4, lr}
286; CHECKV6M-NEXT:    push {r4, lr}
287; CHECKV6M-NEXT:    ldr r4, [sp, #8]
288; CHECKV6M-NEXT:    lsls r4, r4, #31
289; CHECKV6M-NEXT:    beq .LBB3_4
290; CHECKV6M-NEXT:  @ %bb.1: @ %then
291; CHECKV6M-NEXT:    cmp r1, #0
292; CHECKV6M-NEXT:    mov r1, r2
293; CHECKV6M-NEXT:    blt .LBB3_7
294; CHECKV6M-NEXT:  @ %bb.2: @ %then
295; CHECKV6M-NEXT:    cmp r0, #0
296; CHECKV6M-NEXT:    blt .LBB3_8
297; CHECKV6M-NEXT:  .LBB3_3: @ %then
298; CHECKV6M-NEXT:    adds r0, r2, r1
299; CHECKV6M-NEXT:    pop {r4, pc}
300; CHECKV6M-NEXT:  .LBB3_4: @ %else
301; CHECKV6M-NEXT:    cmp r1, #0
302; CHECKV6M-NEXT:    bge .LBB3_6
303; CHECKV6M-NEXT:  @ %bb.5: @ %else
304; CHECKV6M-NEXT:    mov r2, r3
305; CHECKV6M-NEXT:  .LBB3_6: @ %else
306; CHECKV6M-NEXT:    mov r0, r2
307; CHECKV6M-NEXT:    pop {r4, pc}
308; CHECKV6M-NEXT:  .LBB3_7: @ %then
309; CHECKV6M-NEXT:    mov r1, r3
310; CHECKV6M-NEXT:    cmp r0, #0
311; CHECKV6M-NEXT:    bge .LBB3_3
312; CHECKV6M-NEXT:  .LBB3_8: @ %then
313; CHECKV6M-NEXT:    mov r2, r3
314; CHECKV6M-NEXT:    adds r0, r2, r1
315; CHECKV6M-NEXT:    pop {r4, pc}
316;
317; CHECKV7M-LABEL: icmp32_sgt_m1:
318; CHECKV7M:       @ %bb.0:
319; CHECKV7M-NEXT:    mov r12, r3
320; CHECKV7M-NEXT:    ldr r3, [sp]
321; CHECKV7M-NEXT:    lsls r3, r3, #31
322; CHECKV7M-NEXT:    beq .LBB3_2
323; CHECKV7M-NEXT:  @ %bb.1: @ %then
324; CHECKV7M-NEXT:    cmp.w r1, #-1
325; CHECKV7M-NEXT:    mov r1, r12
326; CHECKV7M-NEXT:    it gt
327; CHECKV7M-NEXT:    movgt r1, r2
328; CHECKV7M-NEXT:    cmp.w r0, #-1
329; CHECKV7M-NEXT:    it gt
330; CHECKV7M-NEXT:    movgt r12, r2
331; CHECKV7M-NEXT:    add.w r0, r12, r1
332; CHECKV7M-NEXT:    bx lr
333; CHECKV7M-NEXT:  .LBB3_2: @ %else
334; CHECKV7M-NEXT:    cmp.w r1, #-1
335; CHECKV7M-NEXT:    it gt
336; CHECKV7M-NEXT:    movgt r12, r2
337; CHECKV7M-NEXT:    mov r0, r12
338; CHECKV7M-NEXT:    bx lr
339;
340; CHECKV7A-LABEL: icmp32_sgt_m1:
341; CHECKV7A:       @ %bb.0:
342; CHECKV7A-NEXT:    mov r12, r3
343; CHECKV7A-NEXT:    ldr r3, [sp]
344; CHECKV7A-NEXT:    lsls r3, r3, #31
345; CHECKV7A-NEXT:    beq .LBB3_2
346; CHECKV7A-NEXT:  @ %bb.1: @ %then
347; CHECKV7A-NEXT:    cmp.w r1, #-1
348; CHECKV7A-NEXT:    mov r1, r12
349; CHECKV7A-NEXT:    it gt
350; CHECKV7A-NEXT:    movgt r1, r2
351; CHECKV7A-NEXT:    cmp.w r0, #-1
352; CHECKV7A-NEXT:    it gt
353; CHECKV7A-NEXT:    movgt r12, r2
354; CHECKV7A-NEXT:    add.w r0, r12, r1
355; CHECKV7A-NEXT:    bx lr
356; CHECKV7A-NEXT:  .LBB3_2: @ %else
357; CHECKV7A-NEXT:    cmp.w r1, #-1
358; CHECKV7A-NEXT:    it gt
359; CHECKV7A-NEXT:    movgt r12, r2
360; CHECKV7A-NEXT:    mov r0, r12
361; CHECKV7A-NEXT:    bx lr
362  br i1 %c, label %then, label %else
363then:
364  %c1 = icmp sgt i32 %x, -1
365  %c2 = icmp sgt i32 %y, -1
366  %s1 = select i1 %c1, i32 %a, i32 %b
367  %s2 = select i1 %c2, i32 %a, i32 %b
368  %r = add i32 %s1, %s2
369  ret i32 %r
370else:
371  %c3 = icmp sgt i32 %y, -1
372  %s3 = select i1 %c3, i32 %a, i32 %b
373  ret i32 %s3
374}
375
376define i32 @icmp64_sle_m1(i64 %x, i64 %y, i32 %a, i32 %b, i1 %c) {
377; CHECKV6M-LABEL: icmp64_sle_m1:
378; CHECKV6M:       @ %bb.0:
379; CHECKV6M-NEXT:    ldr r0, [sp, #8]
380; CHECKV6M-NEXT:    lsls r0, r0, #31
381; CHECKV6M-NEXT:    ldr r2, [sp, #4]
382; CHECKV6M-NEXT:    ldr r0, [sp]
383; CHECKV6M-NEXT:    beq .LBB4_4
384; CHECKV6M-NEXT:  @ %bb.1: @ %then
385; CHECKV6M-NEXT:    cmp r3, #0
386; CHECKV6M-NEXT:    mov r3, r0
387; CHECKV6M-NEXT:    bpl .LBB4_7
388; CHECKV6M-NEXT:  @ %bb.2: @ %then
389; CHECKV6M-NEXT:    cmp r1, #0
390; CHECKV6M-NEXT:    bpl .LBB4_8
391; CHECKV6M-NEXT:  .LBB4_3: @ %then
392; CHECKV6M-NEXT:    adds r0, r0, r3
393; CHECKV6M-NEXT:    bx lr
394; CHECKV6M-NEXT:  .LBB4_4: @ %else
395; CHECKV6M-NEXT:    cmp r3, #0
396; CHECKV6M-NEXT:    bmi .LBB4_6
397; CHECKV6M-NEXT:  @ %bb.5: @ %else
398; CHECKV6M-NEXT:    mov r0, r2
399; CHECKV6M-NEXT:  .LBB4_6: @ %else
400; CHECKV6M-NEXT:    bx lr
401; CHECKV6M-NEXT:  .LBB4_7: @ %then
402; CHECKV6M-NEXT:    mov r3, r2
403; CHECKV6M-NEXT:    cmp r1, #0
404; CHECKV6M-NEXT:    bmi .LBB4_3
405; CHECKV6M-NEXT:  .LBB4_8: @ %then
406; CHECKV6M-NEXT:    mov r0, r2
407; CHECKV6M-NEXT:    adds r0, r0, r3
408; CHECKV6M-NEXT:    bx lr
409;
410; CHECKV7M-LABEL: icmp64_sle_m1:
411; CHECKV7M:       @ %bb.0:
412; CHECKV7M-NEXT:    ldr r0, [sp, #8]
413; CHECKV7M-NEXT:    lsls r0, r0, #31
414; CHECKV7M-NEXT:    ldrd r2, r0, [sp]
415; CHECKV7M-NEXT:    beq .LBB4_2
416; CHECKV7M-NEXT:  @ %bb.1: @ %then
417; CHECKV7M-NEXT:    cmp r3, #0
418; CHECKV7M-NEXT:    mov r3, r0
419; CHECKV7M-NEXT:    it mi
420; CHECKV7M-NEXT:    movmi r3, r2
421; CHECKV7M-NEXT:    cmp r1, #0
422; CHECKV7M-NEXT:    it mi
423; CHECKV7M-NEXT:    movmi r0, r2
424; CHECKV7M-NEXT:    add r0, r3
425; CHECKV7M-NEXT:    bx lr
426; CHECKV7M-NEXT:  .LBB4_2: @ %else
427; CHECKV7M-NEXT:    cmp r3, #0
428; CHECKV7M-NEXT:    it mi
429; CHECKV7M-NEXT:    movmi r0, r2
430; CHECKV7M-NEXT:    bx lr
431;
432; CHECKV7A-LABEL: icmp64_sle_m1:
433; CHECKV7A:       @ %bb.0:
434; CHECKV7A-NEXT:    ldr r2, [sp, #8]
435; CHECKV7A-NEXT:    ldrd r12, r0, [sp]
436; CHECKV7A-NEXT:    lsls r2, r2, #31
437; CHECKV7A-NEXT:    beq .LBB4_2
438; CHECKV7A-NEXT:  @ %bb.1: @ %then
439; CHECKV7A-NEXT:    cmp r3, #0
440; CHECKV7A-NEXT:    mov r2, r0
441; CHECKV7A-NEXT:    it mi
442; CHECKV7A-NEXT:    movmi r2, r12
443; CHECKV7A-NEXT:    cmp r1, #0
444; CHECKV7A-NEXT:    it mi
445; CHECKV7A-NEXT:    movmi r0, r12
446; CHECKV7A-NEXT:    add r0, r2
447; CHECKV7A-NEXT:    bx lr
448; CHECKV7A-NEXT:  .LBB4_2: @ %else
449; CHECKV7A-NEXT:    cmp r3, #0
450; CHECKV7A-NEXT:    it mi
451; CHECKV7A-NEXT:    movmi r0, r12
452; CHECKV7A-NEXT:    bx lr
453  br i1 %c, label %then, label %else
454then:
455  %c1 = icmp sle i64 %x, -1
456  %c2 = icmp sle i64 %y, -1
457  %s1 = select i1 %c1, i32 %a, i32 %b
458  %s2 = select i1 %c2, i32 %a, i32 %b
459  %r = add i32 %s1, %s2
460  ret i32 %r
461else:
462  %c3 = icmp sle i64 %y, -1
463  %s3 = select i1 %c3, i32 %a, i32 %b
464  ret i32 %s3
465}
466
467define i32 @icmp64_ule_m1(i64 %x, i64 %y, i32 %a, i32 %b, i1 %c) {
468; CHECKV6M-LABEL: icmp64_ule_m1:
469; CHECKV6M:       @ %bb.0:
470; CHECKV6M-NEXT:    .save {r4, r5, r6, r7, lr}
471; CHECKV6M-NEXT:    push {r4, r5, r6, r7, lr}
472; CHECKV6M-NEXT:    mov r4, r0
473; CHECKV6M-NEXT:    ldr r0, [sp, #28]
474; CHECKV6M-NEXT:    lsls r0, r0, #31
475; CHECKV6M-NEXT:    ldr r6, .LCPI5_0
476; CHECKV6M-NEXT:    ldr r5, [sp, #24]
477; CHECKV6M-NEXT:    ldr r0, [sp, #20]
478; CHECKV6M-NEXT:    beq .LBB5_6
479; CHECKV6M-NEXT:  @ %bb.1: @ %then
480; CHECKV6M-NEXT:    movs r7, #0
481; CHECKV6M-NEXT:    subs r2, r2, r6
482; CHECKV6M-NEXT:    sbcs r3, r7
483; CHECKV6M-NEXT:    mov r2, r0
484; CHECKV6M-NEXT:    blo .LBB5_3
485; CHECKV6M-NEXT:  @ %bb.2: @ %then
486; CHECKV6M-NEXT:    mov r2, r5
487; CHECKV6M-NEXT:  .LBB5_3: @ %then
488; CHECKV6M-NEXT:    subs r3, r4, r6
489; CHECKV6M-NEXT:    sbcs r1, r7
490; CHECKV6M-NEXT:    blo .LBB5_5
491; CHECKV6M-NEXT:  @ %bb.4: @ %then
492; CHECKV6M-NEXT:    mov r0, r5
493; CHECKV6M-NEXT:  .LBB5_5: @ %then
494; CHECKV6M-NEXT:    adds r0, r0, r2
495; CHECKV6M-NEXT:    pop {r4, r5, r6, r7, pc}
496; CHECKV6M-NEXT:  .LBB5_6: @ %else
497; CHECKV6M-NEXT:    movs r1, #0
498; CHECKV6M-NEXT:    subs r2, r2, r6
499; CHECKV6M-NEXT:    sbcs r3, r1
500; CHECKV6M-NEXT:    blo .LBB5_8
501; CHECKV6M-NEXT:  @ %bb.7: @ %else
502; CHECKV6M-NEXT:    mov r0, r5
503; CHECKV6M-NEXT:  .LBB5_8: @ %else
504; CHECKV6M-NEXT:    pop {r4, r5, r6, r7, pc}
505; CHECKV6M-NEXT:    .p2align 2
506; CHECKV6M-NEXT:  @ %bb.9:
507; CHECKV6M-NEXT:  .LCPI5_0:
508; CHECKV6M-NEXT:    .long 131073 @ 0x20001
509;
510; CHECKV7M-LABEL: icmp64_ule_m1:
511; CHECKV7M:       @ %bb.0:
512; CHECKV7M-NEXT:    .save {r4, lr}
513; CHECKV7M-NEXT:    push {r4, lr}
514; CHECKV7M-NEXT:    mov r12, r0
515; CHECKV7M-NEXT:    ldr r0, [sp, #16]
516; CHECKV7M-NEXT:    movs r4, #1
517; CHECKV7M-NEXT:    movt r4, #2
518; CHECKV7M-NEXT:    lsls r0, r0, #31
519; CHECKV7M-NEXT:    ldrd lr, r0, [sp, #8]
520; CHECKV7M-NEXT:    beq .LBB5_2
521; CHECKV7M-NEXT:  @ %bb.1: @ %then
522; CHECKV7M-NEXT:    subs r2, r2, r4
523; CHECKV7M-NEXT:    sbcs r2, r3, #0
524; CHECKV7M-NEXT:    mov r2, r0
525; CHECKV7M-NEXT:    it lo
526; CHECKV7M-NEXT:    movlo r2, lr
527; CHECKV7M-NEXT:    subs.w r3, r12, r4
528; CHECKV7M-NEXT:    sbcs r1, r1, #0
529; CHECKV7M-NEXT:    it lo
530; CHECKV7M-NEXT:    movlo r0, lr
531; CHECKV7M-NEXT:    add r0, r2
532; CHECKV7M-NEXT:    pop {r4, pc}
533; CHECKV7M-NEXT:  .LBB5_2: @ %else
534; CHECKV7M-NEXT:    subs r1, r2, r4
535; CHECKV7M-NEXT:    sbcs r1, r3, #0
536; CHECKV7M-NEXT:    it lo
537; CHECKV7M-NEXT:    movlo r0, lr
538; CHECKV7M-NEXT:    pop {r4, pc}
539;
540; CHECKV7A-LABEL: icmp64_ule_m1:
541; CHECKV7A:       @ %bb.0:
542; CHECKV7A-NEXT:    .save {r4, lr}
543; CHECKV7A-NEXT:    push {r4, lr}
544; CHECKV7A-NEXT:    ldr r4, [sp, #16]
545; CHECKV7A-NEXT:    mov r12, r0
546; CHECKV7A-NEXT:    ldrd lr, r0, [sp, #8]
547; CHECKV7A-NEXT:    lsls r4, r4, #31
548; CHECKV7A-NEXT:    movw r4, #1
549; CHECKV7A-NEXT:    movt r4, #2
550; CHECKV7A-NEXT:    beq .LBB5_2
551; CHECKV7A-NEXT:  @ %bb.1: @ %then
552; CHECKV7A-NEXT:    subs r2, r2, r4
553; CHECKV7A-NEXT:    sbcs r2, r3, #0
554; CHECKV7A-NEXT:    mov r2, r0
555; CHECKV7A-NEXT:    it lo
556; CHECKV7A-NEXT:    movlo r2, lr
557; CHECKV7A-NEXT:    subs.w r3, r12, r4
558; CHECKV7A-NEXT:    sbcs r1, r1, #0
559; CHECKV7A-NEXT:    it lo
560; CHECKV7A-NEXT:    movlo r0, lr
561; CHECKV7A-NEXT:    add r0, r2
562; CHECKV7A-NEXT:    pop {r4, pc}
563; CHECKV7A-NEXT:  .LBB5_2: @ %else
564; CHECKV7A-NEXT:    subs r1, r2, r4
565; CHECKV7A-NEXT:    sbcs r1, r3, #0
566; CHECKV7A-NEXT:    it lo
567; CHECKV7A-NEXT:    movlo r0, lr
568; CHECKV7A-NEXT:    pop {r4, pc}
569  br i1 %c, label %then, label %else
570then:
571  %c1 = icmp ult i64 %x, 131073
572  %c2 = icmp ult i64 %y, 131073
573  %s1 = select i1 %c1, i32 %a, i32 %b
574  %s2 = select i1 %c2, i32 %a, i32 %b
575  %r = add i32 %s1, %s2
576  ret i32 %r
577else:
578  %c3 = icmp ult i64 %y, 131073
579  %s3 = select i1 %c3, i32 %a, i32 %b
580  ret i32 %s3
581}
582
583define i32 @icmp64_uge_m2(i64 %x, i64 %y, i32 %a, i32 %b, i1 %c) {
584; CHECKV6M-LABEL: icmp64_uge_m2:
585; CHECKV6M:       @ %bb.0:
586; CHECKV6M-NEXT:    .save {r4, r5, r6, r7, lr}
587; CHECKV6M-NEXT:    push {r4, r5, r6, r7, lr}
588; CHECKV6M-NEXT:    mov r4, r0
589; CHECKV6M-NEXT:    movs r0, #1
590; CHECKV6M-NEXT:    lsls r6, r0, #17
591; CHECKV6M-NEXT:    ldr r0, [sp, #28]
592; CHECKV6M-NEXT:    lsls r0, r0, #31
593; CHECKV6M-NEXT:    ldr r5, [sp, #24]
594; CHECKV6M-NEXT:    ldr r0, [sp, #20]
595; CHECKV6M-NEXT:    beq .LBB6_6
596; CHECKV6M-NEXT:  @ %bb.1: @ %then
597; CHECKV6M-NEXT:    movs r7, #0
598; CHECKV6M-NEXT:    subs r2, r2, r6
599; CHECKV6M-NEXT:    sbcs r3, r7
600; CHECKV6M-NEXT:    mov r2, r0
601; CHECKV6M-NEXT:    bhs .LBB6_3
602; CHECKV6M-NEXT:  @ %bb.2: @ %then
603; CHECKV6M-NEXT:    mov r2, r5
604; CHECKV6M-NEXT:  .LBB6_3: @ %then
605; CHECKV6M-NEXT:    subs r3, r4, r6
606; CHECKV6M-NEXT:    sbcs r1, r7
607; CHECKV6M-NEXT:    bhs .LBB6_5
608; CHECKV6M-NEXT:  @ %bb.4: @ %then
609; CHECKV6M-NEXT:    mov r0, r5
610; CHECKV6M-NEXT:  .LBB6_5: @ %then
611; CHECKV6M-NEXT:    adds r0, r0, r2
612; CHECKV6M-NEXT:    pop {r4, r5, r6, r7, pc}
613; CHECKV6M-NEXT:  .LBB6_6: @ %else
614; CHECKV6M-NEXT:    movs r1, #0
615; CHECKV6M-NEXT:    subs r2, r2, r6
616; CHECKV6M-NEXT:    sbcs r3, r1
617; CHECKV6M-NEXT:    bhs .LBB6_8
618; CHECKV6M-NEXT:  @ %bb.7: @ %else
619; CHECKV6M-NEXT:    mov r0, r5
620; CHECKV6M-NEXT:  .LBB6_8: @ %else
621; CHECKV6M-NEXT:    pop {r4, r5, r6, r7, pc}
622;
623; CHECKV7M-LABEL: icmp64_uge_m2:
624; CHECKV7M:       @ %bb.0:
625; CHECKV7M-NEXT:    .save {r7, lr}
626; CHECKV7M-NEXT:    push {r7, lr}
627; CHECKV7M-NEXT:    mov r12, r0
628; CHECKV7M-NEXT:    ldr r0, [sp, #16]
629; CHECKV7M-NEXT:    lsls r0, r0, #31
630; CHECKV7M-NEXT:    ldrd lr, r0, [sp, #8]
631; CHECKV7M-NEXT:    beq .LBB6_2
632; CHECKV7M-NEXT:  @ %bb.1: @ %then
633; CHECKV7M-NEXT:    orrs.w r2, r3, r2, lsr #17
634; CHECKV7M-NEXT:    mov r2, r0
635; CHECKV7M-NEXT:    it ne
636; CHECKV7M-NEXT:    movne r2, lr
637; CHECKV7M-NEXT:    orrs.w r1, r1, r12, lsr #17
638; CHECKV7M-NEXT:    it ne
639; CHECKV7M-NEXT:    movne r0, lr
640; CHECKV7M-NEXT:    add r0, r2
641; CHECKV7M-NEXT:    pop {r7, pc}
642; CHECKV7M-NEXT:  .LBB6_2: @ %else
643; CHECKV7M-NEXT:    orrs.w r1, r3, r2, lsr #17
644; CHECKV7M-NEXT:    it ne
645; CHECKV7M-NEXT:    movne r0, lr
646; CHECKV7M-NEXT:    pop {r7, pc}
647;
648; CHECKV7A-LABEL: icmp64_uge_m2:
649; CHECKV7A:       @ %bb.0:
650; CHECKV7A-NEXT:    .save {r4, lr}
651; CHECKV7A-NEXT:    push {r4, lr}
652; CHECKV7A-NEXT:    ldr r4, [sp, #16]
653; CHECKV7A-NEXT:    mov r12, r0
654; CHECKV7A-NEXT:    ldrd lr, r0, [sp, #8]
655; CHECKV7A-NEXT:    lsls r4, r4, #31
656; CHECKV7A-NEXT:    beq .LBB6_2
657; CHECKV7A-NEXT:  @ %bb.1: @ %then
658; CHECKV7A-NEXT:    orrs.w r2, r3, r2, lsr #17
659; CHECKV7A-NEXT:    mov r2, r0
660; CHECKV7A-NEXT:    it ne
661; CHECKV7A-NEXT:    movne r2, lr
662; CHECKV7A-NEXT:    orrs.w r1, r1, r12, lsr #17
663; CHECKV7A-NEXT:    it ne
664; CHECKV7A-NEXT:    movne r0, lr
665; CHECKV7A-NEXT:    add r0, r2
666; CHECKV7A-NEXT:    pop {r4, pc}
667; CHECKV7A-NEXT:  .LBB6_2: @ %else
668; CHECKV7A-NEXT:    orrs.w r1, r3, r2, lsr #17
669; CHECKV7A-NEXT:    it ne
670; CHECKV7A-NEXT:    movne r0, lr
671; CHECKV7A-NEXT:    pop {r4, pc}
672  br i1 %c, label %then, label %else
673then:
674  %c1 = icmp uge i64 %x, 131072
675  %c2 = icmp uge i64 %y, 131072
676  %s1 = select i1 %c1, i32 %a, i32 %b
677  %s2 = select i1 %c2, i32 %a, i32 %b
678  %r = add i32 %s1, %s2
679  ret i32 %r
680else:
681  %c3 = icmp uge i64 %y, 131072
682  %s3 = select i1 %c3, i32 %a, i32 %b
683  ret i32 %s3
684}
685
686define i32 @icmp64_ugt_m1(i64 %x, i64 %y, i32 %a, i32 %b, i1 %c) {
687; CHECKV6M-LABEL: icmp64_ugt_m1:
688; CHECKV6M:       @ %bb.0:
689; CHECKV6M-NEXT:    .save {r4, r5, r6, r7, lr}
690; CHECKV6M-NEXT:    push {r4, r5, r6, r7, lr}
691; CHECKV6M-NEXT:    mov r4, r0
692; CHECKV6M-NEXT:    ldr r0, [sp, #28]
693; CHECKV6M-NEXT:    lsls r0, r0, #31
694; CHECKV6M-NEXT:    ldr r6, .LCPI7_0
695; CHECKV6M-NEXT:    ldr r5, [sp, #24]
696; CHECKV6M-NEXT:    ldr r0, [sp, #20]
697; CHECKV6M-NEXT:    beq .LBB7_6
698; CHECKV6M-NEXT:  @ %bb.1: @ %then
699; CHECKV6M-NEXT:    movs r7, #0
700; CHECKV6M-NEXT:    subs r2, r6, r2
701; CHECKV6M-NEXT:    mov r2, r7
702; CHECKV6M-NEXT:    sbcs r2, r3
703; CHECKV6M-NEXT:    mov r2, r0
704; CHECKV6M-NEXT:    blo .LBB7_3
705; CHECKV6M-NEXT:  @ %bb.2: @ %then
706; CHECKV6M-NEXT:    mov r2, r5
707; CHECKV6M-NEXT:  .LBB7_3: @ %then
708; CHECKV6M-NEXT:    subs r3, r6, r4
709; CHECKV6M-NEXT:    sbcs r7, r1
710; CHECKV6M-NEXT:    blo .LBB7_5
711; CHECKV6M-NEXT:  @ %bb.4: @ %then
712; CHECKV6M-NEXT:    mov r0, r5
713; CHECKV6M-NEXT:  .LBB7_5: @ %then
714; CHECKV6M-NEXT:    adds r0, r0, r2
715; CHECKV6M-NEXT:    pop {r4, r5, r6, r7, pc}
716; CHECKV6M-NEXT:  .LBB7_6: @ %else
717; CHECKV6M-NEXT:    movs r1, #0
718; CHECKV6M-NEXT:    subs r2, r6, r2
719; CHECKV6M-NEXT:    sbcs r1, r3
720; CHECKV6M-NEXT:    blo .LBB7_8
721; CHECKV6M-NEXT:  @ %bb.7: @ %else
722; CHECKV6M-NEXT:    mov r0, r5
723; CHECKV6M-NEXT:  .LBB7_8: @ %else
724; CHECKV6M-NEXT:    pop {r4, r5, r6, r7, pc}
725; CHECKV6M-NEXT:    .p2align 2
726; CHECKV6M-NEXT:  @ %bb.9:
727; CHECKV6M-NEXT:  .LCPI7_0:
728; CHECKV6M-NEXT:    .long 131073 @ 0x20001
729;
730; CHECKV7M-LABEL: icmp64_ugt_m1:
731; CHECKV7M:       @ %bb.0:
732; CHECKV7M-NEXT:    .save {r4, r5, r7, lr}
733; CHECKV7M-NEXT:    push {r4, r5, r7, lr}
734; CHECKV7M-NEXT:    mov r12, r0
735; CHECKV7M-NEXT:    ldr r0, [sp, #24]
736; CHECKV7M-NEXT:    movs r4, #1
737; CHECKV7M-NEXT:    movt r4, #2
738; CHECKV7M-NEXT:    lsls r0, r0, #31
739; CHECKV7M-NEXT:    ldrd lr, r0, [sp, #16]
740; CHECKV7M-NEXT:    beq .LBB7_2
741; CHECKV7M-NEXT:  @ %bb.1: @ %then
742; CHECKV7M-NEXT:    subs r2, r4, r2
743; CHECKV7M-NEXT:    mov.w r5, #0
744; CHECKV7M-NEXT:    sbcs.w r2, r5, r3
745; CHECKV7M-NEXT:    mov r2, r0
746; CHECKV7M-NEXT:    it lo
747; CHECKV7M-NEXT:    movlo r2, lr
748; CHECKV7M-NEXT:    subs.w r3, r4, r12
749; CHECKV7M-NEXT:    sbcs.w r1, r5, r1
750; CHECKV7M-NEXT:    it lo
751; CHECKV7M-NEXT:    movlo r0, lr
752; CHECKV7M-NEXT:    add r0, r2
753; CHECKV7M-NEXT:    pop {r4, r5, r7, pc}
754; CHECKV7M-NEXT:  .LBB7_2: @ %else
755; CHECKV7M-NEXT:    movs r1, #0
756; CHECKV7M-NEXT:    subs r2, r4, r2
757; CHECKV7M-NEXT:    sbcs r1, r3
758; CHECKV7M-NEXT:    it lo
759; CHECKV7M-NEXT:    movlo r0, lr
760; CHECKV7M-NEXT:    pop {r4, r5, r7, pc}
761;
762; CHECKV7A-LABEL: icmp64_ugt_m1:
763; CHECKV7A:       @ %bb.0:
764; CHECKV7A-NEXT:    .save {r4, r5, r7, lr}
765; CHECKV7A-NEXT:    push {r4, r5, r7, lr}
766; CHECKV7A-NEXT:    ldr r4, [sp, #24]
767; CHECKV7A-NEXT:    mov r12, r0
768; CHECKV7A-NEXT:    ldrd lr, r0, [sp, #16]
769; CHECKV7A-NEXT:    lsls r4, r4, #31
770; CHECKV7A-NEXT:    movw r4, #1
771; CHECKV7A-NEXT:    movt r4, #2
772; CHECKV7A-NEXT:    beq .LBB7_2
773; CHECKV7A-NEXT:  @ %bb.1: @ %then
774; CHECKV7A-NEXT:    subs r2, r4, r2
775; CHECKV7A-NEXT:    mov.w r5, #0
776; CHECKV7A-NEXT:    sbcs.w r2, r5, r3
777; CHECKV7A-NEXT:    mov r2, r0
778; CHECKV7A-NEXT:    it lo
779; CHECKV7A-NEXT:    movlo r2, lr
780; CHECKV7A-NEXT:    subs.w r3, r4, r12
781; CHECKV7A-NEXT:    sbcs.w r1, r5, r1
782; CHECKV7A-NEXT:    it lo
783; CHECKV7A-NEXT:    movlo r0, lr
784; CHECKV7A-NEXT:    add r0, r2
785; CHECKV7A-NEXT:    pop {r4, r5, r7, pc}
786; CHECKV7A-NEXT:  .LBB7_2: @ %else
787; CHECKV7A-NEXT:    movs r1, #0
788; CHECKV7A-NEXT:    subs r2, r4, r2
789; CHECKV7A-NEXT:    sbcs r1, r3
790; CHECKV7A-NEXT:    it lo
791; CHECKV7A-NEXT:    movlo r0, lr
792; CHECKV7A-NEXT:    pop {r4, r5, r7, pc}
793  br i1 %c, label %then, label %else
794then:
795  %c1 = icmp ugt i64 %x, 131073
796  %c2 = icmp ugt i64 %y, 131073
797  %s1 = select i1 %c1, i32 %a, i32 %b
798  %s2 = select i1 %c2, i32 %a, i32 %b
799  %r = add i32 %s1, %s2
800  ret i32 %r
801else:
802  %c3 = icmp ugt i64 %y, 131073
803  %s3 = select i1 %c3, i32 %a, i32 %b
804  ret i32 %s3
805}
806