xref: /llvm-project/llvm/test/CodeGen/ARM/combine-bswap.ll (revision d069ac035add3095c771f49540223f98e5ba10b9)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=thumbv7m-none-eabi -mattr=v7 | FileCheck %s --check-prefixes=CHECK
3
4declare i32 @llvm.bswap.i32(i32) readnone
5declare i64 @llvm.bswap.i64(i64) readnone
6declare i32 @llvm.bitreverse.i32(i32) readnone
7
8define i32 @bs_and_lhs_bs32(i32 %a, i32 %b) #0 {
9; CHECK-LABEL: bs_and_lhs_bs32:
10; CHECK:       @ %bb.0:
11; CHECK-NEXT:    rev r1, r1
12; CHECK-NEXT:    ands r0, r1
13; CHECK-NEXT:    bx lr
14  %1 = tail call i32 @llvm.bswap.i32(i32 %a)
15  %2 = and i32 %1, %b
16  %3 = tail call i32 @llvm.bswap.i32(i32 %2)
17  ret i32 %3
18}
19
20define i64 @bs_or_rhs_bs64(i64 %a, i64 %b) #0 {
21; CHECK-LABEL: bs_or_rhs_bs64:
22; CHECK:       @ %bb.0:
23; CHECK-NEXT:    rev r1, r1
24; CHECK-NEXT:    rev r0, r0
25; CHECK-NEXT:    orrs r2, r1
26; CHECK-NEXT:    orr.w r1, r0, r3
27; CHECK-NEXT:    mov r0, r2
28; CHECK-NEXT:    bx lr
29  %1 = tail call i64 @llvm.bswap.i64(i64 %b)
30  %2 = or i64 %a, %1
31  %3 = tail call i64 @llvm.bswap.i64(i64 %2)
32  ret i64 %3
33}
34
35define i32 @bs_and_all_operand_multiuse(i32 %a, i32 %b) #0 {
36; CHECK-LABEL: bs_and_all_operand_multiuse:
37; CHECK:       @ %bb.0:
38; CHECK-NEXT:    and.w r2, r0, r1
39; CHECK-NEXT:    rev r0, r0
40; CHECK-NEXT:    rev r1, r1
41; CHECK-NEXT:    muls r0, r2, r0
42; CHECK-NEXT:    muls r0, r1, r0
43; CHECK-NEXT:    bx lr
44  %1 = tail call i32 @llvm.bswap.i32(i32 %a)
45  %2 = tail call i32 @llvm.bswap.i32(i32 %b)
46  %3 = and i32 %1, %2
47  %4 = tail call i32 @llvm.bswap.i32(i32 %3)
48  %5 = mul i32 %1, %4 ;increase use of left bswap
49  %6 = mul i32 %2, %5 ;increase use of right bswap
50
51  ret i32 %6
52}
53
54; negative test
55define i32 @bs_and_rhs_bs32_multiuse1(i32 %a, i32 %b) #0 {
56; CHECK-LABEL: bs_and_rhs_bs32_multiuse1:
57; CHECK:       @ %bb.0:
58; CHECK-NEXT:    rev r1, r1
59; CHECK-NEXT:    ands r0, r1
60; CHECK-NEXT:    rev r1, r0
61; CHECK-NEXT:    muls r0, r1, r0
62; CHECK-NEXT:    bx lr
63  %1 = tail call i32 @llvm.bswap.i32(i32 %b)
64  %2 = and i32 %1, %a
65  %3 = tail call i32 @llvm.bswap.i32(i32 %2)
66  %4 = mul i32 %2, %3 ;increase use of logical op
67  ret i32 %4
68}
69
70; negative test
71define i32 @bs_xor_rhs_brev32(i32 %a, i32 %b) #0 {
72; CHECK-LABEL: bs_xor_rhs_brev32:
73; CHECK:       @ %bb.0:
74; CHECK-NEXT:    rbit r1, r1
75; CHECK-NEXT:    eors r0, r1
76; CHECK-NEXT:    rev r0, r0
77; CHECK-NEXT:    bx lr
78  %1 = tail call i32 @llvm.bitreverse.i32(i32 %b)
79  %2 = xor i32 %a, %1
80  %3 = tail call i32 @llvm.bswap.i32(i32 %2)
81  ret i32 %3
82}
83
84