xref: /llvm-project/llvm/test/CodeGen/ARM/cmse-clear-float-hard.ll (revision 2d56de9e7e4a3accde42b4d7d329acd007989df8) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc %s -o - -mtriple=thumbv8m.main -mattr=+fp-armv8d16sp,+dsp -float-abi=hard | \
3; RUN:   FileCheck %s --check-prefix=CHECK-8M --check-prefix=CHECK-8M-LE
4; RUN: llc %s -o - -mtriple=thumbebv8m.main -mattr=+fp-armv8d16sp,+dsp -float-abi=hard | \
5; RUN:   FileCheck %s --check-prefix=CHECK-8M --check-prefix=CHECK-8M-BE
6; RUN: llc %s -o - -mtriple=thumbv8.1m.main -mattr=+fp-armv8d16sp,+dsp -float-abi=hard | \
7; RUN:   FileCheck %s --check-prefix=CHECK-81M --check-prefix=CHECK-NO-MVE --check-prefix=CHECK-81M-LE
8; RUN: llc %s -o - -mtriple=thumbebv8.1m.main -mattr=+fp-armv8d16sp,+dsp -float-abi=hard | \
9; RUN:   FileCheck %s --check-prefix=CHECK-81M --check-prefix=CHECK-NO-MVE --check-prefix=CHECK-81M-BE
10; RUN: llc %s -o - -mtriple=thumbv8.1m.main -mattr=+mve.fp -float-abi=hard | \
11; RUN:   FileCheck %s --check-prefix=CHECK-81M --check-prefix=CHECK-MVE --check-prefix=CHECK-81M-LE
12; RUN: llc %s -o - -mtriple=thumbebv8.1m.main -mattr=+mve.fp -float-abi=hard | \
13; RUN:   FileCheck %s --check-prefix=CHECK-81M --check-prefix=CHECK-MVE --check-prefix=CHECK-81M-BE
14
15define float @f1(ptr nocapture %fptr) #0 {
16; CHECK-8M-LABEL: f1:
17; CHECK-8M:       @ %bb.0: @ %entry
18; CHECK-8M-NEXT:    push {r7, lr}
19; CHECK-8M-NEXT:    vmov.f32 s0, #1.000000e+01
20; CHECK-8M-NEXT:    blx r0
21; CHECK-8M-NEXT:    pop.w {r7, lr}
22; CHECK-8M-NEXT:    mrs r12, control
23; CHECK-8M-NEXT:    tst.w r12, #8
24; CHECK-8M-NEXT:    beq .LBB0_2
25; CHECK-8M-NEXT:  @ %bb.1: @ %entry
26; CHECK-8M-NEXT:    vmrs r12, fpscr
27; CHECK-8M-NEXT:    vmov s1, lr
28; CHECK-8M-NEXT:    vmov d1, lr, lr
29; CHECK-8M-NEXT:    vmov d2, lr, lr
30; CHECK-8M-NEXT:    vmov d3, lr, lr
31; CHECK-8M-NEXT:    vmov d4, lr, lr
32; CHECK-8M-NEXT:    vmov d5, lr, lr
33; CHECK-8M-NEXT:    vmov d6, lr, lr
34; CHECK-8M-NEXT:    vmov d7, lr, lr
35; CHECK-8M-NEXT:    bic r12, r12, #159
36; CHECK-8M-NEXT:    bic r12, r12, #4026531840
37; CHECK-8M-NEXT:    vmsr fpscr, r12
38; CHECK-8M-NEXT:  .LBB0_2: @ %entry
39; CHECK-8M-NEXT:    mov r0, lr
40; CHECK-8M-NEXT:    mov r1, lr
41; CHECK-8M-NEXT:    mov r2, lr
42; CHECK-8M-NEXT:    mov r3, lr
43; CHECK-8M-NEXT:    mov r12, lr
44; CHECK-8M-NEXT:    msr apsr_nzcvqg, lr
45; CHECK-8M-NEXT:    bxns lr
46;
47; CHECK-81M-LABEL: f1:
48; CHECK-81M:       @ %bb.0: @ %entry
49; CHECK-81M-NEXT:    vstr fpcxtns, [sp, #-4]!
50; CHECK-81M-NEXT:    push {r7, lr}
51; CHECK-81M-NEXT:    sub sp, #4
52; CHECK-81M-NEXT:    vmov.f32 s0, #1.000000e+01
53; CHECK-81M-NEXT:    blx r0
54; CHECK-81M-NEXT:    add sp, #4
55; CHECK-81M-NEXT:    pop.w {r7, lr}
56; CHECK-81M-NEXT:    vscclrm {s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, vpr}
57; CHECK-81M-NEXT:    vldr fpcxtns, [sp], #4
58; CHECK-81M-NEXT:    clrm {r0, r1, r2, r3, r12, apsr}
59; CHECK-81M-NEXT:    bxns lr
60entry:
61  %call = call float %fptr(float 10.0) #1
62  ret float %call
63}
64
65attributes #0 = { "cmse_nonsecure_entry" nounwind }
66attributes #1 = { nounwind }
67
68define double @d1(ptr nocapture %fptr) #0 {
69; CHECK-8M-LE-LABEL: d1:
70; CHECK-8M-LE:       @ %bb.0: @ %entry
71; CHECK-8M-LE-NEXT:    push {r7, lr}
72; CHECK-8M-LE-NEXT:    vldr d0, .LCPI1_0
73; CHECK-8M-LE-NEXT:    blx r0
74; CHECK-8M-LE-NEXT:    pop.w {r7, lr}
75; CHECK-8M-LE-NEXT:    mrs r12, control
76; CHECK-8M-LE-NEXT:    tst.w r12, #8
77; CHECK-8M-LE-NEXT:    beq .LBB1_2
78; CHECK-8M-LE-NEXT:  @ %bb.1: @ %entry
79; CHECK-8M-LE-NEXT:    vmrs r12, fpscr
80; CHECK-8M-LE-NEXT:    vmov d1, lr, lr
81; CHECK-8M-LE-NEXT:    vmov d2, lr, lr
82; CHECK-8M-LE-NEXT:    vmov d3, lr, lr
83; CHECK-8M-LE-NEXT:    vmov d4, lr, lr
84; CHECK-8M-LE-NEXT:    vmov d5, lr, lr
85; CHECK-8M-LE-NEXT:    vmov d6, lr, lr
86; CHECK-8M-LE-NEXT:    vmov d7, lr, lr
87; CHECK-8M-LE-NEXT:    bic r12, r12, #159
88; CHECK-8M-LE-NEXT:    bic r12, r12, #4026531840
89; CHECK-8M-LE-NEXT:    vmsr fpscr, r12
90; CHECK-8M-LE-NEXT:  .LBB1_2: @ %entry
91; CHECK-8M-LE-NEXT:    mov r0, lr
92; CHECK-8M-LE-NEXT:    mov r1, lr
93; CHECK-8M-LE-NEXT:    mov r2, lr
94; CHECK-8M-LE-NEXT:    mov r3, lr
95; CHECK-8M-LE-NEXT:    mov r12, lr
96; CHECK-8M-LE-NEXT:    msr apsr_nzcvqg, lr
97; CHECK-8M-LE-NEXT:    bxns lr
98; CHECK-8M-LE-NEXT:    .p2align 3
99; CHECK-8M-LE-NEXT:  @ %bb.3:
100; CHECK-8M-LE-NEXT:  .LCPI1_0:
101; CHECK-8M-LE-NEXT:    .long 0 @ double 10
102; CHECK-8M-LE-NEXT:    .long 1076101120
103;
104; CHECK-8M-BE-LABEL: d1:
105; CHECK-8M-BE:       @ %bb.0: @ %entry
106; CHECK-8M-BE-NEXT:    push {r7, lr}
107; CHECK-8M-BE-NEXT:    vldr d0, .LCPI1_0
108; CHECK-8M-BE-NEXT:    blx r0
109; CHECK-8M-BE-NEXT:    pop.w {r7, lr}
110; CHECK-8M-BE-NEXT:    mrs r12, control
111; CHECK-8M-BE-NEXT:    tst.w r12, #8
112; CHECK-8M-BE-NEXT:    beq .LBB1_2
113; CHECK-8M-BE-NEXT:  @ %bb.1: @ %entry
114; CHECK-8M-BE-NEXT:    vmrs r12, fpscr
115; CHECK-8M-BE-NEXT:    vmov d1, lr, lr
116; CHECK-8M-BE-NEXT:    vmov d2, lr, lr
117; CHECK-8M-BE-NEXT:    vmov d3, lr, lr
118; CHECK-8M-BE-NEXT:    vmov d4, lr, lr
119; CHECK-8M-BE-NEXT:    vmov d5, lr, lr
120; CHECK-8M-BE-NEXT:    vmov d6, lr, lr
121; CHECK-8M-BE-NEXT:    vmov d7, lr, lr
122; CHECK-8M-BE-NEXT:    bic r12, r12, #159
123; CHECK-8M-BE-NEXT:    bic r12, r12, #4026531840
124; CHECK-8M-BE-NEXT:    vmsr fpscr, r12
125; CHECK-8M-BE-NEXT:  .LBB1_2: @ %entry
126; CHECK-8M-BE-NEXT:    mov r0, lr
127; CHECK-8M-BE-NEXT:    mov r1, lr
128; CHECK-8M-BE-NEXT:    mov r2, lr
129; CHECK-8M-BE-NEXT:    mov r3, lr
130; CHECK-8M-BE-NEXT:    mov r12, lr
131; CHECK-8M-BE-NEXT:    msr apsr_nzcvqg, lr
132; CHECK-8M-BE-NEXT:    bxns lr
133; CHECK-8M-BE-NEXT:    .p2align 3
134; CHECK-8M-BE-NEXT:  @ %bb.3:
135; CHECK-8M-BE-NEXT:  .LCPI1_0:
136; CHECK-8M-BE-NEXT:    .long 1076101120 @ double 10
137; CHECK-8M-BE-NEXT:    .long 0
138;
139; CHECK-81M-LE-LABEL: d1:
140; CHECK-81M-LE:       @ %bb.0: @ %entry
141; CHECK-81M-LE-NEXT:    vstr fpcxtns, [sp, #-4]!
142; CHECK-81M-LE-NEXT:    push {r7, lr}
143; CHECK-81M-LE-NEXT:    sub sp, #4
144; CHECK-81M-LE-NEXT:    vldr d0, .LCPI1_0
145; CHECK-81M-LE-NEXT:    blx r0
146; CHECK-81M-LE-NEXT:    add sp, #4
147; CHECK-81M-LE-NEXT:    pop.w {r7, lr}
148; CHECK-81M-LE-NEXT:    vscclrm {s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, vpr}
149; CHECK-81M-LE-NEXT:    vldr fpcxtns, [sp], #4
150; CHECK-81M-LE-NEXT:    clrm {r0, r1, r2, r3, r12, apsr}
151; CHECK-81M-LE-NEXT:    bxns lr
152; CHECK-81M-LE-NEXT:    .p2align 3
153; CHECK-81M-LE-NEXT:  @ %bb.1:
154; CHECK-81M-LE-NEXT:  .LCPI1_0:
155; CHECK-81M-LE-NEXT:    .long 0 @ double 10
156; CHECK-81M-LE-NEXT:    .long 1076101120
157;
158; CHECK-81M-BE-LABEL: d1:
159; CHECK-81M-BE:       @ %bb.0: @ %entry
160; CHECK-81M-BE-NEXT:    vstr fpcxtns, [sp, #-4]!
161; CHECK-81M-BE-NEXT:    push {r7, lr}
162; CHECK-81M-BE-NEXT:    sub sp, #4
163; CHECK-81M-BE-NEXT:    vldr d0, .LCPI1_0
164; CHECK-81M-BE-NEXT:    blx r0
165; CHECK-81M-BE-NEXT:    add sp, #4
166; CHECK-81M-BE-NEXT:    pop.w {r7, lr}
167; CHECK-81M-BE-NEXT:    vscclrm {s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, vpr}
168; CHECK-81M-BE-NEXT:    vldr fpcxtns, [sp], #4
169; CHECK-81M-BE-NEXT:    clrm {r0, r1, r2, r3, r12, apsr}
170; CHECK-81M-BE-NEXT:    bxns lr
171; CHECK-81M-BE-NEXT:    .p2align 3
172; CHECK-81M-BE-NEXT:  @ %bb.1:
173; CHECK-81M-BE-NEXT:  .LCPI1_0:
174; CHECK-81M-BE-NEXT:    .long 1076101120 @ double 10
175; CHECK-81M-BE-NEXT:    .long 0
176entry:
177  %call = call double %fptr(double 10.0) #1
178  ret double %call
179}
180
181define float @f2(ptr nocapture %fptr) #2 {
182; CHECK-8M-LABEL: f2:
183; CHECK-8M:       @ %bb.0: @ %entry
184; CHECK-8M-NEXT:    push {r7, lr}
185; CHECK-8M-NEXT:    vmov.f32 s0, #1.000000e+01
186; CHECK-8M-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
187; CHECK-8M-NEXT:    bic r0, r0, #1
188; CHECK-8M-NEXT:    sub sp, #136
189; CHECK-8M-NEXT:    vmov r12, s0
190; CHECK-8M-NEXT:    vlstm sp, {d0 - d15}
191; CHECK-8M-NEXT:    vmov s0, r12
192; CHECK-8M-NEXT:    ldr r1, [sp, #64]
193; CHECK-8M-NEXT:    bic r1, r1, #159
194; CHECK-8M-NEXT:    bic r1, r1, #4026531840
195; CHECK-8M-NEXT:    vmsr fpscr, r1
196; CHECK-8M-NEXT:    mov r1, r0
197; CHECK-8M-NEXT:    mov r2, r0
198; CHECK-8M-NEXT:    mov r3, r0
199; CHECK-8M-NEXT:    mov r4, r0
200; CHECK-8M-NEXT:    mov r5, r0
201; CHECK-8M-NEXT:    mov r6, r0
202; CHECK-8M-NEXT:    mov r7, r0
203; CHECK-8M-NEXT:    mov r8, r0
204; CHECK-8M-NEXT:    mov r9, r0
205; CHECK-8M-NEXT:    mov r10, r0
206; CHECK-8M-NEXT:    mov r11, r0
207; CHECK-8M-NEXT:    msr apsr_nzcvqg, r0
208; CHECK-8M-NEXT:    blxns r0
209; CHECK-8M-NEXT:    vmov r12, s0
210; CHECK-8M-NEXT:    vlldm sp, {d0 - d15}
211; CHECK-8M-NEXT:    vmov s0, r12
212; CHECK-8M-NEXT:    add sp, #136
213; CHECK-8M-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
214; CHECK-8M-NEXT:    pop {r7, pc}
215;
216; CHECK-81M-LABEL: f2:
217; CHECK-81M:       @ %bb.0: @ %entry
218; CHECK-81M-NEXT:    push {r7, lr}
219; CHECK-81M-NEXT:    vmov.f32 s0, #1.000000e+01
220; CHECK-81M-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
221; CHECK-81M-NEXT:    bic r0, r0, #1
222; CHECK-81M-NEXT:    vpush {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
223; CHECK-81M-NEXT:    vscclrm {s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, vpr}
224; CHECK-81M-NEXT:    vstr fpcxts, [sp, #-8]!
225; CHECK-81M-NEXT:    clrm {r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, apsr}
226; CHECK-81M-NEXT:    blxns r0
227; CHECK-81M-NEXT:    vldr fpcxts, [sp], #8
228; CHECK-81M-NEXT:    vpop {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
229; CHECK-81M-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
230; CHECK-81M-NEXT:    pop {r7, pc}
231entry:
232  %call = call float %fptr(float 10.0) #3
233  ret float %call
234}
235
236attributes #2 = { nounwind }
237attributes #3 = { "cmse_nonsecure_call" nounwind }
238
239define double @d2(ptr nocapture %fptr) #2 {
240; CHECK-8M-LE-LABEL: d2:
241; CHECK-8M-LE:       @ %bb.0: @ %entry
242; CHECK-8M-LE-NEXT:    push {r7, lr}
243; CHECK-8M-LE-NEXT:    vldr d0, .LCPI3_0
244; CHECK-8M-LE-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
245; CHECK-8M-LE-NEXT:    bic r0, r0, #1
246; CHECK-8M-LE-NEXT:    sub sp, #136
247; CHECK-8M-LE-NEXT:    vmov r11, r12, d0
248; CHECK-8M-LE-NEXT:    vlstm sp, {d0 - d15}
249; CHECK-8M-LE-NEXT:    vmov d0, r11, r12
250; CHECK-8M-LE-NEXT:    ldr r1, [sp, #64]
251; CHECK-8M-LE-NEXT:    bic r1, r1, #159
252; CHECK-8M-LE-NEXT:    bic r1, r1, #4026531840
253; CHECK-8M-LE-NEXT:    vmsr fpscr, r1
254; CHECK-8M-LE-NEXT:    mov r1, r0
255; CHECK-8M-LE-NEXT:    mov r2, r0
256; CHECK-8M-LE-NEXT:    mov r3, r0
257; CHECK-8M-LE-NEXT:    mov r4, r0
258; CHECK-8M-LE-NEXT:    mov r5, r0
259; CHECK-8M-LE-NEXT:    mov r6, r0
260; CHECK-8M-LE-NEXT:    mov r7, r0
261; CHECK-8M-LE-NEXT:    mov r8, r0
262; CHECK-8M-LE-NEXT:    mov r9, r0
263; CHECK-8M-LE-NEXT:    mov r10, r0
264; CHECK-8M-LE-NEXT:    msr apsr_nzcvqg, r0
265; CHECK-8M-LE-NEXT:    blxns r0
266; CHECK-8M-LE-NEXT:    vmov r11, r12, d0
267; CHECK-8M-LE-NEXT:    vlldm sp, {d0 - d15}
268; CHECK-8M-LE-NEXT:    vmov d0, r11, r12
269; CHECK-8M-LE-NEXT:    add sp, #136
270; CHECK-8M-LE-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
271; CHECK-8M-LE-NEXT:    pop {r7, pc}
272; CHECK-8M-LE-NEXT:    .p2align 3
273; CHECK-8M-LE-NEXT:  @ %bb.1:
274; CHECK-8M-LE-NEXT:  .LCPI3_0:
275; CHECK-8M-LE-NEXT:    .long 0 @ double 10
276; CHECK-8M-LE-NEXT:    .long 1076101120
277;
278; CHECK-8M-BE-LABEL: d2:
279; CHECK-8M-BE:       @ %bb.0: @ %entry
280; CHECK-8M-BE-NEXT:    push {r7, lr}
281; CHECK-8M-BE-NEXT:    vldr d0, .LCPI3_0
282; CHECK-8M-BE-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
283; CHECK-8M-BE-NEXT:    bic r0, r0, #1
284; CHECK-8M-BE-NEXT:    sub sp, #136
285; CHECK-8M-BE-NEXT:    vmov r11, r12, d0
286; CHECK-8M-BE-NEXT:    vlstm sp, {d0 - d15}
287; CHECK-8M-BE-NEXT:    vmov d0, r11, r12
288; CHECK-8M-BE-NEXT:    ldr r1, [sp, #64]
289; CHECK-8M-BE-NEXT:    bic r1, r1, #159
290; CHECK-8M-BE-NEXT:    bic r1, r1, #4026531840
291; CHECK-8M-BE-NEXT:    vmsr fpscr, r1
292; CHECK-8M-BE-NEXT:    mov r1, r0
293; CHECK-8M-BE-NEXT:    mov r2, r0
294; CHECK-8M-BE-NEXT:    mov r3, r0
295; CHECK-8M-BE-NEXT:    mov r4, r0
296; CHECK-8M-BE-NEXT:    mov r5, r0
297; CHECK-8M-BE-NEXT:    mov r6, r0
298; CHECK-8M-BE-NEXT:    mov r7, r0
299; CHECK-8M-BE-NEXT:    mov r8, r0
300; CHECK-8M-BE-NEXT:    mov r9, r0
301; CHECK-8M-BE-NEXT:    mov r10, r0
302; CHECK-8M-BE-NEXT:    msr apsr_nzcvqg, r0
303; CHECK-8M-BE-NEXT:    blxns r0
304; CHECK-8M-BE-NEXT:    vmov r11, r12, d0
305; CHECK-8M-BE-NEXT:    vlldm sp, {d0 - d15}
306; CHECK-8M-BE-NEXT:    vmov d0, r11, r12
307; CHECK-8M-BE-NEXT:    add sp, #136
308; CHECK-8M-BE-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
309; CHECK-8M-BE-NEXT:    pop {r7, pc}
310; CHECK-8M-BE-NEXT:    .p2align 3
311; CHECK-8M-BE-NEXT:  @ %bb.1:
312; CHECK-8M-BE-NEXT:  .LCPI3_0:
313; CHECK-8M-BE-NEXT:    .long 1076101120 @ double 10
314; CHECK-8M-BE-NEXT:    .long 0
315;
316; CHECK-81M-LE-LABEL: d2:
317; CHECK-81M-LE:       @ %bb.0: @ %entry
318; CHECK-81M-LE-NEXT:    push {r7, lr}
319; CHECK-81M-LE-NEXT:    vldr d0, .LCPI3_0
320; CHECK-81M-LE-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
321; CHECK-81M-LE-NEXT:    bic r0, r0, #1
322; CHECK-81M-LE-NEXT:    vpush {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
323; CHECK-81M-LE-NEXT:    vscclrm {s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, vpr}
324; CHECK-81M-LE-NEXT:    vstr fpcxts, [sp, #-8]!
325; CHECK-81M-LE-NEXT:    clrm {r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, apsr}
326; CHECK-81M-LE-NEXT:    blxns r0
327; CHECK-81M-LE-NEXT:    vldr fpcxts, [sp], #8
328; CHECK-81M-LE-NEXT:    vpop {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
329; CHECK-81M-LE-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
330; CHECK-81M-LE-NEXT:    pop {r7, pc}
331; CHECK-81M-LE-NEXT:    .p2align 3
332; CHECK-81M-LE-NEXT:  @ %bb.1:
333; CHECK-81M-LE-NEXT:  .LCPI3_0:
334; CHECK-81M-LE-NEXT:    .long 0 @ double 10
335; CHECK-81M-LE-NEXT:    .long 1076101120
336;
337; CHECK-81M-BE-LABEL: d2:
338; CHECK-81M-BE:       @ %bb.0: @ %entry
339; CHECK-81M-BE-NEXT:    push {r7, lr}
340; CHECK-81M-BE-NEXT:    vldr d0, .LCPI3_0
341; CHECK-81M-BE-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
342; CHECK-81M-BE-NEXT:    bic r0, r0, #1
343; CHECK-81M-BE-NEXT:    vpush {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
344; CHECK-81M-BE-NEXT:    vscclrm {s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, vpr}
345; CHECK-81M-BE-NEXT:    vstr fpcxts, [sp, #-8]!
346; CHECK-81M-BE-NEXT:    clrm {r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, apsr}
347; CHECK-81M-BE-NEXT:    blxns r0
348; CHECK-81M-BE-NEXT:    vldr fpcxts, [sp], #8
349; CHECK-81M-BE-NEXT:    vpop {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
350; CHECK-81M-BE-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
351; CHECK-81M-BE-NEXT:    pop {r7, pc}
352; CHECK-81M-BE-NEXT:    .p2align 3
353; CHECK-81M-BE-NEXT:  @ %bb.1:
354; CHECK-81M-BE-NEXT:  .LCPI3_0:
355; CHECK-81M-BE-NEXT:    .long 1076101120 @ double 10
356; CHECK-81M-BE-NEXT:    .long 0
357entry:
358  %call = call double %fptr(double 10.0) #3
359  ret double %call
360}
361
362define float @f3(ptr nocapture %fptr) #4 {
363; CHECK-8M-LABEL: f3:
364; CHECK-8M:       @ %bb.0: @ %entry
365; CHECK-8M-NEXT:    push {r7, lr}
366; CHECK-8M-NEXT:    vmov.f32 s0, #1.000000e+01
367; CHECK-8M-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
368; CHECK-8M-NEXT:    bic r0, r0, #1
369; CHECK-8M-NEXT:    sub sp, #136
370; CHECK-8M-NEXT:    vmov r12, s0
371; CHECK-8M-NEXT:    vlstm sp, {d0 - d15}
372; CHECK-8M-NEXT:    vmov s0, r12
373; CHECK-8M-NEXT:    ldr r1, [sp, #64]
374; CHECK-8M-NEXT:    bic r1, r1, #159
375; CHECK-8M-NEXT:    bic r1, r1, #4026531840
376; CHECK-8M-NEXT:    vmsr fpscr, r1
377; CHECK-8M-NEXT:    mov r1, r0
378; CHECK-8M-NEXT:    mov r2, r0
379; CHECK-8M-NEXT:    mov r3, r0
380; CHECK-8M-NEXT:    mov r4, r0
381; CHECK-8M-NEXT:    mov r5, r0
382; CHECK-8M-NEXT:    mov r6, r0
383; CHECK-8M-NEXT:    mov r7, r0
384; CHECK-8M-NEXT:    mov r8, r0
385; CHECK-8M-NEXT:    mov r9, r0
386; CHECK-8M-NEXT:    mov r10, r0
387; CHECK-8M-NEXT:    mov r11, r0
388; CHECK-8M-NEXT:    msr apsr_nzcvqg, r0
389; CHECK-8M-NEXT:    blxns r0
390; CHECK-8M-NEXT:    vmov r12, s0
391; CHECK-8M-NEXT:    vlldm sp, {d0 - d15}
392; CHECK-8M-NEXT:    vmov s0, r12
393; CHECK-8M-NEXT:    add sp, #136
394; CHECK-8M-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
395; CHECK-8M-NEXT:    pop {r7, pc}
396;
397; CHECK-81M-LABEL: f3:
398; CHECK-81M:       @ %bb.0: @ %entry
399; CHECK-81M-NEXT:    push {r7, lr}
400; CHECK-81M-NEXT:    vmov.f32 s0, #1.000000e+01
401; CHECK-81M-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
402; CHECK-81M-NEXT:    bic r0, r0, #1
403; CHECK-81M-NEXT:    vpush {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
404; CHECK-81M-NEXT:    vscclrm {s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, vpr}
405; CHECK-81M-NEXT:    vstr fpcxts, [sp, #-8]!
406; CHECK-81M-NEXT:    clrm {r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, apsr}
407; CHECK-81M-NEXT:    blxns r0
408; CHECK-81M-NEXT:    vldr fpcxts, [sp], #8
409; CHECK-81M-NEXT:    vpop {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
410; CHECK-81M-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
411; CHECK-81M-NEXT:    pop {r7, pc}
412entry:
413  %call = tail call float %fptr(float 10.0) #5
414  ret float %call
415}
416
417attributes #4 = { nounwind }
418attributes #5 = { "cmse_nonsecure_call" nounwind }
419
420define double @d3(ptr nocapture %fptr) #4 {
421; CHECK-8M-LE-LABEL: d3:
422; CHECK-8M-LE:       @ %bb.0: @ %entry
423; CHECK-8M-LE-NEXT:    push {r7, lr}
424; CHECK-8M-LE-NEXT:    vldr d0, .LCPI5_0
425; CHECK-8M-LE-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
426; CHECK-8M-LE-NEXT:    bic r0, r0, #1
427; CHECK-8M-LE-NEXT:    sub sp, #136
428; CHECK-8M-LE-NEXT:    vmov r11, r12, d0
429; CHECK-8M-LE-NEXT:    vlstm sp, {d0 - d15}
430; CHECK-8M-LE-NEXT:    vmov d0, r11, r12
431; CHECK-8M-LE-NEXT:    ldr r1, [sp, #64]
432; CHECK-8M-LE-NEXT:    bic r1, r1, #159
433; CHECK-8M-LE-NEXT:    bic r1, r1, #4026531840
434; CHECK-8M-LE-NEXT:    vmsr fpscr, r1
435; CHECK-8M-LE-NEXT:    mov r1, r0
436; CHECK-8M-LE-NEXT:    mov r2, r0
437; CHECK-8M-LE-NEXT:    mov r3, r0
438; CHECK-8M-LE-NEXT:    mov r4, r0
439; CHECK-8M-LE-NEXT:    mov r5, r0
440; CHECK-8M-LE-NEXT:    mov r6, r0
441; CHECK-8M-LE-NEXT:    mov r7, r0
442; CHECK-8M-LE-NEXT:    mov r8, r0
443; CHECK-8M-LE-NEXT:    mov r9, r0
444; CHECK-8M-LE-NEXT:    mov r10, r0
445; CHECK-8M-LE-NEXT:    msr apsr_nzcvqg, r0
446; CHECK-8M-LE-NEXT:    blxns r0
447; CHECK-8M-LE-NEXT:    vmov r11, r12, d0
448; CHECK-8M-LE-NEXT:    vlldm sp, {d0 - d15}
449; CHECK-8M-LE-NEXT:    vmov d0, r11, r12
450; CHECK-8M-LE-NEXT:    add sp, #136
451; CHECK-8M-LE-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
452; CHECK-8M-LE-NEXT:    pop {r7, pc}
453; CHECK-8M-LE-NEXT:    .p2align 3
454; CHECK-8M-LE-NEXT:  @ %bb.1:
455; CHECK-8M-LE-NEXT:  .LCPI5_0:
456; CHECK-8M-LE-NEXT:    .long 0 @ double 10
457; CHECK-8M-LE-NEXT:    .long 1076101120
458;
459; CHECK-8M-BE-LABEL: d3:
460; CHECK-8M-BE:       @ %bb.0: @ %entry
461; CHECK-8M-BE-NEXT:    push {r7, lr}
462; CHECK-8M-BE-NEXT:    vldr d0, .LCPI5_0
463; CHECK-8M-BE-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
464; CHECK-8M-BE-NEXT:    bic r0, r0, #1
465; CHECK-8M-BE-NEXT:    sub sp, #136
466; CHECK-8M-BE-NEXT:    vmov r11, r12, d0
467; CHECK-8M-BE-NEXT:    vlstm sp, {d0 - d15}
468; CHECK-8M-BE-NEXT:    vmov d0, r11, r12
469; CHECK-8M-BE-NEXT:    ldr r1, [sp, #64]
470; CHECK-8M-BE-NEXT:    bic r1, r1, #159
471; CHECK-8M-BE-NEXT:    bic r1, r1, #4026531840
472; CHECK-8M-BE-NEXT:    vmsr fpscr, r1
473; CHECK-8M-BE-NEXT:    mov r1, r0
474; CHECK-8M-BE-NEXT:    mov r2, r0
475; CHECK-8M-BE-NEXT:    mov r3, r0
476; CHECK-8M-BE-NEXT:    mov r4, r0
477; CHECK-8M-BE-NEXT:    mov r5, r0
478; CHECK-8M-BE-NEXT:    mov r6, r0
479; CHECK-8M-BE-NEXT:    mov r7, r0
480; CHECK-8M-BE-NEXT:    mov r8, r0
481; CHECK-8M-BE-NEXT:    mov r9, r0
482; CHECK-8M-BE-NEXT:    mov r10, r0
483; CHECK-8M-BE-NEXT:    msr apsr_nzcvqg, r0
484; CHECK-8M-BE-NEXT:    blxns r0
485; CHECK-8M-BE-NEXT:    vmov r11, r12, d0
486; CHECK-8M-BE-NEXT:    vlldm sp, {d0 - d15}
487; CHECK-8M-BE-NEXT:    vmov d0, r11, r12
488; CHECK-8M-BE-NEXT:    add sp, #136
489; CHECK-8M-BE-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
490; CHECK-8M-BE-NEXT:    pop {r7, pc}
491; CHECK-8M-BE-NEXT:    .p2align 3
492; CHECK-8M-BE-NEXT:  @ %bb.1:
493; CHECK-8M-BE-NEXT:  .LCPI5_0:
494; CHECK-8M-BE-NEXT:    .long 1076101120 @ double 10
495; CHECK-8M-BE-NEXT:    .long 0
496;
497; CHECK-81M-LE-LABEL: d3:
498; CHECK-81M-LE:       @ %bb.0: @ %entry
499; CHECK-81M-LE-NEXT:    push {r7, lr}
500; CHECK-81M-LE-NEXT:    vldr d0, .LCPI5_0
501; CHECK-81M-LE-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
502; CHECK-81M-LE-NEXT:    bic r0, r0, #1
503; CHECK-81M-LE-NEXT:    vpush {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
504; CHECK-81M-LE-NEXT:    vscclrm {s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, vpr}
505; CHECK-81M-LE-NEXT:    vstr fpcxts, [sp, #-8]!
506; CHECK-81M-LE-NEXT:    clrm {r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, apsr}
507; CHECK-81M-LE-NEXT:    blxns r0
508; CHECK-81M-LE-NEXT:    vldr fpcxts, [sp], #8
509; CHECK-81M-LE-NEXT:    vpop {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
510; CHECK-81M-LE-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
511; CHECK-81M-LE-NEXT:    pop {r7, pc}
512; CHECK-81M-LE-NEXT:    .p2align 3
513; CHECK-81M-LE-NEXT:  @ %bb.1:
514; CHECK-81M-LE-NEXT:  .LCPI5_0:
515; CHECK-81M-LE-NEXT:    .long 0 @ double 10
516; CHECK-81M-LE-NEXT:    .long 1076101120
517;
518; CHECK-81M-BE-LABEL: d3:
519; CHECK-81M-BE:       @ %bb.0: @ %entry
520; CHECK-81M-BE-NEXT:    push {r7, lr}
521; CHECK-81M-BE-NEXT:    vldr d0, .LCPI5_0
522; CHECK-81M-BE-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
523; CHECK-81M-BE-NEXT:    bic r0, r0, #1
524; CHECK-81M-BE-NEXT:    vpush {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
525; CHECK-81M-BE-NEXT:    vscclrm {s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, vpr}
526; CHECK-81M-BE-NEXT:    vstr fpcxts, [sp, #-8]!
527; CHECK-81M-BE-NEXT:    clrm {r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, apsr}
528; CHECK-81M-BE-NEXT:    blxns r0
529; CHECK-81M-BE-NEXT:    vldr fpcxts, [sp], #8
530; CHECK-81M-BE-NEXT:    vpop {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
531; CHECK-81M-BE-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
532; CHECK-81M-BE-NEXT:    pop {r7, pc}
533; CHECK-81M-BE-NEXT:    .p2align 3
534; CHECK-81M-BE-NEXT:  @ %bb.1:
535; CHECK-81M-BE-NEXT:  .LCPI5_0:
536; CHECK-81M-BE-NEXT:    .long 1076101120 @ double 10
537; CHECK-81M-BE-NEXT:    .long 0
538entry:
539  %call = tail call double %fptr(double 10.0) #5
540  ret double %call
541}
542
543define float @f4(ptr nocapture %fptr) #6 {
544; CHECK-8M-LABEL: f4:
545; CHECK-8M:       @ %bb.0: @ %entry
546; CHECK-8M-NEXT:    push {r7, lr}
547; CHECK-8M-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
548; CHECK-8M-NEXT:    bic r0, r0, #1
549; CHECK-8M-NEXT:    sub sp, #136
550; CHECK-8M-NEXT:    vmov.f32 s0, s0
551; CHECK-8M-NEXT:    mov r1, r0
552; CHECK-8M-NEXT:    vlstm sp, {d0 - d15}
553; CHECK-8M-NEXT:    mov r2, r0
554; CHECK-8M-NEXT:    mov r3, r0
555; CHECK-8M-NEXT:    mov r4, r0
556; CHECK-8M-NEXT:    mov r5, r0
557; CHECK-8M-NEXT:    mov r6, r0
558; CHECK-8M-NEXT:    mov r7, r0
559; CHECK-8M-NEXT:    mov r8, r0
560; CHECK-8M-NEXT:    mov r9, r0
561; CHECK-8M-NEXT:    mov r10, r0
562; CHECK-8M-NEXT:    mov r11, r0
563; CHECK-8M-NEXT:    mov r12, r0
564; CHECK-8M-NEXT:    msr apsr_nzcvqg, r0
565; CHECK-8M-NEXT:    blxns r0
566; CHECK-8M-NEXT:    vmov r12, s0
567; CHECK-8M-NEXT:    vlldm sp, {d0 - d15}
568; CHECK-8M-NEXT:    vmov s0, r12
569; CHECK-8M-NEXT:    add sp, #136
570; CHECK-8M-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
571; CHECK-8M-NEXT:    pop {r7, pc}
572;
573; CHECK-81M-LABEL: f4:
574; CHECK-81M:       @ %bb.0: @ %entry
575; CHECK-81M-NEXT:    push {r7, lr}
576; CHECK-81M-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
577; CHECK-81M-NEXT:    bic r0, r0, #1
578; CHECK-81M-NEXT:    vpush {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
579; CHECK-81M-NEXT:    vscclrm {s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, vpr}
580; CHECK-81M-NEXT:    vstr fpcxts, [sp, #-8]!
581; CHECK-81M-NEXT:    clrm {r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, apsr}
582; CHECK-81M-NEXT:    blxns r0
583; CHECK-81M-NEXT:    vldr fpcxts, [sp], #8
584; CHECK-81M-NEXT:    vpop {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
585; CHECK-81M-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
586; CHECK-81M-NEXT:    pop {r7, pc}
587entry:
588  %call = call float %fptr() #7
589  ret float %call
590}
591
592attributes #6 = { nounwind }
593attributes #7 = { "cmse_nonsecure_call" nounwind }
594
595define double @d4(ptr nocapture %fptr) #6 {
596; CHECK-8M-LABEL: d4:
597; CHECK-8M:       @ %bb.0: @ %entry
598; CHECK-8M-NEXT:    push {r7, lr}
599; CHECK-8M-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
600; CHECK-8M-NEXT:    bic r0, r0, #1
601; CHECK-8M-NEXT:    sub sp, #136
602; CHECK-8M-NEXT:    vmov.f32 s0, s0
603; CHECK-8M-NEXT:    mov r1, r0
604; CHECK-8M-NEXT:    vlstm sp, {d0 - d15}
605; CHECK-8M-NEXT:    mov r2, r0
606; CHECK-8M-NEXT:    mov r3, r0
607; CHECK-8M-NEXT:    mov r4, r0
608; CHECK-8M-NEXT:    mov r5, r0
609; CHECK-8M-NEXT:    mov r6, r0
610; CHECK-8M-NEXT:    mov r7, r0
611; CHECK-8M-NEXT:    mov r8, r0
612; CHECK-8M-NEXT:    mov r9, r0
613; CHECK-8M-NEXT:    mov r10, r0
614; CHECK-8M-NEXT:    mov r11, r0
615; CHECK-8M-NEXT:    mov r12, r0
616; CHECK-8M-NEXT:    msr apsr_nzcvqg, r0
617; CHECK-8M-NEXT:    blxns r0
618; CHECK-8M-NEXT:    vmov r11, r12, d0
619; CHECK-8M-NEXT:    vlldm sp, {d0 - d15}
620; CHECK-8M-NEXT:    vmov d0, r11, r12
621; CHECK-8M-NEXT:    add sp, #136
622; CHECK-8M-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
623; CHECK-8M-NEXT:    pop {r7, pc}
624;
625; CHECK-81M-LABEL: d4:
626; CHECK-81M:       @ %bb.0: @ %entry
627; CHECK-81M-NEXT:    push {r7, lr}
628; CHECK-81M-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
629; CHECK-81M-NEXT:    bic r0, r0, #1
630; CHECK-81M-NEXT:    vpush {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
631; CHECK-81M-NEXT:    vscclrm {s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, vpr}
632; CHECK-81M-NEXT:    vstr fpcxts, [sp, #-8]!
633; CHECK-81M-NEXT:    clrm {r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, apsr}
634; CHECK-81M-NEXT:    blxns r0
635; CHECK-81M-NEXT:    vldr fpcxts, [sp], #8
636; CHECK-81M-NEXT:    vpop {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
637; CHECK-81M-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
638; CHECK-81M-NEXT:    pop {r7, pc}
639entry:
640  %call = call double %fptr() #7
641  ret double %call
642}
643
644define void @fd(ptr %f, float %a, double %b) #8 {
645; CHECK-8M-LABEL: fd:
646; CHECK-8M:       @ %bb.0: @ %entry
647; CHECK-8M-NEXT:    push {r7, lr}
648; CHECK-8M-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
649; CHECK-8M-NEXT:    bic r0, r0, #1
650; CHECK-8M-NEXT:    sub sp, #136
651; CHECK-8M-NEXT:    vmov r12, s0
652; CHECK-8M-NEXT:    mov r2, r0
653; CHECK-8M-NEXT:    vmov r10, r11, d1
654; CHECK-8M-NEXT:    vlstm sp, {d0 - d15}
655; CHECK-8M-NEXT:    vmov s0, r12
656; CHECK-8M-NEXT:    vmov d1, r10, r11
657; CHECK-8M-NEXT:    ldr r1, [sp, #64]
658; CHECK-8M-NEXT:    bic r1, r1, #159
659; CHECK-8M-NEXT:    bic r1, r1, #4026531840
660; CHECK-8M-NEXT:    vmsr fpscr, r1
661; CHECK-8M-NEXT:    mov r1, r0
662; CHECK-8M-NEXT:    mov r3, r0
663; CHECK-8M-NEXT:    mov r4, r0
664; CHECK-8M-NEXT:    mov r5, r0
665; CHECK-8M-NEXT:    mov r6, r0
666; CHECK-8M-NEXT:    mov r7, r0
667; CHECK-8M-NEXT:    mov r8, r0
668; CHECK-8M-NEXT:    mov r9, r0
669; CHECK-8M-NEXT:    msr apsr_nzcvqg, r0
670; CHECK-8M-NEXT:    blxns r0
671; CHECK-8M-NEXT:    vlldm sp, {d0 - d15}
672; CHECK-8M-NEXT:    add sp, #136
673; CHECK-8M-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
674; CHECK-8M-NEXT:    pop {r7, pc}
675;
676; CHECK-81M-LABEL: fd:
677; CHECK-81M:       @ %bb.0: @ %entry
678; CHECK-81M-NEXT:    push {r7, lr}
679; CHECK-81M-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
680; CHECK-81M-NEXT:    bic r0, r0, #1
681; CHECK-81M-NEXT:    vpush {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
682; CHECK-81M-NEXT:    vscclrm {s1, vpr}
683; CHECK-81M-NEXT:    vscclrm {s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, vpr}
684; CHECK-81M-NEXT:    vstr fpcxts, [sp, #-8]!
685; CHECK-81M-NEXT:    clrm {r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, apsr}
686; CHECK-81M-NEXT:    blxns r0
687; CHECK-81M-NEXT:    vldr fpcxts, [sp], #8
688; CHECK-81M-NEXT:    vpop {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
689; CHECK-81M-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
690; CHECK-81M-NEXT:    pop {r7, pc}
691entry:
692  call void %f(float %a, double %b) #9
693  ret void
694}
695
696attributes #8 = { nounwind }
697attributes #9 = { "cmse_nonsecure_call" nounwind }
698
699define void @fdff(ptr %f, float %a, double %b, float %c, float %d) #8 {
700; CHECK-8M-LABEL: fdff:
701; CHECK-8M:       @ %bb.0: @ %entry
702; CHECK-8M-NEXT:    push {r7, lr}
703; CHECK-8M-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
704; CHECK-8M-NEXT:    bic r0, r0, #1
705; CHECK-8M-NEXT:    sub sp, #136
706; CHECK-8M-NEXT:    vmov r12, s0
707; CHECK-8M-NEXT:    mov r2, r0
708; CHECK-8M-NEXT:    vmov r10, r11, d1
709; CHECK-8M-NEXT:    mov r3, r0
710; CHECK-8M-NEXT:    vmov r9, s1
711; CHECK-8M-NEXT:    mov r4, r0
712; CHECK-8M-NEXT:    vmov r8, s4
713; CHECK-8M-NEXT:    vlstm sp, {d0 - d15}
714; CHECK-8M-NEXT:    vmov s0, r12
715; CHECK-8M-NEXT:    vmov d1, r10, r11
716; CHECK-8M-NEXT:    vmov s1, r9
717; CHECK-8M-NEXT:    vmov s4, r8
718; CHECK-8M-NEXT:    ldr r1, [sp, #64]
719; CHECK-8M-NEXT:    bic r1, r1, #159
720; CHECK-8M-NEXT:    bic r1, r1, #4026531840
721; CHECK-8M-NEXT:    vmsr fpscr, r1
722; CHECK-8M-NEXT:    mov r1, r0
723; CHECK-8M-NEXT:    mov r5, r0
724; CHECK-8M-NEXT:    mov r6, r0
725; CHECK-8M-NEXT:    mov r7, r0
726; CHECK-8M-NEXT:    msr apsr_nzcvqg, r0
727; CHECK-8M-NEXT:    blxns r0
728; CHECK-8M-NEXT:    vlldm sp, {d0 - d15}
729; CHECK-8M-NEXT:    add sp, #136
730; CHECK-8M-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
731; CHECK-8M-NEXT:    pop {r7, pc}
732;
733; CHECK-81M-LABEL: fdff:
734; CHECK-81M:       @ %bb.0: @ %entry
735; CHECK-81M-NEXT:    push {r7, lr}
736; CHECK-81M-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
737; CHECK-81M-NEXT:    bic r0, r0, #1
738; CHECK-81M-NEXT:    vpush {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
739; CHECK-81M-NEXT:    vscclrm {s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, vpr}
740; CHECK-81M-NEXT:    vstr fpcxts, [sp, #-8]!
741; CHECK-81M-NEXT:    clrm {r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, apsr}
742; CHECK-81M-NEXT:    blxns r0
743; CHECK-81M-NEXT:    vldr fpcxts, [sp], #8
744; CHECK-81M-NEXT:    vpop {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
745; CHECK-81M-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
746; CHECK-81M-NEXT:    pop {r7, pc}
747entry:
748  call void %f(float %a, double %b, float %c, float %d) #9
749  ret void
750}
751
752define void @fidififid(ptr %fu, float %a, i32 %b, double %c, i32 %d, float %e, i32 %f, float %g, i32 %h, double %i) #8 {
753; CHECK-8M-LABEL: fidififid:
754; CHECK-8M:       @ %bb.0: @ %entry
755; CHECK-8M-NEXT:    push {r7, lr}
756; CHECK-8M-NEXT:    mov lr, r3
757; CHECK-8M-NEXT:    mov r12, r0
758; CHECK-8M-NEXT:    mov r0, r1
759; CHECK-8M-NEXT:    mov r1, r2
760; CHECK-8M-NEXT:    ldr r3, [sp, #8]
761; CHECK-8M-NEXT:    mov r2, lr
762; CHECK-8M-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
763; CHECK-8M-NEXT:    bic r12, r12, #1
764; CHECK-8M-NEXT:    sub sp, #136
765; CHECK-8M-NEXT:    vmov r11, s0
766; CHECK-8M-NEXT:    vmov r9, r10, d1
767; CHECK-8M-NEXT:    vmov r8, s1
768; CHECK-8M-NEXT:    vmov r7, s4
769; CHECK-8M-NEXT:    vmov r5, r6, d3
770; CHECK-8M-NEXT:    vlstm sp, {d0 - d15}
771; CHECK-8M-NEXT:    vmov s0, r11
772; CHECK-8M-NEXT:    vmov d1, r9, r10
773; CHECK-8M-NEXT:    vmov s1, r8
774; CHECK-8M-NEXT:    vmov s4, r7
775; CHECK-8M-NEXT:    vmov d3, r5, r6
776; CHECK-8M-NEXT:    ldr r4, [sp, #64]
777; CHECK-8M-NEXT:    bic r4, r4, #159
778; CHECK-8M-NEXT:    bic r4, r4, #4026531840
779; CHECK-8M-NEXT:    vmsr fpscr, r4
780; CHECK-8M-NEXT:    mov r4, r12
781; CHECK-8M-NEXT:    msr apsr_nzcvqg, r12
782; CHECK-8M-NEXT:    blxns r12
783; CHECK-8M-NEXT:    vlldm sp, {d0 - d15}
784; CHECK-8M-NEXT:    add sp, #136
785; CHECK-8M-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
786; CHECK-8M-NEXT:    pop {r7, pc}
787;
788; CHECK-81M-LABEL: fidififid:
789; CHECK-81M:       @ %bb.0: @ %entry
790; CHECK-81M-NEXT:    push {r7, lr}
791; CHECK-81M-NEXT:    mov lr, r3
792; CHECK-81M-NEXT:    mov r12, r0
793; CHECK-81M-NEXT:    mov r0, r1
794; CHECK-81M-NEXT:    mov r1, r2
795; CHECK-81M-NEXT:    ldr r3, [sp, #8]
796; CHECK-81M-NEXT:    mov r2, lr
797; CHECK-81M-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
798; CHECK-81M-NEXT:    bic r12, r12, #1
799; CHECK-81M-NEXT:    vpush {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
800; CHECK-81M-NEXT:    vscclrm {s5, vpr}
801; CHECK-81M-NEXT:    vscclrm {s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, vpr}
802; CHECK-81M-NEXT:    vstr fpcxts, [sp, #-8]!
803; CHECK-81M-NEXT:    clrm {r4, r5, r6, r7, r8, r9, r10, r11, apsr}
804; CHECK-81M-NEXT:    blxns r12
805; CHECK-81M-NEXT:    vldr fpcxts, [sp], #8
806; CHECK-81M-NEXT:    vpop {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
807; CHECK-81M-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
808; CHECK-81M-NEXT:    pop {r7, pc}
809entry:
810  call void %fu(float %a, i32 %b, double %c, i32 %d, float %e, i32 %f, float %g, i32 %h, double %i) #9
811  ret void
812}
813
814define half @h1(ptr nocapture %hptr) "cmse_nonsecure_entry" nounwind {
815; CHECK-8M-LABEL: h1:
816; CHECK-8M:       @ %bb.0:
817; CHECK-8M-NEXT:    push {r7, lr}
818; CHECK-8M-NEXT:    vldr s0, .LCPI11_0
819; CHECK-8M-NEXT:    blx r0
820; CHECK-8M-NEXT:    vmov r0, s0
821; CHECK-8M-NEXT:    uxth r0, r0
822; CHECK-8M-NEXT:    vmov s0, r0
823; CHECK-8M-NEXT:    pop.w {r7, lr}
824; CHECK-8M-NEXT:    mrs r12, control
825; CHECK-8M-NEXT:    tst.w r12, #8
826; CHECK-8M-NEXT:    beq .LBB11_2
827; CHECK-8M-NEXT:  @ %bb.1:
828; CHECK-8M-NEXT:    vmrs r12, fpscr
829; CHECK-8M-NEXT:    vmov s1, lr
830; CHECK-8M-NEXT:    vmov d1, lr, lr
831; CHECK-8M-NEXT:    vmov d2, lr, lr
832; CHECK-8M-NEXT:    vmov d3, lr, lr
833; CHECK-8M-NEXT:    vmov d4, lr, lr
834; CHECK-8M-NEXT:    vmov d5, lr, lr
835; CHECK-8M-NEXT:    vmov d6, lr, lr
836; CHECK-8M-NEXT:    vmov d7, lr, lr
837; CHECK-8M-NEXT:    bic r12, r12, #159
838; CHECK-8M-NEXT:    bic r12, r12, #4026531840
839; CHECK-8M-NEXT:    vmsr fpscr, r12
840; CHECK-8M-NEXT:  .LBB11_2:
841; CHECK-8M-NEXT:    mov r0, lr
842; CHECK-8M-NEXT:    mov r1, lr
843; CHECK-8M-NEXT:    mov r2, lr
844; CHECK-8M-NEXT:    mov r3, lr
845; CHECK-8M-NEXT:    mov r12, lr
846; CHECK-8M-NEXT:    msr apsr_nzcvqg, lr
847; CHECK-8M-NEXT:    bxns lr
848; CHECK-8M-NEXT:    .p2align 2
849; CHECK-8M-NEXT:  @ %bb.3:
850; CHECK-8M-NEXT:  .LCPI11_0:
851; CHECK-8M-NEXT:    .long 0x00004900 @ float 2.61874657E-41
852;
853; CHECK-NO-MVE-LABEL: h1:
854; CHECK-NO-MVE:       @ %bb.0:
855; CHECK-NO-MVE-NEXT:    vstr fpcxtns, [sp, #-4]!
856; CHECK-NO-MVE-NEXT:    push {r7, lr}
857; CHECK-NO-MVE-NEXT:    sub sp, #4
858; CHECK-NO-MVE-NEXT:    vldr s0, .LCPI11_0
859; CHECK-NO-MVE-NEXT:    blx r0
860; CHECK-NO-MVE-NEXT:    vmov r0, s0
861; CHECK-NO-MVE-NEXT:    uxth r0, r0
862; CHECK-NO-MVE-NEXT:    vmov s0, r0
863; CHECK-NO-MVE-NEXT:    add sp, #4
864; CHECK-NO-MVE-NEXT:    pop.w {r7, lr}
865; CHECK-NO-MVE-NEXT:    vscclrm {s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, vpr}
866; CHECK-NO-MVE-NEXT:    vldr fpcxtns, [sp], #4
867; CHECK-NO-MVE-NEXT:    clrm {r0, r1, r2, r3, r12, apsr}
868; CHECK-NO-MVE-NEXT:    bxns lr
869; CHECK-NO-MVE-NEXT:    .p2align 2
870; CHECK-NO-MVE-NEXT:  @ %bb.1:
871; CHECK-NO-MVE-NEXT:  .LCPI11_0:
872; CHECK-NO-MVE-NEXT:    .long 0x00004900 @ float 2.61874657E-41
873;
874; CHECK-MVE-LABEL: h1:
875; CHECK-MVE:       @ %bb.0:
876; CHECK-MVE-NEXT:    vstr fpcxtns, [sp, #-4]!
877; CHECK-MVE-NEXT:    push {r7, lr}
878; CHECK-MVE-NEXT:    sub sp, #4
879; CHECK-MVE-NEXT:    vmov.f16 s0, #1.000000e+01
880; CHECK-MVE-NEXT:    blx r0
881; CHECK-MVE-NEXT:    vmov.f16 r0, s0
882; CHECK-MVE-NEXT:    vmov s0, r0
883; CHECK-MVE-NEXT:    add sp, #4
884; CHECK-MVE-NEXT:    pop.w {r7, lr}
885; CHECK-MVE-NEXT:    vscclrm {s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, vpr}
886; CHECK-MVE-NEXT:    vldr fpcxtns, [sp], #4
887; CHECK-MVE-NEXT:    clrm {r0, r1, r2, r3, r12, apsr}
888; CHECK-MVE-NEXT:    bxns lr
889  %call = call half %hptr(half 10.0) nounwind
890  ret half %call
891}
892
893define half @h2(ptr nocapture %hptr) nounwind {
894; CHECK-8M-LABEL: h2:
895; CHECK-8M:       @ %bb.0: @ %entry
896; CHECK-8M-NEXT:    push {r7, lr}
897; CHECK-8M-NEXT:    vldr s0, .LCPI12_0
898; CHECK-8M-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
899; CHECK-8M-NEXT:    bic r0, r0, #1
900; CHECK-8M-NEXT:    sub sp, #136
901; CHECK-8M-NEXT:    vmov r12, s0
902; CHECK-8M-NEXT:    vlstm sp, {d0 - d15}
903; CHECK-8M-NEXT:    vmov s0, r12
904; CHECK-8M-NEXT:    ldr r1, [sp, #64]
905; CHECK-8M-NEXT:    bic r1, r1, #159
906; CHECK-8M-NEXT:    bic r1, r1, #4026531840
907; CHECK-8M-NEXT:    vmsr fpscr, r1
908; CHECK-8M-NEXT:    mov r1, r0
909; CHECK-8M-NEXT:    mov r2, r0
910; CHECK-8M-NEXT:    mov r3, r0
911; CHECK-8M-NEXT:    mov r4, r0
912; CHECK-8M-NEXT:    mov r5, r0
913; CHECK-8M-NEXT:    mov r6, r0
914; CHECK-8M-NEXT:    mov r7, r0
915; CHECK-8M-NEXT:    mov r8, r0
916; CHECK-8M-NEXT:    mov r9, r0
917; CHECK-8M-NEXT:    mov r10, r0
918; CHECK-8M-NEXT:    mov r11, r0
919; CHECK-8M-NEXT:    msr apsr_nzcvqg, r0
920; CHECK-8M-NEXT:    blxns r0
921; CHECK-8M-NEXT:    vmov r12, s0
922; CHECK-8M-NEXT:    vlldm sp, {d0 - d15}
923; CHECK-8M-NEXT:    vmov s0, r12
924; CHECK-8M-NEXT:    add sp, #136
925; CHECK-8M-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
926; CHECK-8M-NEXT:    pop {r7, pc}
927; CHECK-8M-NEXT:    .p2align 2
928; CHECK-8M-NEXT:  @ %bb.1:
929; CHECK-8M-NEXT:  .LCPI12_0:
930; CHECK-8M-NEXT:    .long 0x00004900 @ float 2.61874657E-41
931;
932; CHECK-NO-MVE-LABEL: h2:
933; CHECK-NO-MVE:       @ %bb.0: @ %entry
934; CHECK-NO-MVE-NEXT:    push {r7, lr}
935; CHECK-NO-MVE-NEXT:    vldr s0, .LCPI12_0
936; CHECK-NO-MVE-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
937; CHECK-NO-MVE-NEXT:    bic r0, r0, #1
938; CHECK-NO-MVE-NEXT:    vpush {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
939; CHECK-NO-MVE-NEXT:    vscclrm {s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, vpr}
940; CHECK-NO-MVE-NEXT:    vstr fpcxts, [sp, #-8]!
941; CHECK-NO-MVE-NEXT:    clrm {r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, apsr}
942; CHECK-NO-MVE-NEXT:    blxns r0
943; CHECK-NO-MVE-NEXT:    vldr fpcxts, [sp], #8
944; CHECK-NO-MVE-NEXT:    vpop {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
945; CHECK-NO-MVE-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
946; CHECK-NO-MVE-NEXT:    pop {r7, pc}
947; CHECK-NO-MVE-NEXT:    .p2align 2
948; CHECK-NO-MVE-NEXT:  @ %bb.1:
949; CHECK-NO-MVE-NEXT:  .LCPI12_0:
950; CHECK-NO-MVE-NEXT:    .long 0x00004900 @ float 2.61874657E-41
951;
952; CHECK-MVE-LABEL: h2:
953; CHECK-MVE:       @ %bb.0: @ %entry
954; CHECK-MVE-NEXT:    push {r7, lr}
955; CHECK-MVE-NEXT:    vmov.f16 s0, #1.000000e+01
956; CHECK-MVE-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
957; CHECK-MVE-NEXT:    bic r0, r0, #1
958; CHECK-MVE-NEXT:    vpush {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
959; CHECK-MVE-NEXT:    vscclrm {s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, vpr}
960; CHECK-MVE-NEXT:    vstr fpcxts, [sp, #-8]!
961; CHECK-MVE-NEXT:    clrm {r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, apsr}
962; CHECK-MVE-NEXT:    blxns r0
963; CHECK-MVE-NEXT:    vldr fpcxts, [sp], #8
964; CHECK-MVE-NEXT:    vpop {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
965; CHECK-MVE-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
966; CHECK-MVE-NEXT:    pop {r7, pc}
967entry:
968  %call = call half %hptr(half 10.0) "cmse_nonsecure_call" nounwind
969  ret half %call
970}
971
972define half @h3(ptr nocapture %hptr) nounwind {
973; CHECK-8M-LABEL: h3:
974; CHECK-8M:       @ %bb.0: @ %entry
975; CHECK-8M-NEXT:    push {r7, lr}
976; CHECK-8M-NEXT:    vldr s0, .LCPI13_0
977; CHECK-8M-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
978; CHECK-8M-NEXT:    bic r0, r0, #1
979; CHECK-8M-NEXT:    sub sp, #136
980; CHECK-8M-NEXT:    vmov r12, s0
981; CHECK-8M-NEXT:    vlstm sp, {d0 - d15}
982; CHECK-8M-NEXT:    vmov s0, r12
983; CHECK-8M-NEXT:    ldr r1, [sp, #64]
984; CHECK-8M-NEXT:    bic r1, r1, #159
985; CHECK-8M-NEXT:    bic r1, r1, #4026531840
986; CHECK-8M-NEXT:    vmsr fpscr, r1
987; CHECK-8M-NEXT:    mov r1, r0
988; CHECK-8M-NEXT:    mov r2, r0
989; CHECK-8M-NEXT:    mov r3, r0
990; CHECK-8M-NEXT:    mov r4, r0
991; CHECK-8M-NEXT:    mov r5, r0
992; CHECK-8M-NEXT:    mov r6, r0
993; CHECK-8M-NEXT:    mov r7, r0
994; CHECK-8M-NEXT:    mov r8, r0
995; CHECK-8M-NEXT:    mov r9, r0
996; CHECK-8M-NEXT:    mov r10, r0
997; CHECK-8M-NEXT:    mov r11, r0
998; CHECK-8M-NEXT:    msr apsr_nzcvqg, r0
999; CHECK-8M-NEXT:    blxns r0
1000; CHECK-8M-NEXT:    vmov r12, s0
1001; CHECK-8M-NEXT:    vlldm sp, {d0 - d15}
1002; CHECK-8M-NEXT:    vmov s0, r12
1003; CHECK-8M-NEXT:    add sp, #136
1004; CHECK-8M-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
1005; CHECK-8M-NEXT:    pop {r7, pc}
1006; CHECK-8M-NEXT:    .p2align 2
1007; CHECK-8M-NEXT:  @ %bb.1:
1008; CHECK-8M-NEXT:  .LCPI13_0:
1009; CHECK-8M-NEXT:    .long 0x00004900 @ float 2.61874657E-41
1010;
1011; CHECK-NO-MVE-LABEL: h3:
1012; CHECK-NO-MVE:       @ %bb.0: @ %entry
1013; CHECK-NO-MVE-NEXT:    push {r7, lr}
1014; CHECK-NO-MVE-NEXT:    vldr s0, .LCPI13_0
1015; CHECK-NO-MVE-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
1016; CHECK-NO-MVE-NEXT:    bic r0, r0, #1
1017; CHECK-NO-MVE-NEXT:    vpush {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
1018; CHECK-NO-MVE-NEXT:    vscclrm {s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, vpr}
1019; CHECK-NO-MVE-NEXT:    vstr fpcxts, [sp, #-8]!
1020; CHECK-NO-MVE-NEXT:    clrm {r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, apsr}
1021; CHECK-NO-MVE-NEXT:    blxns r0
1022; CHECK-NO-MVE-NEXT:    vldr fpcxts, [sp], #8
1023; CHECK-NO-MVE-NEXT:    vpop {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
1024; CHECK-NO-MVE-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
1025; CHECK-NO-MVE-NEXT:    pop {r7, pc}
1026; CHECK-NO-MVE-NEXT:    .p2align 2
1027; CHECK-NO-MVE-NEXT:  @ %bb.1:
1028; CHECK-NO-MVE-NEXT:  .LCPI13_0:
1029; CHECK-NO-MVE-NEXT:    .long 0x00004900 @ float 2.61874657E-41
1030;
1031; CHECK-MVE-LABEL: h3:
1032; CHECK-MVE:       @ %bb.0: @ %entry
1033; CHECK-MVE-NEXT:    push {r7, lr}
1034; CHECK-MVE-NEXT:    vmov.f16 s0, #1.000000e+01
1035; CHECK-MVE-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
1036; CHECK-MVE-NEXT:    bic r0, r0, #1
1037; CHECK-MVE-NEXT:    vpush {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
1038; CHECK-MVE-NEXT:    vscclrm {s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, vpr}
1039; CHECK-MVE-NEXT:    vstr fpcxts, [sp, #-8]!
1040; CHECK-MVE-NEXT:    clrm {r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, apsr}
1041; CHECK-MVE-NEXT:    blxns r0
1042; CHECK-MVE-NEXT:    vldr fpcxts, [sp], #8
1043; CHECK-MVE-NEXT:    vpop {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
1044; CHECK-MVE-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
1045; CHECK-MVE-NEXT:    pop {r7, pc}
1046entry:
1047  %call = tail call half %hptr(half 10.0) "cmse_nonsecure_call" nounwind
1048  ret half %call
1049}
1050
1051define half @h4(ptr nocapture %hptr) nounwind {
1052; CHECK-8M-LABEL: h4:
1053; CHECK-8M:       @ %bb.0: @ %entry
1054; CHECK-8M-NEXT:    push {r7, lr}
1055; CHECK-8M-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
1056; CHECK-8M-NEXT:    bic r0, r0, #1
1057; CHECK-8M-NEXT:    sub sp, #136
1058; CHECK-8M-NEXT:    vmov.f32 s0, s0
1059; CHECK-8M-NEXT:    mov r1, r0
1060; CHECK-8M-NEXT:    vlstm sp, {d0 - d15}
1061; CHECK-8M-NEXT:    mov r2, r0
1062; CHECK-8M-NEXT:    mov r3, r0
1063; CHECK-8M-NEXT:    mov r4, r0
1064; CHECK-8M-NEXT:    mov r5, r0
1065; CHECK-8M-NEXT:    mov r6, r0
1066; CHECK-8M-NEXT:    mov r7, r0
1067; CHECK-8M-NEXT:    mov r8, r0
1068; CHECK-8M-NEXT:    mov r9, r0
1069; CHECK-8M-NEXT:    mov r10, r0
1070; CHECK-8M-NEXT:    mov r11, r0
1071; CHECK-8M-NEXT:    mov r12, r0
1072; CHECK-8M-NEXT:    msr apsr_nzcvqg, r0
1073; CHECK-8M-NEXT:    blxns r0
1074; CHECK-8M-NEXT:    vmov r12, s0
1075; CHECK-8M-NEXT:    vlldm sp, {d0 - d15}
1076; CHECK-8M-NEXT:    vmov s0, r12
1077; CHECK-8M-NEXT:    add sp, #136
1078; CHECK-8M-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
1079; CHECK-8M-NEXT:    pop {r7, pc}
1080;
1081; CHECK-81M-LABEL: h4:
1082; CHECK-81M:       @ %bb.0: @ %entry
1083; CHECK-81M-NEXT:    push {r7, lr}
1084; CHECK-81M-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
1085; CHECK-81M-NEXT:    bic r0, r0, #1
1086; CHECK-81M-NEXT:    vpush {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
1087; CHECK-81M-NEXT:    vscclrm {s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, vpr}
1088; CHECK-81M-NEXT:    vstr fpcxts, [sp, #-8]!
1089; CHECK-81M-NEXT:    clrm {r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, apsr}
1090; CHECK-81M-NEXT:    blxns r0
1091; CHECK-81M-NEXT:    vldr fpcxts, [sp], #8
1092; CHECK-81M-NEXT:    vpop {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
1093; CHECK-81M-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
1094; CHECK-81M-NEXT:    pop {r7, pc}
1095entry:
1096  %call = call half %hptr() "cmse_nonsecure_call" nounwind
1097  ret half %call
1098}
1099
1100define half @h1_minsize(ptr nocapture %hptr) "cmse_nonsecure_entry" minsize nounwind {
1101; CHECK-8M-LABEL: h1_minsize:
1102; CHECK-8M:       @ %bb.0: @ %entry
1103; CHECK-8M-NEXT:    push {r7, lr}
1104; CHECK-8M-NEXT:    vldr s0, .LCPI15_0
1105; CHECK-8M-NEXT:    blx r0
1106; CHECK-8M-NEXT:    vmov r0, s0
1107; CHECK-8M-NEXT:    uxth r0, r0
1108; CHECK-8M-NEXT:    vmov s0, r0
1109; CHECK-8M-NEXT:    pop.w {r7, lr}
1110; CHECK-8M-NEXT:    vmrs r12, fpscr
1111; CHECK-8M-NEXT:    vmov s1, lr
1112; CHECK-8M-NEXT:    vmov d1, lr, lr
1113; CHECK-8M-NEXT:    mov r0, lr
1114; CHECK-8M-NEXT:    vmov d2, lr, lr
1115; CHECK-8M-NEXT:    mov r1, lr
1116; CHECK-8M-NEXT:    vmov d3, lr, lr
1117; CHECK-8M-NEXT:    mov r2, lr
1118; CHECK-8M-NEXT:    vmov d4, lr, lr
1119; CHECK-8M-NEXT:    mov r3, lr
1120; CHECK-8M-NEXT:    vmov d5, lr, lr
1121; CHECK-8M-NEXT:    vmov d6, lr, lr
1122; CHECK-8M-NEXT:    vmov d7, lr, lr
1123; CHECK-8M-NEXT:    bic r12, r12, #159
1124; CHECK-8M-NEXT:    bic r12, r12, #4026531840
1125; CHECK-8M-NEXT:    vmsr fpscr, r12
1126; CHECK-8M-NEXT:    mov r12, lr
1127; CHECK-8M-NEXT:    msr apsr_nzcvqg, lr
1128; CHECK-8M-NEXT:    bxns lr
1129; CHECK-8M-NEXT:    .p2align 2
1130; CHECK-8M-NEXT:  @ %bb.1:
1131; CHECK-8M-NEXT:  .LCPI15_0:
1132; CHECK-8M-NEXT:    .long 0x00004900 @ float 2.61874657E-41
1133;
1134; CHECK-NO-MVE-LABEL: h1_minsize:
1135; CHECK-NO-MVE:       @ %bb.0: @ %entry
1136; CHECK-NO-MVE-NEXT:    vstr fpcxtns, [sp, #-4]!
1137; CHECK-NO-MVE-NEXT:    push {r6, r7, lr}
1138; CHECK-NO-MVE-NEXT:    vldr s0, .LCPI15_0
1139; CHECK-NO-MVE-NEXT:    blx r0
1140; CHECK-NO-MVE-NEXT:    vmov r0, s0
1141; CHECK-NO-MVE-NEXT:    uxth r0, r0
1142; CHECK-NO-MVE-NEXT:    vmov s0, r0
1143; CHECK-NO-MVE-NEXT:    pop.w {r3, r7, lr}
1144; CHECK-NO-MVE-NEXT:    vscclrm {s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, vpr}
1145; CHECK-NO-MVE-NEXT:    vldr fpcxtns, [sp], #4
1146; CHECK-NO-MVE-NEXT:    clrm {r0, r1, r2, r3, r12, apsr}
1147; CHECK-NO-MVE-NEXT:    bxns lr
1148; CHECK-NO-MVE-NEXT:    .p2align 2
1149; CHECK-NO-MVE-NEXT:  @ %bb.1:
1150; CHECK-NO-MVE-NEXT:  .LCPI15_0:
1151; CHECK-NO-MVE-NEXT:    .long 0x00004900 @ float 2.61874657E-41
1152;
1153; CHECK-MVE-LABEL: h1_minsize:
1154; CHECK-MVE:       @ %bb.0: @ %entry
1155; CHECK-MVE-NEXT:    vstr fpcxtns, [sp, #-4]!
1156; CHECK-MVE-NEXT:    push {r6, r7, lr}
1157; CHECK-MVE-NEXT:    vmov.f16 s0, #1.000000e+01
1158; CHECK-MVE-NEXT:    blx r0
1159; CHECK-MVE-NEXT:    vmov.f16 r0, s0
1160; CHECK-MVE-NEXT:    vmov s0, r0
1161; CHECK-MVE-NEXT:    pop.w {r3, r7, lr}
1162; CHECK-MVE-NEXT:    vscclrm {s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, vpr}
1163; CHECK-MVE-NEXT:    vldr fpcxtns, [sp], #4
1164; CHECK-MVE-NEXT:    clrm {r0, r1, r2, r3, r12, apsr}
1165; CHECK-MVE-NEXT:    bxns lr
1166entry:
1167  %call = call half %hptr(half 10.0) nounwind
1168  ret half %call
1169}
1170
1171define half @h1_arg(ptr nocapture %hptr, half %harg) nounwind {
1172; CHECK-8M-LABEL: h1_arg:
1173; CHECK-8M:       @ %bb.0: @ %entry
1174; CHECK-8M-NEXT:    push {r7, lr}
1175; CHECK-8M-NEXT:    vmov r1, s0
1176; CHECK-8M-NEXT:    uxth r1, r1
1177; CHECK-8M-NEXT:    vmov s0, r1
1178; CHECK-8M-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
1179; CHECK-8M-NEXT:    bic r0, r0, #1
1180; CHECK-8M-NEXT:    sub sp, #136
1181; CHECK-8M-NEXT:    vmov r12, s0
1182; CHECK-8M-NEXT:    vlstm sp, {d0 - d15}
1183; CHECK-8M-NEXT:    vmov s0, r12
1184; CHECK-8M-NEXT:    ldr r1, [sp, #64]
1185; CHECK-8M-NEXT:    bic r1, r1, #159
1186; CHECK-8M-NEXT:    bic r1, r1, #4026531840
1187; CHECK-8M-NEXT:    vmsr fpscr, r1
1188; CHECK-8M-NEXT:    mov r1, r0
1189; CHECK-8M-NEXT:    mov r2, r0
1190; CHECK-8M-NEXT:    mov r3, r0
1191; CHECK-8M-NEXT:    mov r4, r0
1192; CHECK-8M-NEXT:    mov r5, r0
1193; CHECK-8M-NEXT:    mov r6, r0
1194; CHECK-8M-NEXT:    mov r7, r0
1195; CHECK-8M-NEXT:    mov r8, r0
1196; CHECK-8M-NEXT:    mov r9, r0
1197; CHECK-8M-NEXT:    mov r10, r0
1198; CHECK-8M-NEXT:    mov r11, r0
1199; CHECK-8M-NEXT:    msr apsr_nzcvqg, r0
1200; CHECK-8M-NEXT:    blxns r0
1201; CHECK-8M-NEXT:    vmov r12, s0
1202; CHECK-8M-NEXT:    vlldm sp, {d0 - d15}
1203; CHECK-8M-NEXT:    vmov s0, r12
1204; CHECK-8M-NEXT:    add sp, #136
1205; CHECK-8M-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
1206; CHECK-8M-NEXT:    pop {r7, pc}
1207;
1208; CHECK-NO-MVE-LABEL: h1_arg:
1209; CHECK-NO-MVE:       @ %bb.0: @ %entry
1210; CHECK-NO-MVE-NEXT:    push {r7, lr}
1211; CHECK-NO-MVE-NEXT:    vmov r1, s0
1212; CHECK-NO-MVE-NEXT:    uxth r1, r1
1213; CHECK-NO-MVE-NEXT:    vmov s0, r1
1214; CHECK-NO-MVE-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
1215; CHECK-NO-MVE-NEXT:    bic r0, r0, #1
1216; CHECK-NO-MVE-NEXT:    vpush {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
1217; CHECK-NO-MVE-NEXT:    vscclrm {s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, vpr}
1218; CHECK-NO-MVE-NEXT:    vstr fpcxts, [sp, #-8]!
1219; CHECK-NO-MVE-NEXT:    clrm {r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, apsr}
1220; CHECK-NO-MVE-NEXT:    blxns r0
1221; CHECK-NO-MVE-NEXT:    vldr fpcxts, [sp], #8
1222; CHECK-NO-MVE-NEXT:    vpop {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
1223; CHECK-NO-MVE-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
1224; CHECK-NO-MVE-NEXT:    pop {r7, pc}
1225;
1226; CHECK-MVE-LABEL: h1_arg:
1227; CHECK-MVE:       @ %bb.0: @ %entry
1228; CHECK-MVE-NEXT:    push {r7, lr}
1229; CHECK-MVE-NEXT:    vmov.f16 r1, s0
1230; CHECK-MVE-NEXT:    vmov s0, r1
1231; CHECK-MVE-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
1232; CHECK-MVE-NEXT:    bic r0, r0, #1
1233; CHECK-MVE-NEXT:    vpush {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
1234; CHECK-MVE-NEXT:    vscclrm {s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, vpr}
1235; CHECK-MVE-NEXT:    vstr fpcxts, [sp, #-8]!
1236; CHECK-MVE-NEXT:    clrm {r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, apsr}
1237; CHECK-MVE-NEXT:    blxns r0
1238; CHECK-MVE-NEXT:    vldr fpcxts, [sp], #8
1239; CHECK-MVE-NEXT:    vpop {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
1240; CHECK-MVE-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
1241; CHECK-MVE-NEXT:    pop {r7, pc}
1242entry:
1243  %call = call half %hptr(half %harg) "cmse_nonsecure_call" nounwind
1244  ret half %call
1245}
1246
1247define float @float_return_undef_arg(ptr nocapture %fptr) #6 {
1248; CHECK-8M-LABEL: float_return_undef_arg:
1249; CHECK-8M:       @ %bb.0: @ %entry
1250; CHECK-8M-NEXT:    push {r7, lr}
1251; CHECK-8M-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
1252; CHECK-8M-NEXT:    bic r0, r0, #1
1253; CHECK-8M-NEXT:    sub sp, #136
1254; CHECK-8M-NEXT:    vmov.f32 s0, s0
1255; CHECK-8M-NEXT:    mov r1, r0
1256; CHECK-8M-NEXT:    vlstm sp, {d0 - d15}
1257; CHECK-8M-NEXT:    mov r2, r0
1258; CHECK-8M-NEXT:    mov r3, r0
1259; CHECK-8M-NEXT:    mov r4, r0
1260; CHECK-8M-NEXT:    mov r5, r0
1261; CHECK-8M-NEXT:    mov r6, r0
1262; CHECK-8M-NEXT:    mov r7, r0
1263; CHECK-8M-NEXT:    mov r8, r0
1264; CHECK-8M-NEXT:    mov r9, r0
1265; CHECK-8M-NEXT:    mov r10, r0
1266; CHECK-8M-NEXT:    mov r11, r0
1267; CHECK-8M-NEXT:    mov r12, r0
1268; CHECK-8M-NEXT:    msr apsr_nzcvqg, r0
1269; CHECK-8M-NEXT:    blxns r0
1270; CHECK-8M-NEXT:    vmov r12, s0
1271; CHECK-8M-NEXT:    vlldm sp, {d0 - d15}
1272; CHECK-8M-NEXT:    vmov s0, r12
1273; CHECK-8M-NEXT:    add sp, #136
1274; CHECK-8M-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
1275; CHECK-8M-NEXT:    pop {r7, pc}
1276;
1277; CHECK-81M-LABEL: float_return_undef_arg:
1278; CHECK-81M:       @ %bb.0: @ %entry
1279; CHECK-81M-NEXT:    push {r7, lr}
1280; CHECK-81M-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
1281; CHECK-81M-NEXT:    bic r0, r0, #1
1282; CHECK-81M-NEXT:    vpush {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
1283; CHECK-81M-NEXT:    vscclrm {s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, vpr}
1284; CHECK-81M-NEXT:    vstr fpcxts, [sp, #-8]!
1285; CHECK-81M-NEXT:    clrm {r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, apsr}
1286; CHECK-81M-NEXT:    blxns r0
1287; CHECK-81M-NEXT:    vldr fpcxts, [sp], #8
1288; CHECK-81M-NEXT:    vpop {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
1289; CHECK-81M-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
1290; CHECK-81M-NEXT:    pop {r7, pc}
1291entry:
1292  %call = call float %fptr(i32 undef) #7
1293  ret float %call
1294}
1295
1296define float @float_return_poison_arg(ptr nocapture %fptr) #6 {
1297; CHECK-8M-LABEL: float_return_poison_arg:
1298; CHECK-8M:       @ %bb.0: @ %entry
1299; CHECK-8M-NEXT:    push {r7, lr}
1300; CHECK-8M-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
1301; CHECK-8M-NEXT:    bic r0, r0, #1
1302; CHECK-8M-NEXT:    sub sp, #136
1303; CHECK-8M-NEXT:    vmov.f32 s0, s0
1304; CHECK-8M-NEXT:    mov r1, r0
1305; CHECK-8M-NEXT:    vlstm sp, {d0 - d15}
1306; CHECK-8M-NEXT:    mov r2, r0
1307; CHECK-8M-NEXT:    mov r3, r0
1308; CHECK-8M-NEXT:    mov r4, r0
1309; CHECK-8M-NEXT:    mov r5, r0
1310; CHECK-8M-NEXT:    mov r6, r0
1311; CHECK-8M-NEXT:    mov r7, r0
1312; CHECK-8M-NEXT:    mov r8, r0
1313; CHECK-8M-NEXT:    mov r9, r0
1314; CHECK-8M-NEXT:    mov r10, r0
1315; CHECK-8M-NEXT:    mov r11, r0
1316; CHECK-8M-NEXT:    mov r12, r0
1317; CHECK-8M-NEXT:    msr apsr_nzcvqg, r0
1318; CHECK-8M-NEXT:    blxns r0
1319; CHECK-8M-NEXT:    vmov r12, s0
1320; CHECK-8M-NEXT:    vlldm sp, {d0 - d15}
1321; CHECK-8M-NEXT:    vmov s0, r12
1322; CHECK-8M-NEXT:    add sp, #136
1323; CHECK-8M-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
1324; CHECK-8M-NEXT:    pop {r7, pc}
1325;
1326; CHECK-81M-LABEL: float_return_poison_arg:
1327; CHECK-81M:       @ %bb.0: @ %entry
1328; CHECK-81M-NEXT:    push {r7, lr}
1329; CHECK-81M-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
1330; CHECK-81M-NEXT:    bic r0, r0, #1
1331; CHECK-81M-NEXT:    vpush {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
1332; CHECK-81M-NEXT:    vscclrm {s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, vpr}
1333; CHECK-81M-NEXT:    vstr fpcxts, [sp, #-8]!
1334; CHECK-81M-NEXT:    clrm {r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, apsr}
1335; CHECK-81M-NEXT:    blxns r0
1336; CHECK-81M-NEXT:    vldr fpcxts, [sp], #8
1337; CHECK-81M-NEXT:    vpop {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
1338; CHECK-81M-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
1339; CHECK-81M-NEXT:    pop {r7, pc}
1340entry:
1341  %call = call float %fptr(i32 poison) #7
1342  ret float %call
1343}
1344