xref: /llvm-project/llvm/test/CodeGen/ARM/atomic-load-store.ll (revision 4a2bd78f5b0d0661c23dff9c4b93a393a49dbf9a) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s -check-prefixes=ARM
3; RUN: llc < %s -mtriple=armv7-apple-ios -O0 | FileCheck %s -check-prefix=ARMOPTNONE
4; RUN: llc < %s -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s -check-prefix=THUMBTWO
5; RUN: llc < %s -mtriple=thumbv6 | FileCheck %s -check-prefix=THUMBONE
6; RUN: llc < %s -mtriple=armv4 | FileCheck %s -check-prefix=ARMV4
7; RUN: llc < %s -mtriple=armv6 | FileCheck %s -check-prefix=ARMV6
8; RUN: llc < %s -mtriple=thumbv7m | FileCheck %s -check-prefix=THUMBM
9
10define void @test1(ptr %ptr, i32 %val1) {
11; ARM-LABEL: test1:
12; ARM:       @ %bb.0:
13; ARM-NEXT:    dmb ish
14; ARM-NEXT:    str r1, [r0]
15; ARM-NEXT:    dmb ish
16; ARM-NEXT:    bx lr
17;
18; ARMOPTNONE-LABEL: test1:
19; ARMOPTNONE:       @ %bb.0:
20; ARMOPTNONE-NEXT:    dmb ish
21; ARMOPTNONE-NEXT:    str r1, [r0]
22; ARMOPTNONE-NEXT:    dmb ish
23; ARMOPTNONE-NEXT:    bx lr
24;
25; THUMBTWO-LABEL: test1:
26; THUMBTWO:       @ %bb.0:
27; THUMBTWO-NEXT:    dmb ish
28; THUMBTWO-NEXT:    str r1, [r0]
29; THUMBTWO-NEXT:    dmb ish
30; THUMBTWO-NEXT:    bx lr
31;
32; THUMBONE-LABEL: test1:
33; THUMBONE:       @ %bb.0:
34; THUMBONE-NEXT:    push {r7, lr}
35; THUMBONE-NEXT:    bl __sync_lock_test_and_set_4
36; THUMBONE-NEXT:    pop {r7, pc}
37;
38; ARMV4-LABEL: test1:
39; ARMV4:       @ %bb.0:
40; ARMV4-NEXT:    push {r11, lr}
41; ARMV4-NEXT:    mov r2, #5
42; ARMV4-NEXT:    bl __atomic_store_4
43; ARMV4-NEXT:    pop {r11, lr}
44; ARMV4-NEXT:    mov pc, lr
45;
46; ARMV6-LABEL: test1:
47; ARMV6:       @ %bb.0:
48; ARMV6-NEXT:    mov r2, #0
49; ARMV6-NEXT:    mcr p15, #0, r2, c7, c10, #5
50; ARMV6-NEXT:    str r1, [r0]
51; ARMV6-NEXT:    mcr p15, #0, r2, c7, c10, #5
52; ARMV6-NEXT:    bx lr
53;
54; THUMBM-LABEL: test1:
55; THUMBM:       @ %bb.0:
56; THUMBM-NEXT:    dmb sy
57; THUMBM-NEXT:    str r1, [r0]
58; THUMBM-NEXT:    dmb sy
59; THUMBM-NEXT:    bx lr
60  store atomic i32 %val1, ptr %ptr seq_cst, align 4
61  ret void
62}
63
64define i32 @test2(ptr %ptr) {
65; ARM-LABEL: test2:
66; ARM:       @ %bb.0:
67; ARM-NEXT:    ldr r0, [r0]
68; ARM-NEXT:    dmb ish
69; ARM-NEXT:    bx lr
70;
71; ARMOPTNONE-LABEL: test2:
72; ARMOPTNONE:       @ %bb.0:
73; ARMOPTNONE-NEXT:    ldr r0, [r0]
74; ARMOPTNONE-NEXT:    dmb ish
75; ARMOPTNONE-NEXT:    bx lr
76;
77; THUMBTWO-LABEL: test2:
78; THUMBTWO:       @ %bb.0:
79; THUMBTWO-NEXT:    ldr r0, [r0]
80; THUMBTWO-NEXT:    dmb ish
81; THUMBTWO-NEXT:    bx lr
82;
83; THUMBONE-LABEL: test2:
84; THUMBONE:       @ %bb.0:
85; THUMBONE-NEXT:    push {r7, lr}
86; THUMBONE-NEXT:    movs r1, #0
87; THUMBONE-NEXT:    mov r2, r1
88; THUMBONE-NEXT:    bl __sync_val_compare_and_swap_4
89; THUMBONE-NEXT:    pop {r7, pc}
90;
91; ARMV4-LABEL: test2:
92; ARMV4:       @ %bb.0:
93; ARMV4-NEXT:    push {r11, lr}
94; ARMV4-NEXT:    mov r1, #5
95; ARMV4-NEXT:    bl __atomic_load_4
96; ARMV4-NEXT:    pop {r11, lr}
97; ARMV4-NEXT:    mov pc, lr
98;
99; ARMV6-LABEL: test2:
100; ARMV6:       @ %bb.0:
101; ARMV6-NEXT:    ldr r0, [r0]
102; ARMV6-NEXT:    mov r1, #0
103; ARMV6-NEXT:    mcr p15, #0, r1, c7, c10, #5
104; ARMV6-NEXT:    bx lr
105;
106; THUMBM-LABEL: test2:
107; THUMBM:       @ %bb.0:
108; THUMBM-NEXT:    ldr r0, [r0]
109; THUMBM-NEXT:    dmb sy
110; THUMBM-NEXT:    bx lr
111  %val = load atomic i32, ptr %ptr seq_cst, align 4
112  ret i32 %val
113}
114
115define void @test3(ptr %ptr1, ptr %ptr2) {
116; ARM-LABEL: test3:
117; ARM:       @ %bb.0:
118; ARM-NEXT:    ldrb r0, [r0]
119; ARM-NEXT:    strb r0, [r1]
120; ARM-NEXT:    bx lr
121;
122; ARMOPTNONE-LABEL: test3:
123; ARMOPTNONE:       @ %bb.0:
124; ARMOPTNONE-NEXT:    ldrb r0, [r0]
125; ARMOPTNONE-NEXT:    strb r0, [r1]
126; ARMOPTNONE-NEXT:    bx lr
127;
128; THUMBTWO-LABEL: test3:
129; THUMBTWO:       @ %bb.0:
130; THUMBTWO-NEXT:    ldrb r0, [r0]
131; THUMBTWO-NEXT:    strb r0, [r1]
132; THUMBTWO-NEXT:    bx lr
133;
134; THUMBONE-LABEL: test3:
135; THUMBONE:       @ %bb.0:
136; THUMBONE-NEXT:    ldrb r0, [r0]
137; THUMBONE-NEXT:    strb r0, [r1]
138; THUMBONE-NEXT:    bx lr
139;
140; ARMV4-LABEL: test3:
141; ARMV4:       @ %bb.0:
142; ARMV4-NEXT:    push {r4, lr}
143; ARMV4-NEXT:    mov r4, r1
144; ARMV4-NEXT:    mov r1, #0
145; ARMV4-NEXT:    bl __atomic_load_1
146; ARMV4-NEXT:    mov r1, r0
147; ARMV4-NEXT:    mov r0, r4
148; ARMV4-NEXT:    mov r2, #0
149; ARMV4-NEXT:    bl __atomic_store_1
150; ARMV4-NEXT:    pop {r4, lr}
151; ARMV4-NEXT:    mov pc, lr
152;
153; ARMV6-LABEL: test3:
154; ARMV6:       @ %bb.0:
155; ARMV6-NEXT:    ldrb r0, [r0]
156; ARMV6-NEXT:    strb r0, [r1]
157; ARMV6-NEXT:    bx lr
158;
159; THUMBM-LABEL: test3:
160; THUMBM:       @ %bb.0:
161; THUMBM-NEXT:    ldrb r0, [r0]
162; THUMBM-NEXT:    strb r0, [r1]
163; THUMBM-NEXT:    bx lr
164
165
166
167  %val = load atomic i8, ptr %ptr1 unordered, align 1
168  store atomic i8 %val, ptr %ptr2 unordered, align 1
169  ret void
170}
171
172define void @test4(ptr %ptr1, ptr %ptr2) {
173; ARM-LABEL: test4:
174; ARM:       @ %bb.0:
175; ARM-NEXT:    ldrb r0, [r0]
176; ARM-NEXT:    dmb ish
177; ARM-NEXT:    strb r0, [r1]
178; ARM-NEXT:    dmb ish
179; ARM-NEXT:    bx lr
180;
181; ARMOPTNONE-LABEL: test4:
182; ARMOPTNONE:       @ %bb.0:
183; ARMOPTNONE-NEXT:    ldrb r0, [r0]
184; ARMOPTNONE-NEXT:    dmb ish
185; ARMOPTNONE-NEXT:    dmb ish
186; ARMOPTNONE-NEXT:    strb r0, [r1]
187; ARMOPTNONE-NEXT:    dmb ish
188; ARMOPTNONE-NEXT:    bx lr
189;
190; THUMBTWO-LABEL: test4:
191; THUMBTWO:       @ %bb.0:
192; THUMBTWO-NEXT:    ldrb r0, [r0]
193; THUMBTWO-NEXT:    dmb ish
194; THUMBTWO-NEXT:    dmb ish
195; THUMBTWO-NEXT:    strb r0, [r1]
196; THUMBTWO-NEXT:    dmb ish
197; THUMBTWO-NEXT:    bx lr
198;
199; THUMBONE-LABEL: test4:
200; THUMBONE:       @ %bb.0:
201; THUMBONE-NEXT:    push {r4, lr}
202; THUMBONE-NEXT:    mov r4, r1
203; THUMBONE-NEXT:    movs r1, #0
204; THUMBONE-NEXT:    mov r2, r1
205; THUMBONE-NEXT:    bl __sync_val_compare_and_swap_1
206; THUMBONE-NEXT:    mov r1, r0
207; THUMBONE-NEXT:    mov r0, r4
208; THUMBONE-NEXT:    bl __sync_lock_test_and_set_1
209; THUMBONE-NEXT:    pop {r4, pc}
210;
211; ARMV4-LABEL: test4:
212; ARMV4:       @ %bb.0:
213; ARMV4-NEXT:    push {r4, lr}
214; ARMV4-NEXT:    mov r4, r1
215; ARMV4-NEXT:    mov r1, #5
216; ARMV4-NEXT:    bl __atomic_load_1
217; ARMV4-NEXT:    mov r1, r0
218; ARMV4-NEXT:    mov r0, r4
219; ARMV4-NEXT:    mov r2, #5
220; ARMV4-NEXT:    bl __atomic_store_1
221; ARMV4-NEXT:    pop {r4, lr}
222; ARMV4-NEXT:    mov pc, lr
223;
224; ARMV6-LABEL: test4:
225; ARMV6:       @ %bb.0:
226; ARMV6-NEXT:    mov r2, #0
227; ARMV6-NEXT:    ldrb r0, [r0]
228; ARMV6-NEXT:    mcr p15, #0, r2, c7, c10, #5
229; ARMV6-NEXT:    mcr p15, #0, r2, c7, c10, #5
230; ARMV6-NEXT:    strb r0, [r1]
231; ARMV6-NEXT:    mcr p15, #0, r2, c7, c10, #5
232; ARMV6-NEXT:    bx lr
233;
234; THUMBM-LABEL: test4:
235; THUMBM:       @ %bb.0:
236; THUMBM-NEXT:    ldrb r0, [r0]
237; THUMBM-NEXT:    dmb sy
238; THUMBM-NEXT:    dmb sy
239; THUMBM-NEXT:    strb r0, [r1]
240; THUMBM-NEXT:    dmb sy
241; THUMBM-NEXT:    bx lr
242  %val = load atomic i8, ptr %ptr1 seq_cst, align 1
243  store atomic i8 %val, ptr %ptr2 seq_cst, align 1
244  ret void
245}
246
247define i64 @test_old_load_64bit(ptr %p) {
248; ARM-LABEL: test_old_load_64bit:
249; ARM:       @ %bb.0:
250; ARM-NEXT:    ldrexd r0, r1, [r0]
251; ARM-NEXT:    clrex
252; ARM-NEXT:    dmb ish
253; ARM-NEXT:    bx lr
254;
255; ARMOPTNONE-LABEL: test_old_load_64bit:
256; ARMOPTNONE:       @ %bb.0:
257; ARMOPTNONE-NEXT:    ldrexd r2, r3, [r0]
258; ARMOPTNONE-NEXT:    mov r0, r2
259; ARMOPTNONE-NEXT:    mov r1, r3
260; ARMOPTNONE-NEXT:    clrex
261; ARMOPTNONE-NEXT:    dmb ish
262; ARMOPTNONE-NEXT:    bx lr
263;
264; THUMBTWO-LABEL: test_old_load_64bit:
265; THUMBTWO:       @ %bb.0:
266; THUMBTWO-NEXT:    ldrexd r0, r1, [r0]
267; THUMBTWO-NEXT:    clrex
268; THUMBTWO-NEXT:    dmb ish
269; THUMBTWO-NEXT:    bx lr
270;
271; THUMBONE-LABEL: test_old_load_64bit:
272; THUMBONE:       @ %bb.0:
273; THUMBONE-NEXT:    push {r7, lr}
274; THUMBONE-NEXT:    sub sp, #8
275; THUMBONE-NEXT:    movs r2, #0
276; THUMBONE-NEXT:    str r2, [sp]
277; THUMBONE-NEXT:    str r2, [sp, #4]
278; THUMBONE-NEXT:    mov r3, r2
279; THUMBONE-NEXT:    bl __sync_val_compare_and_swap_8
280; THUMBONE-NEXT:    add sp, #8
281; THUMBONE-NEXT:    pop {r7, pc}
282;
283; ARMV4-LABEL: test_old_load_64bit:
284; ARMV4:       @ %bb.0:
285; ARMV4-NEXT:    push {r11, lr}
286; ARMV4-NEXT:    mov r1, #5
287; ARMV4-NEXT:    bl __atomic_load_8
288; ARMV4-NEXT:    pop {r11, lr}
289; ARMV4-NEXT:    mov pc, lr
290;
291; ARMV6-LABEL: test_old_load_64bit:
292; ARMV6:       @ %bb.0:
293; ARMV6-NEXT:    ldrexd r0, r1, [r0]
294; ARMV6-NEXT:    mov r2, #0
295; ARMV6-NEXT:    mcr p15, #0, r2, c7, c10, #5
296; ARMV6-NEXT:    bx lr
297;
298; THUMBM-LABEL: test_old_load_64bit:
299; THUMBM:       @ %bb.0:
300; THUMBM-NEXT:    push {r7, lr}
301; THUMBM-NEXT:    movs r1, #5
302; THUMBM-NEXT:    bl __atomic_load_8
303; THUMBM-NEXT:    pop {r7, pc}
304  %1 = load atomic i64, ptr %p seq_cst, align 8
305  ret i64 %1
306}
307
308define void @test_old_store_64bit(ptr %p, i64 %v) {
309; ARM-LABEL: test_old_store_64bit:
310; ARM:       @ %bb.0:
311; ARM-NEXT:    push {r4, r5, lr}
312; ARM-NEXT:    mov r3, r2
313; ARM-NEXT:    dmb ish
314; ARM-NEXT:    mov r2, r1
315; ARM-NEXT:  LBB5_1: @ %atomicrmw.start
316; ARM-NEXT:    @ =>This Inner Loop Header: Depth=1
317; ARM-NEXT:    ldrexd r4, r5, [r0]
318; ARM-NEXT:    strexd r1, r2, r3, [r0]
319; ARM-NEXT:    cmp r1, #0
320; ARM-NEXT:    bne LBB5_1
321; ARM-NEXT:  @ %bb.2: @ %atomicrmw.end
322; ARM-NEXT:    dmb ish
323; ARM-NEXT:    pop {r4, r5, pc}
324;
325; ARMOPTNONE-LABEL: test_old_store_64bit:
326; ARMOPTNONE:       @ %bb.0:
327; ARMOPTNONE-NEXT:    push	{r4, r5, r7, r8, r10, r11, lr}
328; ARMOPTNONE-NEXT:    add	r7, sp, #20
329; ARMOPTNONE-NEXT:    sub	sp, sp, #24
330; ARMOPTNONE-NEXT:    str	r0, [sp, #4] @ 4-byte Spill
331; ARMOPTNONE-NEXT:    str	r2, [sp, #8] @ 4-byte Spill
332; ARMOPTNONE-NEXT:    str	r1, [sp, #12] @ 4-byte Spill
333; ARMOPTNONE-NEXT:    dmb	ish
334; ARMOPTNONE-NEXT:    ldr	r1, [r0]
335; ARMOPTNONE-NEXT:    ldr	r0, [r0, #4]
336; ARMOPTNONE-NEXT:    str	r1, [sp, #16] @ 4-byte Spill
337; ARMOPTNONE-NEXT:    str	r0, [sp, #20] @ 4-byte Spill
338; ARMOPTNONE-NEXT:    b LBB5_1
339; ARMOPTNONE-NEXT:  LBB5_1: @ %atomicrmw.start
340; ARMOPTNONE-NEXT:    @ =>This Loop Header: Depth=1
341; ARMOPTNONE-NEXT:    @ Child Loop BB5_2 Depth 2
342; ARMOPTNONE-NEXT:    ldr r3, [sp, #20] @ 4-byte Reload
343; ARMOPTNONE-NEXT:    ldr r2, [sp, #16] @ 4-byte Reload
344; ARMOPTNONE-NEXT:    ldr r12, [sp, #8] @ 4-byte Reload
345; ARMOPTNONE-NEXT:    ldr r0, [sp, #12] @ 4-byte Reload
346; ARMOPTNONE-NEXT:    ldr r8, [sp, #4] @ 4-byte Reload
347; ARMOPTNONE-NEXT:    str r3, [sp] @ 4-byte Spill
348; ARMOPTNONE-NEXT:    @ implicit-def: $r1
349; ARMOPTNONE-NEXT:    @ implicit-def: $r9
350; ARMOPTNONE-NEXT:    @ kill: def $r8 killed $r8 def $r8_r9
351; ARMOPTNONE-NEXT:    mov r9, r1
352; ARMOPTNONE-NEXT:    @ kill: def $r0 killed $r0 def $r0_r1
353; ARMOPTNONE-NEXT:    mov r1, r12
354; ARMOPTNONE-NEXT:    mov r10, r2
355; ARMOPTNONE-NEXT:    mov r11, r3
356; ARMOPTNONE-NEXT:  LBB5_2: @ %atomicrmw.start
357; ARMOPTNONE-NEXT:    @ Parent Loop BB5_1 Depth=1
358; ARMOPTNONE-NEXT:    @ => This Inner Loop Header: Depth=2
359; ARMOPTNONE-NEXT:    ldrexd r4, r5, [r8]
360; ARMOPTNONE-NEXT:    cmp r4, r10
361; ARMOPTNONE-NEXT:    cmpeq r5, r11
362; ARMOPTNONE-NEXT:    bne LBB5_4
363; ARMOPTNONE-NEXT:  @ %bb.3: @ %atomicrmw.start
364; ARMOPTNONE-NEXT:    @ in Loop: Header=BB5_2 Depth=2
365; ARMOPTNONE-NEXT:    strexd r9, r0, r1, [r8]
366; ARMOPTNONE-NEXT:    cmp r9, #0
367; ARMOPTNONE-NEXT:    bne LBB5_2
368; ARMOPTNONE-NEXT:  LBB5_4: @ %atomicrmw.start
369; ARMOPTNONE-NEXT:    @ in Loop: Header=BB5_1 Depth=1
370; ARMOPTNONE-NEXT:    ldr r1, [sp] @ 4-byte Reload
371; ARMOPTNONE-NEXT:    mov r0, r5
372; ARMOPTNONE-NEXT:    eor r3, r0, r1
373; ARMOPTNONE-NEXT:    mov r1, r4
374; ARMOPTNONE-NEXT:    eor r2, r1, r2
375; ARMOPTNONE-NEXT:    orr r2, r2, r3
376; ARMOPTNONE-NEXT:    cmp r2, #0
377; ARMOPTNONE-NEXT:    str r1, [sp, #16] @ 4-byte Spill
378; ARMOPTNONE-NEXT:    str r0, [sp, #20] @ 4-byte Spill
379; ARMOPTNONE-NEXT:    bne LBB5_1
380; ARMOPTNONE-NEXT:    b LBB5_5
381; ARMOPTNONE-NEXT:  LBB5_5: @ %atomicrmw.end
382; ARMOPTNONE-NEXT:    dmb ish
383; ARMOPTNONE-NEXT:    sub sp, r7, #20
384; ARMOPTNONE-NEXT:    pop	{r4, r5, r7, r8, r10, r11, pc}
385;
386; THUMBTWO-LABEL: test_old_store_64bit:
387; THUMBTWO:       @ %bb.0:
388; THUMBTWO-NEXT:    dmb ish
389; THUMBTWO-NEXT:  LBB5_1: @ %atomicrmw.start
390; THUMBTWO-NEXT:    @ =>This Inner Loop Header: Depth=1
391; THUMBTWO-NEXT:    ldrexd r3, r9, [r0]
392; THUMBTWO-NEXT:    strexd r3, r1, r2, [r0]
393; THUMBTWO-NEXT:    cmp r3, #0
394; THUMBTWO-NEXT:    bne LBB5_1
395; THUMBTWO-NEXT:  @ %bb.2: @ %atomicrmw.end
396; THUMBTWO-NEXT:    dmb ish
397; THUMBTWO-NEXT:    bx lr
398;
399; THUMBONE-LABEL: test_old_store_64bit:
400; THUMBONE:       @ %bb.0:
401; THUMBONE-NEXT:    push {r7, lr}
402; THUMBONE-NEXT:    bl __sync_lock_test_and_set_8
403; THUMBONE-NEXT:    pop {r7, pc}
404;
405; ARMV4-LABEL: test_old_store_64bit:
406; ARMV4:       @ %bb.0:
407; ARMV4-NEXT:    push {r11, lr}
408; ARMV4-NEXT:    sub sp, sp, #8
409; ARMV4-NEXT:    mov r1, #5
410; ARMV4-NEXT:    str r1, [sp]
411; ARMV4-NEXT:    bl __atomic_store_8
412; ARMV4-NEXT:    add sp, sp, #8
413; ARMV4-NEXT:    pop {r11, lr}
414; ARMV4-NEXT:    mov pc, lr
415;
416; ARMV6-LABEL: test_old_store_64bit:
417; ARMV6:       @ %bb.0:
418; ARMV6-NEXT:    push {r4, r5, r11, lr}
419; ARMV6-NEXT:    @ kill: def $r3 killed $r3 killed $r2_r3 def $r2_r3
420; ARMV6-NEXT:    mov r1, #0
421; ARMV6-NEXT:    @ kill: def $r2 killed $r2 killed $r2_r3 def $r2_r3
422; ARMV6-NEXT:    mcr p15, #0, r1, c7, c10, #5
423; ARMV6-NEXT:  .LBB5_1: @ %atomicrmw.start
424; ARMV6-NEXT:    @ =>This Inner Loop Header: Depth=1
425; ARMV6-NEXT:    ldrexd r4, r5, [r0]
426; ARMV6-NEXT:    strexd r1, r2, r3, [r0]
427; ARMV6-NEXT:    cmp r1, #0
428; ARMV6-NEXT:    bne .LBB5_1
429; ARMV6-NEXT:  @ %bb.2: @ %atomicrmw.end
430; ARMV6-NEXT:    mov r0, #0
431; ARMV6-NEXT:    mcr p15, #0, r0, c7, c10, #5
432; ARMV6-NEXT:    pop {r4, r5, r11, pc}
433;
434; THUMBM-LABEL: test_old_store_64bit:
435; THUMBM:       @ %bb.0:
436; THUMBM-NEXT:    push {r7, lr}
437; THUMBM-NEXT:    sub sp, #8
438; THUMBM-NEXT:    movs r1, #5
439; THUMBM-NEXT:    str r1, [sp]
440; THUMBM-NEXT:    bl __atomic_store_8
441; THUMBM-NEXT:    add sp, #8
442; THUMBM-NEXT:    pop {r7, pc}
443  store atomic i64 %v, ptr %p seq_cst, align 8
444  ret void
445}
446
447define half @load_atomic_f16__seq_cst(ptr %ptr) {
448; ARM-LABEL: load_atomic_f16__seq_cst:
449; ARM:       @ %bb.0:
450; ARM-NEXT:    ldrh r0, [r0]
451; ARM-NEXT:    dmb ish
452; ARM-NEXT:    bx lr
453;
454; ARMOPTNONE-LABEL: load_atomic_f16__seq_cst:
455; ARMOPTNONE:       @ %bb.0:
456; ARMOPTNONE-NEXT:    ldrh r0, [r0]
457; ARMOPTNONE-NEXT:    dmb ish
458; ARMOPTNONE-NEXT:    bx lr
459;
460; THUMBTWO-LABEL: load_atomic_f16__seq_cst:
461; THUMBTWO:       @ %bb.0:
462; THUMBTWO-NEXT:    ldrh r0, [r0]
463; THUMBTWO-NEXT:    dmb ish
464; THUMBTWO-NEXT:    bx lr
465;
466; THUMBONE-LABEL: load_atomic_f16__seq_cst:
467; THUMBONE:       @ %bb.0:
468; THUMBONE-NEXT:    push {r7, lr}
469; THUMBONE-NEXT:    movs r1, #0
470; THUMBONE-NEXT:    mov r2, r1
471; THUMBONE-NEXT:    bl __sync_val_compare_and_swap_2
472; THUMBONE-NEXT:    pop {r7, pc}
473;
474; ARMV4-LABEL: load_atomic_f16__seq_cst:
475; ARMV4:       @ %bb.0:
476; ARMV4-NEXT:    push {r11, lr}
477; ARMV4-NEXT:    mov r1, #5
478; ARMV4-NEXT:    bl __atomic_load_2
479; ARMV4-NEXT:    pop {r11, lr}
480; ARMV4-NEXT:    mov pc, lr
481;
482; ARMV6-LABEL: load_atomic_f16__seq_cst:
483; ARMV6:       @ %bb.0:
484; ARMV6-NEXT:    ldrh r0, [r0]
485; ARMV6-NEXT:    mov r1, #0
486; ARMV6-NEXT:    mcr p15, #0, r1, c7, c10, #5
487; ARMV6-NEXT:    bx lr
488;
489; THUMBM-LABEL: load_atomic_f16__seq_cst:
490; THUMBM:       @ %bb.0:
491; THUMBM-NEXT:    ldrh r0, [r0]
492; THUMBM-NEXT:    dmb sy
493; THUMBM-NEXT:    bx lr
494  %val = load atomic half, ptr %ptr seq_cst, align 2
495  ret half %val
496}
497
498define bfloat @load_atomic_bf16__seq_cst(ptr %ptr) {
499; ARM-LABEL: load_atomic_bf16__seq_cst:
500; ARM:       @ %bb.0:
501; ARM-NEXT:    ldrh r0, [r0]
502; ARM-NEXT:    dmb ish
503; ARM-NEXT:    bx lr
504;
505; ARMOPTNONE-LABEL: load_atomic_bf16__seq_cst:
506; ARMOPTNONE:       @ %bb.0:
507; ARMOPTNONE-NEXT:    ldrh r0, [r0]
508; ARMOPTNONE-NEXT:    dmb ish
509; ARMOPTNONE-NEXT:    bx lr
510;
511; THUMBTWO-LABEL: load_atomic_bf16__seq_cst:
512; THUMBTWO:       @ %bb.0:
513; THUMBTWO-NEXT:    ldrh r0, [r0]
514; THUMBTWO-NEXT:    dmb ish
515; THUMBTWO-NEXT:    bx lr
516;
517; THUMBONE-LABEL: load_atomic_bf16__seq_cst:
518; THUMBONE:       @ %bb.0:
519; THUMBONE-NEXT:    push {r7, lr}
520; THUMBONE-NEXT:    movs r1, #0
521; THUMBONE-NEXT:    mov r2, r1
522; THUMBONE-NEXT:    bl __sync_val_compare_and_swap_2
523; THUMBONE-NEXT:    pop {r7, pc}
524;
525; ARMV4-LABEL: load_atomic_bf16__seq_cst:
526; ARMV4:       @ %bb.0:
527; ARMV4-NEXT:    push {r11, lr}
528; ARMV4-NEXT:    mov r1, #5
529; ARMV4-NEXT:    bl __atomic_load_2
530; ARMV4-NEXT:    pop {r11, lr}
531; ARMV4-NEXT:    mov pc, lr
532;
533; ARMV6-LABEL: load_atomic_bf16__seq_cst:
534; ARMV6:       @ %bb.0:
535; ARMV6-NEXT:    ldrh r0, [r0]
536; ARMV6-NEXT:    mov r1, #0
537; ARMV6-NEXT:    mcr p15, #0, r1, c7, c10, #5
538; ARMV6-NEXT:    bx lr
539;
540; THUMBM-LABEL: load_atomic_bf16__seq_cst:
541; THUMBM:       @ %bb.0:
542; THUMBM-NEXT:    ldrh r0, [r0]
543; THUMBM-NEXT:    dmb sy
544; THUMBM-NEXT:    bx lr
545  %val = load atomic bfloat, ptr %ptr seq_cst, align 2
546  ret bfloat %val
547}
548
549define float @load_atomic_f32__seq_cst(ptr %ptr) {
550; ARM-LABEL: load_atomic_f32__seq_cst:
551; ARM:       @ %bb.0:
552; ARM-NEXT:    ldr r0, [r0]
553; ARM-NEXT:    dmb ish
554; ARM-NEXT:    bx lr
555;
556; ARMOPTNONE-LABEL: load_atomic_f32__seq_cst:
557; ARMOPTNONE:       @ %bb.0:
558; ARMOPTNONE-NEXT:    ldr r0, [r0]
559; ARMOPTNONE-NEXT:    dmb ish
560; ARMOPTNONE-NEXT:    vmov s0, r0
561; ARMOPTNONE-NEXT:    bx lr
562;
563; THUMBTWO-LABEL: load_atomic_f32__seq_cst:
564; THUMBTWO:       @ %bb.0:
565; THUMBTWO-NEXT:    ldr r0, [r0]
566; THUMBTWO-NEXT:    dmb ish
567; THUMBTWO-NEXT:    bx lr
568;
569; THUMBONE-LABEL: load_atomic_f32__seq_cst:
570; THUMBONE:       @ %bb.0:
571; THUMBONE-NEXT:    push {r7, lr}
572; THUMBONE-NEXT:    movs r1, #0
573; THUMBONE-NEXT:    mov r2, r1
574; THUMBONE-NEXT:    bl __sync_val_compare_and_swap_4
575; THUMBONE-NEXT:    pop {r7, pc}
576;
577; ARMV4-LABEL: load_atomic_f32__seq_cst:
578; ARMV4:       @ %bb.0:
579; ARMV4-NEXT:    push {r11, lr}
580; ARMV4-NEXT:    mov r1, #5
581; ARMV4-NEXT:    bl __atomic_load_4
582; ARMV4-NEXT:    pop {r11, lr}
583; ARMV4-NEXT:    mov pc, lr
584;
585; ARMV6-LABEL: load_atomic_f32__seq_cst:
586; ARMV6:       @ %bb.0:
587; ARMV6-NEXT:    ldr r0, [r0]
588; ARMV6-NEXT:    mov r1, #0
589; ARMV6-NEXT:    mcr p15, #0, r1, c7, c10, #5
590; ARMV6-NEXT:    bx lr
591;
592; THUMBM-LABEL: load_atomic_f32__seq_cst:
593; THUMBM:       @ %bb.0:
594; THUMBM-NEXT:    ldr r0, [r0]
595; THUMBM-NEXT:    dmb sy
596; THUMBM-NEXT:    bx lr
597  %val = load atomic float, ptr %ptr seq_cst, align 4
598  ret float %val
599}
600
601define double @load_atomic_f64__seq_cst(ptr %ptr) {
602; ARM-LABEL: load_atomic_f64__seq_cst:
603; ARM:       @ %bb.0:
604; ARM-NEXT:    ldrexd r0, r1, [r0]
605; ARM-NEXT:    clrex
606; ARM-NEXT:    dmb ish
607; ARM-NEXT:    bx lr
608;
609; ARMOPTNONE-LABEL: load_atomic_f64__seq_cst:
610; ARMOPTNONE:       @ %bb.0:
611; ARMOPTNONE-NEXT:    ldrexd r2, r3, [r0]
612; ARMOPTNONE-NEXT:    mov r1, r3
613; ARMOPTNONE-NEXT:    mov r0, r2
614; ARMOPTNONE-NEXT:    clrex
615; ARMOPTNONE-NEXT:    dmb ish
616; ARMOPTNONE-NEXT:    vmov d16, r0, r1
617; ARMOPTNONE-NEXT:    bx lr
618;
619; THUMBTWO-LABEL: load_atomic_f64__seq_cst:
620; THUMBTWO:       @ %bb.0:
621; THUMBTWO-NEXT:    ldrexd r0, r1, [r0]
622; THUMBTWO-NEXT:    clrex
623; THUMBTWO-NEXT:    dmb ish
624; THUMBTWO-NEXT:    bx lr
625;
626; THUMBONE-LABEL: load_atomic_f64__seq_cst:
627; THUMBONE:       @ %bb.0:
628; THUMBONE-NEXT:    push {r7, lr}
629; THUMBONE-NEXT:    sub sp, #8
630; THUMBONE-NEXT:    movs r2, #0
631; THUMBONE-NEXT:    str r2, [sp]
632; THUMBONE-NEXT:    str r2, [sp, #4]
633; THUMBONE-NEXT:    mov r3, r2
634; THUMBONE-NEXT:    bl __sync_val_compare_and_swap_8
635; THUMBONE-NEXT:    add sp, #8
636; THUMBONE-NEXT:    pop {r7, pc}
637;
638; ARMV4-LABEL: load_atomic_f64__seq_cst:
639; ARMV4:       @ %bb.0:
640; ARMV4-NEXT:    push {r11, lr}
641; ARMV4-NEXT:    mov r1, #5
642; ARMV4-NEXT:    bl __atomic_load_8
643; ARMV4-NEXT:    pop {r11, lr}
644; ARMV4-NEXT:    mov pc, lr
645;
646; ARMV6-LABEL: load_atomic_f64__seq_cst:
647; ARMV6:       @ %bb.0:
648; ARMV6-NEXT:    ldrexd r0, r1, [r0]
649; ARMV6-NEXT:    mov r2, #0
650; ARMV6-NEXT:    mcr p15, #0, r2, c7, c10, #5
651; ARMV6-NEXT:    bx lr
652;
653; THUMBM-LABEL: load_atomic_f64__seq_cst:
654; THUMBM:       @ %bb.0:
655; THUMBM-NEXT:    push {r7, lr}
656; THUMBM-NEXT:    movs r1, #5
657; THUMBM-NEXT:    bl __atomic_load_8
658; THUMBM-NEXT:    pop {r7, pc}
659  %val = load atomic double, ptr %ptr seq_cst, align 8
660  ret double %val
661}
662
663define void @store_atomic_f16__seq_cst(ptr %ptr, half %val1) {
664; ARM-LABEL: store_atomic_f16__seq_cst:
665; ARM:       @ %bb.0:
666; ARM-NEXT:    dmb ish
667; ARM-NEXT:    strh r1, [r0]
668; ARM-NEXT:    dmb ish
669; ARM-NEXT:    bx lr
670;
671; ARMOPTNONE-LABEL: store_atomic_f16__seq_cst:
672; ARMOPTNONE:       @ %bb.0:
673; ARMOPTNONE-NEXT:    sub sp, sp, #4
674; ARMOPTNONE-NEXT:    str r1, [sp] @ 4-byte Spill
675; ARMOPTNONE-NEXT:    mov r1, r0
676; ARMOPTNONE-NEXT:    ldr r0, [sp] @ 4-byte Reload
677; ARMOPTNONE-NEXT:    vmov s0, r0
678; ARMOPTNONE-NEXT:    vmov r0, s0
679; ARMOPTNONE-NEXT:    dmb ish
680; ARMOPTNONE-NEXT:    strh r0, [r1]
681; ARMOPTNONE-NEXT:    dmb ish
682; ARMOPTNONE-NEXT:    add sp, sp, #4
683; ARMOPTNONE-NEXT:    bx lr
684;
685; THUMBTWO-LABEL: store_atomic_f16__seq_cst:
686; THUMBTWO:       @ %bb.0:
687; THUMBTWO-NEXT:    dmb ish
688; THUMBTWO-NEXT:    strh r1, [r0]
689; THUMBTWO-NEXT:    dmb ish
690; THUMBTWO-NEXT:    bx lr
691;
692; THUMBONE-LABEL: store_atomic_f16__seq_cst:
693; THUMBONE:       @ %bb.0:
694; THUMBONE-NEXT:    push {r7, lr}
695; THUMBONE-NEXT:    bl __sync_lock_test_and_set_2
696; THUMBONE-NEXT:    pop {r7, pc}
697;
698; ARMV4-LABEL: store_atomic_f16__seq_cst:
699; ARMV4:       @ %bb.0:
700; ARMV4-NEXT:    push {r11, lr}
701; ARMV4-NEXT:    mov r2, #5
702; ARMV4-NEXT:    bl __atomic_store_2
703; ARMV4-NEXT:    pop {r11, lr}
704; ARMV4-NEXT:    mov pc, lr
705;
706; ARMV6-LABEL: store_atomic_f16__seq_cst:
707; ARMV6:       @ %bb.0:
708; ARMV6-NEXT:    mov r2, #0
709; ARMV6-NEXT:    mcr p15, #0, r2, c7, c10, #5
710; ARMV6-NEXT:    strh r1, [r0]
711; ARMV6-NEXT:    mcr p15, #0, r2, c7, c10, #5
712; ARMV6-NEXT:    bx lr
713;
714; THUMBM-LABEL: store_atomic_f16__seq_cst:
715; THUMBM:       @ %bb.0:
716; THUMBM-NEXT:    dmb sy
717; THUMBM-NEXT:    strh r1, [r0]
718; THUMBM-NEXT:    dmb sy
719; THUMBM-NEXT:    bx lr
720  store atomic half %val1, ptr %ptr seq_cst, align 2
721  ret void
722}
723
724define void @store_atomic_bf16__seq_cst(ptr %ptr, bfloat %val1) {
725; ARM-LABEL: store_atomic_bf16__seq_cst:
726; ARM:       @ %bb.0:
727; ARM-NEXT:    dmb ish
728; ARM-NEXT:    strh r1, [r0]
729; ARM-NEXT:    dmb ish
730; ARM-NEXT:    bx lr
731;
732; ARMOPTNONE-LABEL: store_atomic_bf16__seq_cst:
733; ARMOPTNONE:       @ %bb.0:
734; ARMOPTNONE-NEXT:    sub sp, sp, #4
735; ARMOPTNONE-NEXT:    str r1, [sp] @ 4-byte Spill
736; ARMOPTNONE-NEXT:    mov r1, r0
737; ARMOPTNONE-NEXT:    ldr r0, [sp] @ 4-byte Reload
738; ARMOPTNONE-NEXT:    vmov s0, r0
739; ARMOPTNONE-NEXT:    vmov r0, s0
740; ARMOPTNONE-NEXT:    dmb ish
741; ARMOPTNONE-NEXT:    strh r0, [r1]
742; ARMOPTNONE-NEXT:    dmb ish
743; ARMOPTNONE-NEXT:    add sp, sp, #4
744; ARMOPTNONE-NEXT:    bx lr
745;
746; THUMBTWO-LABEL: store_atomic_bf16__seq_cst:
747; THUMBTWO:       @ %bb.0:
748; THUMBTWO-NEXT:    dmb ish
749; THUMBTWO-NEXT:    strh r1, [r0]
750; THUMBTWO-NEXT:    dmb ish
751; THUMBTWO-NEXT:    bx lr
752;
753; THUMBONE-LABEL: store_atomic_bf16__seq_cst:
754; THUMBONE:       @ %bb.0:
755; THUMBONE-NEXT:    push {r7, lr}
756; THUMBONE-NEXT:    bl __sync_lock_test_and_set_2
757; THUMBONE-NEXT:    pop {r7, pc}
758;
759; ARMV4-LABEL: store_atomic_bf16__seq_cst:
760; ARMV4:       @ %bb.0:
761; ARMV4-NEXT:    push {r11, lr}
762; ARMV4-NEXT:    mov r2, #5
763; ARMV4-NEXT:    bl __atomic_store_2
764; ARMV4-NEXT:    pop {r11, lr}
765; ARMV4-NEXT:    mov pc, lr
766;
767; ARMV6-LABEL: store_atomic_bf16__seq_cst:
768; ARMV6:       @ %bb.0:
769; ARMV6-NEXT:    mov r2, #0
770; ARMV6-NEXT:    mcr p15, #0, r2, c7, c10, #5
771; ARMV6-NEXT:    strh r1, [r0]
772; ARMV6-NEXT:    mcr p15, #0, r2, c7, c10, #5
773; ARMV6-NEXT:    bx lr
774;
775; THUMBM-LABEL: store_atomic_bf16__seq_cst:
776; THUMBM:       @ %bb.0:
777; THUMBM-NEXT:    dmb sy
778; THUMBM-NEXT:    strh r1, [r0]
779; THUMBM-NEXT:    dmb sy
780; THUMBM-NEXT:    bx lr
781  store atomic bfloat %val1, ptr %ptr seq_cst, align 2
782  ret void
783}
784
785define void @store_atomic_f32__seq_cst(ptr %ptr, float %val1) {
786; ARM-LABEL: store_atomic_f32__seq_cst:
787; ARM:       @ %bb.0:
788; ARM-NEXT:    dmb ish
789; ARM-NEXT:    str r1, [r0]
790; ARM-NEXT:    dmb ish
791; ARM-NEXT:    bx lr
792;
793; ARMOPTNONE-LABEL: store_atomic_f32__seq_cst:
794; ARMOPTNONE:       @ %bb.0:
795; ARMOPTNONE-NEXT:    sub sp, sp, #4
796; ARMOPTNONE-NEXT:    str r1, [sp] @ 4-byte Spill
797; ARMOPTNONE-NEXT:    mov r1, r0
798; ARMOPTNONE-NEXT:    ldr r0, [sp] @ 4-byte Reload
799; ARMOPTNONE-NEXT:    vmov s0, r0
800; ARMOPTNONE-NEXT:    vmov r0, s0
801; ARMOPTNONE-NEXT:    dmb ish
802; ARMOPTNONE-NEXT:    str r0, [r1]
803; ARMOPTNONE-NEXT:    dmb ish
804; ARMOPTNONE-NEXT:    add sp, sp, #4
805; ARMOPTNONE-NEXT:    bx lr
806;
807; THUMBTWO-LABEL: store_atomic_f32__seq_cst:
808; THUMBTWO:       @ %bb.0:
809; THUMBTWO-NEXT:    dmb ish
810; THUMBTWO-NEXT:    str r1, [r0]
811; THUMBTWO-NEXT:    dmb ish
812; THUMBTWO-NEXT:    bx lr
813;
814; THUMBONE-LABEL: store_atomic_f32__seq_cst:
815; THUMBONE:       @ %bb.0:
816; THUMBONE-NEXT:    push {r7, lr}
817; THUMBONE-NEXT:    bl __sync_lock_test_and_set_4
818; THUMBONE-NEXT:    pop {r7, pc}
819;
820; ARMV4-LABEL: store_atomic_f32__seq_cst:
821; ARMV4:       @ %bb.0:
822; ARMV4-NEXT:    push {r11, lr}
823; ARMV4-NEXT:    mov r2, #5
824; ARMV4-NEXT:    bl __atomic_store_4
825; ARMV4-NEXT:    pop {r11, lr}
826; ARMV4-NEXT:    mov pc, lr
827;
828; ARMV6-LABEL: store_atomic_f32__seq_cst:
829; ARMV6:       @ %bb.0:
830; ARMV6-NEXT:    mov r2, #0
831; ARMV6-NEXT:    mcr p15, #0, r2, c7, c10, #5
832; ARMV6-NEXT:    str r1, [r0]
833; ARMV6-NEXT:    mcr p15, #0, r2, c7, c10, #5
834; ARMV6-NEXT:    bx lr
835;
836; THUMBM-LABEL: store_atomic_f32__seq_cst:
837; THUMBM:       @ %bb.0:
838; THUMBM-NEXT:    dmb sy
839; THUMBM-NEXT:    str r1, [r0]
840; THUMBM-NEXT:    dmb sy
841; THUMBM-NEXT:    bx lr
842  store atomic float %val1, ptr %ptr seq_cst, align 4
843  ret void
844}
845
846define void @store_atomic_f64__seq_cst(ptr %ptr, double %val1) {
847; ARM-LABEL: store_atomic_f64__seq_cst:
848; ARM:       @ %bb.0:
849; ARM-NEXT:    push {r4, r5, lr}
850; ARM-NEXT:    mov r3, r2
851; ARM-NEXT:    dmb ish
852; ARM-NEXT:    mov r2, r1
853; ARM-NEXT:  LBB13_1: @ %atomicrmw.start
854; ARM-NEXT:    @ =>This Inner Loop Header: Depth=1
855; ARM-NEXT:    ldrexd r4, r5, [r0]
856; ARM-NEXT:    strexd r1, r2, r3, [r0]
857; ARM-NEXT:    cmp r1, #0
858; ARM-NEXT:    bne LBB13_1
859; ARM-NEXT:  @ %bb.2: @ %atomicrmw.end
860; ARM-NEXT:    dmb ish
861; ARM-NEXT:    pop {r4, r5, pc}
862;
863; ARMOPTNONE-LABEL: store_atomic_f64__seq_cst:
864; ARMOPTNONE:       @ %bb.0:
865; ARMOPTNONE-NEXT:    push	{r4, r5, r7, r8, r10, r11, lr}
866; ARMOPTNONE-NEXT:    add	r7, sp, #20
867; ARMOPTNONE-NEXT:    sub	sp, sp, #24
868; ARMOPTNONE-NEXT:    str	r0, [sp, #4] @ 4-byte Spill
869; ARMOPTNONE-NEXT:    vmov	d16, r1, r2
870; ARMOPTNONE-NEXT:    vmov	r1, r2, d16
871; ARMOPTNONE-NEXT:    str	r2, [sp, #8] @ 4-byte Spill
872; ARMOPTNONE-NEXT:    str	r1, [sp, #12] @ 4-byte Spill
873; ARMOPTNONE-NEXT:    dmb	ish
874; ARMOPTNONE-NEXT:    ldr	r1, [r0]
875; ARMOPTNONE-NEXT:    ldr	r0, [r0, #4]
876; ARMOPTNONE-NEXT:    str	r1, [sp, #16] @ 4-byte Spill
877; ARMOPTNONE-NEXT:    str	r0, [sp, #20] @ 4-byte Spill
878; ARMOPTNONE-NEXT:    b LBB13_1
879; ARMOPTNONE-NEXT:  LBB13_1: @ %atomicrmw.start
880; ARMOPTNONE-NEXT:    @ =>This Loop Header: Depth=1
881; ARMOPTNONE-NEXT:    @ Child Loop BB13_2 Depth 2
882; ARMOPTNONE-NEXT:    ldr r3, [sp, #20] @ 4-byte Reload
883; ARMOPTNONE-NEXT:    ldr r2, [sp, #16] @ 4-byte Reload
884; ARMOPTNONE-NEXT:    ldr r12, [sp, #8] @ 4-byte Reload
885; ARMOPTNONE-NEXT:    ldr r0, [sp, #12] @ 4-byte Reload
886; ARMOPTNONE-NEXT:    ldr r8, [sp, #4] @ 4-byte Reload
887; ARMOPTNONE-NEXT:    str r3, [sp] @ 4-byte Spill
888; ARMOPTNONE-NEXT:    @ implicit-def: $r1
889; ARMOPTNONE-NEXT:    @ implicit-def: $r9
890; ARMOPTNONE-NEXT:    @ kill: def $r8 killed $r8 def $r8_r9
891; ARMOPTNONE-NEXT:    mov r9, r1
892; ARMOPTNONE-NEXT:    @ kill: def $r0 killed $r0 def $r0_r1
893; ARMOPTNONE-NEXT:    mov r1, r12
894; ARMOPTNONE-NEXT:    mov r10, r2
895; ARMOPTNONE-NEXT:    mov r11, r3
896; ARMOPTNONE-NEXT:  LBB13_2: @ %atomicrmw.start
897; ARMOPTNONE-NEXT:    @ Parent Loop BB13_1 Depth=1
898; ARMOPTNONE-NEXT:    @ => This Inner Loop Header: Depth=2
899; ARMOPTNONE-NEXT:    ldrexd r4, r5, [r8]
900; ARMOPTNONE-NEXT:    cmp r4, r10
901; ARMOPTNONE-NEXT:    cmpeq r5, r11
902; ARMOPTNONE-NEXT:    bne LBB13_4
903; ARMOPTNONE-NEXT:  @ %bb.3: @ %atomicrmw.start
904; ARMOPTNONE-NEXT:    @ in Loop: Header=BB13_2 Depth=2
905; ARMOPTNONE-NEXT:    strexd r9, r0, r1, [r8]
906; ARMOPTNONE-NEXT:    cmp r9, #0
907; ARMOPTNONE-NEXT:    bne LBB13_2
908; ARMOPTNONE-NEXT:  LBB13_4: @ %atomicrmw.start
909; ARMOPTNONE-NEXT:    @ in Loop: Header=BB13_1 Depth=1
910; ARMOPTNONE-NEXT:    ldr r1, [sp] @ 4-byte Reload
911; ARMOPTNONE-NEXT:    mov r0, r5
912; ARMOPTNONE-NEXT:    eor r3, r0, r1
913; ARMOPTNONE-NEXT:    mov r1, r4
914; ARMOPTNONE-NEXT:    eor r2, r1, r2
915; ARMOPTNONE-NEXT:    orr r2, r2, r3
916; ARMOPTNONE-NEXT:    cmp r2, #0
917; ARMOPTNONE-NEXT:    str r1, [sp, #16] @ 4-byte Spill
918; ARMOPTNONE-NEXT:    str r0, [sp, #20] @ 4-byte Spill
919; ARMOPTNONE-NEXT:    bne LBB13_1
920; ARMOPTNONE-NEXT:    b LBB13_5
921; ARMOPTNONE-NEXT:  LBB13_5: @ %atomicrmw.end
922; ARMOPTNONE-NEXT:    dmb ish
923; ARMOPTNONE-NEXT:    sub sp, r7, #20
924; ARMOPTNONE-NEXT:    pop	{r4, r5, r7, r8, r10, r11, pc}
925;
926; THUMBTWO-LABEL: store_atomic_f64__seq_cst:
927; THUMBTWO:       @ %bb.0:
928; THUMBTWO-NEXT:    dmb ish
929; THUMBTWO-NEXT:  LBB13_1: @ %atomicrmw.start
930; THUMBTWO-NEXT:    @ =>This Inner Loop Header: Depth=1
931; THUMBTWO-NEXT:    ldrexd r3, r9, [r0]
932; THUMBTWO-NEXT:    strexd r3, r1, r2, [r0]
933; THUMBTWO-NEXT:    cmp r3, #0
934; THUMBTWO-NEXT:    bne LBB13_1
935; THUMBTWO-NEXT:  @ %bb.2: @ %atomicrmw.end
936; THUMBTWO-NEXT:    dmb ish
937; THUMBTWO-NEXT:    bx lr
938;
939; THUMBONE-LABEL: store_atomic_f64__seq_cst:
940; THUMBONE:       @ %bb.0:
941; THUMBONE-NEXT:    push {r7, lr}
942; THUMBONE-NEXT:    bl __sync_lock_test_and_set_8
943; THUMBONE-NEXT:    pop {r7, pc}
944;
945; ARMV4-LABEL: store_atomic_f64__seq_cst:
946; ARMV4:       @ %bb.0:
947; ARMV4-NEXT:    push {r11, lr}
948; ARMV4-NEXT:    sub sp, sp, #8
949; ARMV4-NEXT:    mov r1, #5
950; ARMV4-NEXT:    str r1, [sp]
951; ARMV4-NEXT:    bl __atomic_store_8
952; ARMV4-NEXT:    add sp, sp, #8
953; ARMV4-NEXT:    pop {r11, lr}
954; ARMV4-NEXT:    mov pc, lr
955;
956; ARMV6-LABEL: store_atomic_f64__seq_cst:
957; ARMV6:       @ %bb.0:
958; ARMV6-NEXT:    push {r4, r5, r11, lr}
959; ARMV6-NEXT:    @ kill: def $r3 killed $r3 killed $r2_r3 def $r2_r3
960; ARMV6-NEXT:    mov r1, #0
961; ARMV6-NEXT:    @ kill: def $r2 killed $r2 killed $r2_r3 def $r2_r3
962; ARMV6-NEXT:    mcr p15, #0, r1, c7, c10, #5
963; ARMV6-NEXT:  .LBB13_1: @ %atomicrmw.start
964; ARMV6-NEXT:    @ =>This Inner Loop Header: Depth=1
965; ARMV6-NEXT:    ldrexd r4, r5, [r0]
966; ARMV6-NEXT:    strexd r1, r2, r3, [r0]
967; ARMV6-NEXT:    cmp r1, #0
968; ARMV6-NEXT:    bne .LBB13_1
969; ARMV6-NEXT:  @ %bb.2: @ %atomicrmw.end
970; ARMV6-NEXT:    mov r0, #0
971; ARMV6-NEXT:    mcr p15, #0, r0, c7, c10, #5
972; ARMV6-NEXT:    pop {r4, r5, r11, pc}
973;
974; THUMBM-LABEL: store_atomic_f64__seq_cst:
975; THUMBM:       @ %bb.0:
976; THUMBM-NEXT:    push {r7, lr}
977; THUMBM-NEXT:    sub sp, #8
978; THUMBM-NEXT:    movs r1, #5
979; THUMBM-NEXT:    str r1, [sp]
980; THUMBM-NEXT:    bl __atomic_store_8
981; THUMBM-NEXT:    add sp, #8
982; THUMBM-NEXT:    pop {r7, pc}
983  store atomic double %val1, ptr %ptr seq_cst, align 8
984  ret void
985}
986