xref: /llvm-project/llvm/test/CodeGen/ARM/and-cmpz-to-shift.ll (revision e0ed0333f0fed2e73f805afd58b61176a87aa3ad)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
2; RUN: llc -mtriple=thumbv6m %s -o - | FileCheck %s --check-prefix=T1
3; RUN: llc -mtriple=thumbv7m %s -o - | FileCheck %s --check-prefix=T2
4
5define void @test(i32 %x, i32 %a, i32 %b, i32 %c, i32 %d, ptr %p1, ptr %p2) {
6; T1-LABEL: test:
7; T1:       @ %bb.0:
8; T1-NEXT:    push {r4, lr}
9; T1-NEXT:    movs r4, #1
10; T1-NEXT:    lsls r4, r4, #24
11; T1-NEXT:    tst r0, r4
12; T1-NEXT:    beq .LBB0_2
13; T1-NEXT:  @ %bb.1:
14; T1-NEXT:    mov r1, r2
15; T1-NEXT:  .LBB0_2:
16; T1-NEXT:    ldr r0, [sp, #12]
17; T1-NEXT:    str r1, [r0]
18; T1-NEXT:    beq .LBB0_4
19; T1-NEXT:  @ %bb.3:
20; T1-NEXT:    ldr r3, [sp, #8]
21; T1-NEXT:  .LBB0_4:
22; T1-NEXT:    ldr r0, [sp, #16]
23; T1-NEXT:    str r3, [r0]
24; T1-NEXT:    pop {r4, pc}
25;
26; T2-LABEL: test:
27; T2:       @ %bb.0:
28; T2-NEXT:    tst.w r0, #16777216
29; T2-NEXT:    ldr r0, [sp, #4]
30; T2-NEXT:    it ne
31; T2-NEXT:    movne r1, r2
32; T2-NEXT:    str r1, [r0]
33; T2-NEXT:    ldr r1, [sp, #8]
34; T2-NEXT:    ldr r0, [sp]
35; T2-NEXT:    it eq
36; T2-NEXT:    moveq r0, r3
37; T2-NEXT:    str r0, [r1]
38; T2-NEXT:    bx lr
39  %and = and i32 %x, u0x1000000
40  %cmp = icmp eq i32 %and, 0
41  %sel1 = select i1 %cmp, i32 %a, i32 %b
42  %sel2 = select i1 %cmp, i32 %c, i32 %d
43  store i32 %sel1, ptr %p1, align 4
44  store i32 %sel2, ptr %p2, align 4
45  ret void
46}
47