xref: /llvm-project/llvm/test/CodeGen/ARM/ParallelDSP/smlad9.ll (revision 9bd7b149c2f577086a716ccd0363d057caa3d98a)
1; RUN: opt -mtriple=armv8m.main-none-none-eabi -mattr=+dsp < %s -arm-parallel-dsp -S | FileCheck %s
2;
3; Muls with operands that are constants: not yet supported, so the rewrite
4; should not trigger (but we do want to add this soon).
5;
6; CHECK-NOT:  call i32 @llvm.arm.smlad
7;
8define dso_local i32 @test(i32 %arg, ptr nocapture readnone %arg1, ptr nocapture readonly %arg2, ptr nocapture readonly %arg3) {
9entry:
10  %cmp24 = icmp sgt i32 %arg, 0
11  br i1 %cmp24, label %for.body.preheader, label %for.cond.cleanup
12
13for.body.preheader:
14  %.pre = load i16, ptr %arg3, align 2
15  %.pre27 = load i16, ptr %arg2, align 2
16  br label %for.body
17
18for.cond.cleanup:
19  %mac1.0.lcssa = phi i32 [ 0, %entry ], [ %add11, %for.body ]
20  ret i32 %mac1.0.lcssa
21
22for.body:
23  %mac1.026 = phi i32 [ %add11, %for.body ], [ 0, %for.body.preheader ]
24  %i.025 = phi i32 [ %add, %for.body ], [ 0, %for.body.preheader ]
25  %add = add nuw nsw i32 %i.025, 1
26  %arrayidx3 = getelementptr inbounds i16, ptr %arg2, i32 %i.025
27  %v2 = load i16, ptr %arrayidx3, align 2
28  %conv = sext i16 %v2 to i32
29
30; RHS operand of this mul is a constant
31  %mul = mul nsw i32 %conv, 43
32
33  %arrayidx6 = getelementptr inbounds i16, ptr %arg2, i32 %add
34  %v3 = load i16, ptr %arrayidx6, align 2
35  %conv7 = sext i16 %v3 to i32
36
37; And this RHS operand is a constant too.
38  %mul9 = mul nsw i32 %conv7, 42
39
40  %add10 = add i32 %mul, %mac1.026
41  %add11 = add i32 %mul9, %add10
42  %exitcond = icmp ne i32 %add, %arg
43  br i1 %exitcond, label %for.body, label %for.cond.cleanup
44}
45
46