xref: /llvm-project/llvm/test/CodeGen/ARM/ParallelDSP/pr42729.ll (revision bed1c7f061aa12417aa081e334afdba45767b938) 
1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2; RUN: opt -mtriple=thumbv7-unknown-linux-android -arm-parallel-dsp -S %s -o - | FileCheck %s
3
4define void @undef_no_return(ptr %a) {
5; CHECK-LABEL: @undef_no_return(
6; CHECK-NEXT:  entry:
7; CHECK-NEXT:    [[INCDEC_PTR21:%.*]] = getelementptr inbounds i16, ptr [[A:%.*]], i32 3
8; CHECK-NEXT:    [[INCDEC_PTR29:%.*]] = getelementptr inbounds i16, ptr [[A]], i32 4
9; CHECK-NEXT:    br label [[FOR_BODY:%.*]]
10; CHECK:       for.body:
11; CHECK-NEXT:    [[TMP0:%.*]] = load i16, ptr [[INCDEC_PTR21]], align 2
12; CHECK-NEXT:    [[TMP2:%.*]] = load i32, ptr [[INCDEC_PTR21]], align 2
13; CHECK-NEXT:    [[TMP3:%.*]] = trunc i32 [[TMP2]] to i16
14; CHECK-NEXT:    [[TMP4:%.*]] = sext i16 [[TMP3]] to i32
15; CHECK-NEXT:    [[TMP5:%.*]] = lshr i32 [[TMP2]], 16
16; CHECK-NEXT:    [[TMP6:%.*]] = trunc i32 [[TMP5]] to i16
17; CHECK-NEXT:    [[TMP7:%.*]] = sext i16 [[TMP6]] to i32
18; CHECK-NEXT:    [[CONV25:%.*]] = sext i16 [[TMP0]] to i32
19; CHECK-NEXT:    [[UGLYGEP15:%.*]] = getelementptr i8, ptr undef, i32 undef
20; CHECK-NEXT:    [[SCEVGEP17:%.*]] = getelementptr i16, ptr [[UGLYGEP15]], i32 7
21; CHECK-NEXT:    [[TMP8:%.*]] = load i16, ptr [[SCEVGEP17]], align 2
22; CHECK-NEXT:    [[UGLYGEP12:%.*]] = getelementptr i8, ptr undef, i32 undef
23; CHECK-NEXT:    [[SCEVGEP14:%.*]] = getelementptr i16, ptr [[UGLYGEP12]], i32 6
24; CHECK-NEXT:    [[TMP10:%.*]] = load i32, ptr [[SCEVGEP14]], align 2
25; CHECK-NEXT:    [[TMP11:%.*]] = trunc i32 [[TMP10]] to i16
26; CHECK-NEXT:    [[TMP12:%.*]] = call i32 @llvm.arm.smladx(i32 [[TMP10]], i32 [[TMP2]], i32 undef)
27; CHECK-NEXT:    [[TMP13:%.*]] = sext i16 [[TMP11]] to i32
28; CHECK-NEXT:    [[TMP14:%.*]] = lshr i32 [[TMP10]], 16
29; CHECK-NEXT:    [[TMP15:%.*]] = trunc i32 [[TMP14]] to i16
30; CHECK-NEXT:    [[TMP16:%.*]] = sext i16 [[TMP15]] to i32
31; CHECK-NEXT:    [[CONV31:%.*]] = sext i16 [[TMP8]] to i32
32; CHECK-NEXT:    [[TMP17:%.*]] = load i16, ptr [[INCDEC_PTR29]], align 2
33; CHECK-NEXT:    [[CONV33:%.*]] = sext i16 [[TMP17]] to i32
34; CHECK-NEXT:    [[TMP18:%.*]] = load i16, ptr [[SCEVGEP14]], align 2
35; CHECK-NEXT:    [[CONV39:%.*]] = sext i16 [[TMP18]] to i32
36; CHECK-NEXT:    [[MUL_I287_NEG_NEG:%.*]] = mul nsw i32 [[TMP16]], [[TMP4]]
37; CHECK-NEXT:    [[MUL_I283_NEG_NEG:%.*]] = mul nsw i32 [[TMP13]], [[TMP7]]
38; CHECK-NEXT:    [[REASS_ADD408:%.*]] = add i32 undef, [[MUL_I287_NEG_NEG]]
39; CHECK-NEXT:    [[REASS_ADD409:%.*]] = add i32 [[REASS_ADD408]], [[MUL_I283_NEG_NEG]]
40; CHECK-NEXT:    br label [[FOR_BODY]]
41;
42entry:
43  %incdec.ptr21 = getelementptr inbounds i16, ptr %a, i32 3
44  %incdec.ptr29 = getelementptr inbounds i16, ptr %a, i32 4
45  br label %for.body
46
47for.body:
48  %0 = load i16, ptr %incdec.ptr21, align 2
49  %conv25 = sext i16 %0 to i32
50  %uglygep15 = getelementptr i8, ptr undef, i32 undef
51  %scevgep17 = getelementptr i16, ptr %uglygep15, i32 7
52  %1 = load i16, ptr %scevgep17, align 2
53  %conv31 = sext i16 %1 to i32
54  %2 = load i16, ptr %incdec.ptr29, align 2
55  %conv33 = sext i16 %2 to i32
56  %uglygep12 = getelementptr i8, ptr undef, i32 undef
57  %scevgep14 = getelementptr i16, ptr %uglygep12, i32 6
58  %3 = load i16, ptr %scevgep14, align 2
59  %conv39 = sext i16 %3 to i32
60  %mul.i287.neg.neg = mul nsw i32 %conv31, %conv25
61  %mul.i283.neg.neg = mul nsw i32 %conv39, %conv33
62  %reass.add408 = add i32 undef, %mul.i287.neg.neg
63  %reass.add409 = add i32 %reass.add408, %mul.i283.neg.neg
64  br label %for.body
65}
66
67define i32 @return(ptr %a, ptr %b, i32 %N) {
68; CHECK-LABEL: @return(
69; CHECK-NEXT:  entry:
70; CHECK-NEXT:    [[INCDEC_PTR21:%.*]] = getelementptr inbounds i16, ptr [[A:%.*]], i32 3
71; CHECK-NEXT:    [[INCDEC_PTR29:%.*]] = getelementptr inbounds i16, ptr [[A]], i32 4
72; CHECK-NEXT:    br label [[FOR_BODY:%.*]]
73; CHECK:       for.body:
74; CHECK-NEXT:    [[IV:%.*]] = phi i32 [ [[N:%.*]], [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[FOR_BODY]] ]
75; CHECK-NEXT:    [[ACC:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[TMP12:%.*]], [[FOR_BODY]] ]
76; CHECK-NEXT:    [[TMP0:%.*]] = load i16, ptr [[INCDEC_PTR21]], align 2
77; CHECK-NEXT:    [[TMP2:%.*]] = load i32, ptr [[INCDEC_PTR21]], align 2
78; CHECK-NEXT:    [[TMP3:%.*]] = trunc i32 [[TMP2]] to i16
79; CHECK-NEXT:    [[TMP4:%.*]] = sext i16 [[TMP3]] to i32
80; CHECK-NEXT:    [[TMP5:%.*]] = lshr i32 [[TMP2]], 16
81; CHECK-NEXT:    [[TMP6:%.*]] = trunc i32 [[TMP5]] to i16
82; CHECK-NEXT:    [[TMP7:%.*]] = sext i16 [[TMP6]] to i32
83; CHECK-NEXT:    [[CONV25:%.*]] = sext i16 [[TMP0]] to i32
84; CHECK-NEXT:    [[B_IDX:%.*]] = add nuw nsw i32 [[IV]], 1
85; CHECK-NEXT:    [[SCEVGEP17:%.*]] = getelementptr i16, ptr [[B:%.*]], i32 [[B_IDX]]
86; CHECK-NEXT:    [[SCEVGEP14:%.*]] = getelementptr i16, ptr [[B]], i32 [[IV]]
87; CHECK-NEXT:    [[TMP8:%.*]] = load i16, ptr [[SCEVGEP17]], align 2
88; CHECK-NEXT:    [[TMP10:%.*]] = load i32, ptr [[SCEVGEP14]], align 2
89; CHECK-NEXT:    [[TMP11:%.*]] = trunc i32 [[TMP10]] to i16
90; CHECK-NEXT:    [[TMP12]] = call i32 @llvm.arm.smladx(i32 [[TMP10]], i32 [[TMP2]], i32 [[ACC]])
91; CHECK-NEXT:    [[TMP13:%.*]] = sext i16 [[TMP11]] to i32
92; CHECK-NEXT:    [[TMP14:%.*]] = lshr i32 [[TMP10]], 16
93; CHECK-NEXT:    [[TMP15:%.*]] = trunc i32 [[TMP14]] to i16
94; CHECK-NEXT:    [[TMP16:%.*]] = sext i16 [[TMP15]] to i32
95; CHECK-NEXT:    [[CONV31:%.*]] = sext i16 [[TMP8]] to i32
96; CHECK-NEXT:    [[TMP17:%.*]] = load i16, ptr [[INCDEC_PTR29]], align 2
97; CHECK-NEXT:    [[CONV33:%.*]] = sext i16 [[TMP17]] to i32
98; CHECK-NEXT:    [[TMP18:%.*]] = load i16, ptr [[SCEVGEP14]], align 2
99; CHECK-NEXT:    [[CONV39:%.*]] = sext i16 [[TMP18]] to i32
100; CHECK-NEXT:    [[MUL_I287_NEG_NEG:%.*]] = mul nsw i32 [[TMP16]], [[TMP4]]
101; CHECK-NEXT:    [[MUL_I283_NEG_NEG:%.*]] = mul nsw i32 [[TMP13]], [[TMP7]]
102; CHECK-NEXT:    [[REASS_ADD408:%.*]] = add i32 [[ACC]], [[MUL_I287_NEG_NEG]]
103; CHECK-NEXT:    [[REASS_ADD409:%.*]] = add i32 [[REASS_ADD408]], [[MUL_I283_NEG_NEG]]
104; CHECK-NEXT:    [[IV_NEXT]] = add nuw nsw i32 [[IV]], -1
105; CHECK-NEXT:    [[CMP:%.*]] = icmp ne i32 [[IV_NEXT]], 0
106; CHECK-NEXT:    br i1 [[CMP]], label [[FOR_BODY]], label [[EXIT:%.*]]
107; CHECK:       exit:
108; CHECK-NEXT:    ret i32 [[TMP12]]
109;
110entry:
111  %incdec.ptr21 = getelementptr inbounds i16, ptr %a, i32 3
112  %incdec.ptr29 = getelementptr inbounds i16, ptr %a, i32 4
113  br label %for.body
114
115for.body:
116  %iv = phi i32 [ %N, %entry ], [ %iv.next, %for.body ]
117  %acc = phi i32 [ 0, %entry ], [ %reass.add409, %for.body ]
118  %0 = load i16, ptr %incdec.ptr21, align 2
119  %conv25 = sext i16 %0 to i32
120  %b.idx = add nuw nsw i32 %iv, 1
121  %scevgep17 = getelementptr i16, ptr %b, i32 %b.idx
122  %scevgep14 = getelementptr i16, ptr %b, i32 %iv
123  %1 = load i16, ptr %scevgep17, align 2
124  %conv31 = sext i16 %1 to i32
125  %2 = load i16, ptr %incdec.ptr29, align 2
126  %conv33 = sext i16 %2 to i32
127  %3 = load i16, ptr %scevgep14, align 2
128  %conv39 = sext i16 %3 to i32
129  %mul.i287.neg.neg = mul nsw i32 %conv31, %conv25
130  %mul.i283.neg.neg = mul nsw i32 %conv39, %conv33
131  %reass.add408 = add i32 %acc, %mul.i287.neg.neg
132  %reass.add409 = add i32 %reass.add408, %mul.i283.neg.neg
133  %iv.next = add nuw nsw i32 %iv, -1
134  %cmp = icmp ne i32 %iv.next, 0
135  br i1 %cmp, label %for.body, label %exit
136
137exit:
138  ret i32 %reass.add409
139}
140