1; RUN: llc -mtriple arm-linux-gnueabihf -mattr=+vfp2 -float-abi=hard -global-isel %s -o - | FileCheck %s -check-prefix CHECK -check-prefix HARD 2; RUN: llc -mtriple arm-linux-gnueabi -mattr=+vfp2,+soft-float -float-abi=soft -global-isel %s -o - | FileCheck %s -check-prefix CHECK -check-prefix SOFT-AEABI 3; RUN: llc -mtriple arm-linux-gnu- -mattr=+vfp2,+soft-float -float-abi=soft -global-isel %s -o - | FileCheck %s -check-prefix CHECK -check-prefix SOFT-DEFAULT 4 5define arm_aapcscc float @test_frem_float(float %x, float %y) { 6; CHECK-LABEL: test_frem_float: 7; CHECK: bl fmodf 8 %r = frem float %x, %y 9 ret float %r 10} 11 12define arm_aapcscc double @test_frem_double(double %x, double %y) { 13; CHECK-LABEL: test_frem_double: 14; CHECK: bl fmod 15 %r = frem double %x, %y 16 ret double %r 17} 18 19declare float @llvm.pow.f32(float %x, float %y) 20define arm_aapcscc float @test_fpow_float(float %x, float %y) { 21; CHECK-LABEL: test_fpow_float: 22; CHECK: bl powf 23 %r = call float @llvm.pow.f32(float %x, float %y) 24 ret float %r 25} 26 27declare double @llvm.pow.f64(double %x, double %y) 28define arm_aapcscc double @test_fpow_double(double %x, double %y) { 29; CHECK-LABEL: test_fpow_double: 30; CHECK: bl pow 31 %r = call double @llvm.pow.f64(double %x, double %y) 32 ret double %r 33} 34 35define arm_aapcscc float @test_add_float(float %x, float %y) { 36; CHECK-LABEL: test_add_float: 37; HARD: vadd.f32 38; SOFT-AEABI: bl __aeabi_fadd 39; SOFT-DEFAULT: bl __addsf3 40 %r = fadd float %x, %y 41 ret float %r 42} 43 44define arm_aapcscc double @test_add_double(double %x, double %y) { 45; CHECK-LABEL: test_add_double: 46; HARD: vadd.f64 47; SOFT-AEABI: bl __aeabi_dadd 48; SOFT-DEFAULT: bl __adddf3 49 %r = fadd double %x, %y 50 ret double %r 51} 52 53define arm_aapcscc float @test_sub_float(float %x, float %y) { 54; CHECK-LABEL: test_sub_float: 55; HARD: vsub.f32 56; SOFT-AEABI: bl __aeabi_fsub 57; SOFT-DEFAULT: bl __subsf3 58 %r = fsub float %x, %y 59 ret float %r 60} 61 62define arm_aapcscc double @test_sub_double(double %x, double %y) { 63; CHECK-LABEL: test_sub_double: 64; HARD: vsub.f64 65; SOFT-AEABI: bl __aeabi_dsub 66; SOFT-DEFAULT: bl __subdf3 67 %r = fsub double %x, %y 68 ret double %r 69} 70define arm_aapcs_vfpcc i32 @test_cmp_float_ogt(float %x, float %y) { 71; CHECK-LABEL: test_cmp_float_ogt 72; HARD: vcmp.f32 73; HARD: vmrs APSR_nzcv, fpscr 74; HARD-NEXT: movgt 75; SOFT-AEABI: bl __aeabi_fcmpgt 76; SOFT-DEFAULT: bl __gtsf2 77entry: 78 %v = fcmp ogt float %x, %y 79 %r = zext i1 %v to i32 80 ret i32 %r 81} 82 83define arm_aapcs_vfpcc i32 @test_cmp_float_one(float %x, float %y) { 84; CHECK-LABEL: test_cmp_float_one 85; HARD: vcmp.f32 86; HARD: vmrs APSR_nzcv, fpscr 87; HARD: movgt 88; HARD-NOT: vcmp 89; HARD: movmi 90; SOFT-AEABI-DAG: bl __aeabi_fcmpgt 91; SOFT-AEABI-DAG: bl __aeabi_fcmplt 92; SOFT-DEFAULT-DAG: bl __gtsf2 93; SOFT-DEFAULT-DAG: bl __ltsf2 94entry: 95 %v = fcmp one float %x, %y 96 %r = zext i1 %v to i32 97 ret i32 %r 98} 99