1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 2; RUN: llc < %s -mtriple=thumbv7-apple-ios | FileCheck %s 3; rdar://11035895 4 5; DAG combine incorrectly optimize (i32 vextract (v4i16 load $addr), c) to 6; (i16 load $addr+c*sizeof(i16)). It should have issued an extload instead. i.e. 7; (i32 extload $addr+c*sizeof(i16) 8define void @test_hi_short3(ptr nocapture %srcA, ptr nocapture %dst) nounwind { 9; CHECK-LABEL: test_hi_short3: 10; CHECK: @ %bb.0: @ %entry 11; CHECK-NEXT: vldr d16, [r0] 12; CHECK-NEXT: vmov.u16 r0, d16[2] 13; CHECK-NEXT: vmov.32 d16[0], r0 14; CHECK-NEXT: vuzp.16 d16, d17 15; CHECK-NEXT: vst1.32 {d16[0]}, [r1:32] 16; CHECK-NEXT: bx lr 17entry: 18 %0 = load <3 x i16> , ptr %srcA, align 8 19 %1 = shufflevector <3 x i16> %0, <3 x i16> undef, <2 x i32> <i32 2, i32 undef> 20 store <2 x i16> %1, ptr %dst, align 4 21 ret void 22} 23 24