1; RUN: llc -mtriple=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=GCN %s 2; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=GCN %s 3; RUN: llc -mtriple=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 %s 4 5; R600: {{^}}s_mad_zext_i32_to_i64: 6; R600: MEM_RAT_CACHELESS STORE_RAW 7; R600: MEM_RAT_CACHELESS STORE_RAW 8 9; GCN: {{^}}s_mad_zext_i32_to_i64: 10; GCN: v_mov_b32_e32 v[[V_ZERO:[0-9]]], 0{{$}} 11; GCN: buffer_store_dwordx2 v[0:[[V_ZERO]]] 12define amdgpu_kernel void @s_mad_zext_i32_to_i64(ptr addrspace(1) %out, i32 %a, i32 %b, i32 %c) #0 { 13entry: 14 %tmp0 = mul i32 %a, %b 15 %tmp1 = add i32 %tmp0, %c 16 %tmp2 = zext i32 %tmp1 to i64 17 store i64 %tmp2, ptr addrspace(1) %out 18 ret void 19} 20 21; GCN-LABEL: {{^}}s_cmp_zext_i1_to_i32 22; GCN: v_cndmask_b32 23define amdgpu_kernel void @s_cmp_zext_i1_to_i32(ptr addrspace(1) %out, i32 %a, i32 %b) #0 { 24entry: 25 %tmp0 = icmp eq i32 %a, %b 26 %tmp1 = zext i1 %tmp0 to i32 27 store i32 %tmp1, ptr addrspace(1) %out 28 ret void 29} 30 31; GCN-LABEL: {{^}}s_arg_zext_i1_to_i64: 32define amdgpu_kernel void @s_arg_zext_i1_to_i64(ptr addrspace(1) %out, i1 zeroext %arg) #0 { 33 %ext = zext i1 %arg to i64 34 store i64 %ext, ptr addrspace(1) %out, align 8 35 ret void 36} 37 38; GCN-LABEL: {{^}}s_cmp_zext_i1_to_i64: 39; GCN-DAG: s_mov_b32 s{{[0-9]+}}, 0 40; GCN-DAG: s_cmp_eq_u32 41; GCN: v_cndmask_b32 42define amdgpu_kernel void @s_cmp_zext_i1_to_i64(ptr addrspace(1) %out, i32 %a, i32 %b) #0 { 43 %cmp = icmp eq i32 %a, %b 44 %ext = zext i1 %cmp to i64 45 store i64 %ext, ptr addrspace(1) %out, align 8 46 ret void 47} 48 49; FIXME: Why different commute? 50; GCN-LABEL: {{^}}s_cmp_zext_i1_to_i16 51; GCN: s_load_dword [[A:s[0-9]+]] 52; GCN: s_load_dword [[B:s[0-9]+]] 53 54; GCN-DAG: s_and_b32 [[MASK_A:s[0-9]+]], [[A]], 0xffff{{$}} 55; GCN-DAG: s_and_b32 [[MASK_B:s[0-9]+]], [[B]], 0xffff{{$}} 56; GCN: s_cmp_eq_u32 [[MASK_A]], [[MASK_B]] 57; GCN: s_cselect_b64 [[CC:s\[[0-9:]+\]]], -1, 0 58; GCN: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, [[CC]] 59; GCN: buffer_store_short [[RESULT]] 60define amdgpu_kernel void @s_cmp_zext_i1_to_i16(ptr addrspace(1) %out, [8 x i32], i16 zeroext %a, [8 x i32], i16 zeroext %b) #0 { 61 %tmp0 = icmp eq i16 %a, %b 62 %tmp1 = zext i1 %tmp0 to i16 63 store i16 %tmp1, ptr addrspace(1) %out 64 ret void 65} 66 67attributes #0 = { nounwind } 68