1; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=bonaire -enable-misched=0 -verify-machineinstrs < %s | FileCheck %s 2; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=bonaire -enable-misched=0 -verify-machineinstrs < %s | FileCheck %s 3 4declare void @llvm.write_register.i32(metadata, i32) #0 5declare void @llvm.write_register.i64(metadata, i64) #0 6 7; CHECK-LABEL: {{^}}test_write_m0: 8define amdgpu_kernel void @test_write_m0(i32 %val) #0 { 9 call void @llvm.write_register.i32(metadata !0, i32 0) 10 call void @llvm.write_register.i32(metadata !0, i32 -1) 11 call void @llvm.write_register.i32(metadata !0, i32 %val) 12 call void @llvm.amdgcn.wave.barrier() #1 13 ret void 14} 15 16; CHECK-LABEL: {{^}}test_write_exec: 17; CHECK: s_mov_b64 exec, 0 18; CHECK: s_mov_b64 exec, -1 19; CHECK: s_mov_b64 exec, s{{\[[0-9]+:[0-9]+\]}} 20define amdgpu_kernel void @test_write_exec(i64 %val) #0 { 21 call void @llvm.write_register.i64(metadata !1, i64 0) 22 call void @llvm.write_register.i64(metadata !1, i64 -1) 23 call void @llvm.write_register.i64(metadata !1, i64 %val) 24 call void @llvm.amdgcn.wave.barrier() #1 25 ret void 26} 27 28; CHECK-LABEL: {{^}}test_write_flat_scratch_0: 29; CHECK: s_mov_b64 flat_scratch, 0 30define amdgpu_kernel void @test_write_flat_scratch_0(i64 %val) #0 { 31 call void @llvm.write_register.i64(metadata !2, i64 0) 32 call void @llvm.amdgcn.wave.barrier() #1 33 ret void 34} 35 36; CHECK-LABEL: {{^}}test_write_flat_scratch_neg1: 37; CHECK: s_mov_b64 flat_scratch, -1 38define amdgpu_kernel void @test_write_flat_scratch_neg1(i64 %val) #0 { 39 call void @llvm.write_register.i64(metadata !2, i64 -1) 40 call void @llvm.amdgcn.wave.barrier() #1 41 ret void 42} 43 44; CHECK-LABEL: {{^}}test_write_flat_scratch_val: 45; CHECK: s_load_dwordx2 flat_scratch, s{{\[[0-9]+:[0-9]+\]}} 46define amdgpu_kernel void @test_write_flat_scratch_val(i64 %val) #0 { 47 call void @llvm.write_register.i64(metadata !2, i64 %val) 48 call void @llvm.amdgcn.wave.barrier() #1 49 ret void 50} 51 52; CHECK-LABEL: {{^}}test_write_flat_scratch_lo: 53; CHECK: s_mov_b32 flat_scratch_lo, 0 54; CHECK: s_mov_b32 flat_scratch_lo, s{{[0-9]+}} 55define amdgpu_kernel void @test_write_flat_scratch_lo(i32 %val) #0 { 56 call void @llvm.write_register.i32(metadata !3, i32 0) 57 call void @llvm.write_register.i32(metadata !3, i32 %val) 58 call void @llvm.amdgcn.wave.barrier() #1 59 ret void 60} 61 62; CHECK-LABEL: {{^}}test_write_flat_scratch_hi: 63; CHECK: s_mov_b32 flat_scratch_hi, 0 64; CHECK: s_mov_b32 flat_scratch_hi, s{{[0-9]+}} 65define amdgpu_kernel void @test_write_flat_scratch_hi(i32 %val) #0 { 66 call void @llvm.write_register.i32(metadata !4, i32 0) 67 call void @llvm.write_register.i32(metadata !4, i32 %val) 68 call void @llvm.amdgcn.wave.barrier() #1 69 ret void 70} 71 72; CHECK-LABEL: {{^}}test_write_exec_lo: 73; CHECK: s_mov_b32 exec_lo, 0 74; CHECK: s_mov_b32 exec_lo, s{{[0-9]+}} 75define amdgpu_kernel void @test_write_exec_lo(i32 %val) #0 { 76 call void @llvm.write_register.i32(metadata !5, i32 0) 77 call void @llvm.write_register.i32(metadata !5, i32 %val) 78 call void @llvm.amdgcn.wave.barrier() #1 79 ret void 80} 81 82; CHECK-LABEL: {{^}}test_write_exec_hi: 83; CHECK: s_mov_b32 exec_hi, 0 84; CHECK: s_mov_b32 exec_hi, s{{[0-9]+}} 85define amdgpu_kernel void @test_write_exec_hi(i32 %val) #0 { 86 call void @llvm.write_register.i32(metadata !6, i32 0) 87 call void @llvm.write_register.i32(metadata !6, i32 %val) 88 call void @llvm.amdgcn.wave.barrier() #1 89 ret void 90} 91 92declare void @llvm.amdgcn.wave.barrier() #1 93 94attributes #0 = { nounwind } 95attributes #1 = { convergent nounwind } 96 97!0 = !{!"m0"} 98!1 = !{!"exec"} 99!2 = !{!"flat_scratch"} 100!3 = !{!"flat_scratch_lo"} 101!4 = !{!"flat_scratch_hi"} 102!5 = !{!"exec_lo"} 103!6 = !{!"exec_hi"} 104