1; RUN: llc -mtriple=amdgcn -verify-machineinstrs < %s | FileCheck -strict-whitespace %s --check-prefix=DEFAULT 2; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -strict-whitespace %s --check-prefix=DEFAULT 3; RUN: llc -mtriple=amdgcn --misched=ilpmax -verify-machineinstrs < %s | FileCheck -strict-whitespace %s --check-prefix=ILPMAX 4; RUN: llc -mtriple=amdgcn --misched=ilpmax -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -strict-whitespace %s --check-prefix=ILPMAX 5; The ilpmax scheduler is used for the second test to get the ordering we want for the test. 6 7; DEFAULT-LABEL: {{^}}main: 8; DEFAULT: s_load_dwordx8 9; DEFAULT: s_waitcnt lgkmcnt(0) 10; DEFAULT: buffer_load_format_xyzw 11; DEFAULT: buffer_load_format_xyzw 12; DEFAULT-DAG: s_waitcnt vmcnt(0) 13; DEFAULT-DAG: exp 14; DEFAULT: exp 15; DEFAULT-NEXT: s_endpgm 16define amdgpu_vs void @main(ptr addrspace(4) inreg %arg, ptr addrspace(4) inreg %arg1, ptr addrspace(4) inreg %arg2, ptr addrspace(4) inreg %arg3, ptr addrspace(4) inreg %arg4, i32 inreg %arg5, i32 %arg6, i32 %arg7, i32 %arg8, i32 %arg9, ptr addrspace(4) inreg %constptr) #0 { 17main_body: 18 %tmp10 = load <16 x i8>, ptr addrspace(4) %arg3, !tbaa !0 19 %tmp10.cast.int = bitcast <16 x i8> %tmp10 to i128 20 %tmp10.cast = inttoptr i128 %tmp10.cast.int to ptr addrspace(8) 21 %tmp11 = call <4 x float> @llvm.amdgcn.struct.ptr.buffer.load.format.v4f32(ptr addrspace(8) %tmp10.cast, i32 %arg6, i32 0, i32 0, i32 0) 22 %tmp12 = extractelement <4 x float> %tmp11, i32 0 23 %tmp13 = extractelement <4 x float> %tmp11, i32 1 24 call void @llvm.amdgcn.s.barrier() #1 25 %tmp14 = extractelement <4 x float> %tmp11, i32 2 26 %tmp15 = load float, ptr addrspace(4) %constptr, align 4 27 %tmp16 = getelementptr <16 x i8>, ptr addrspace(4) %arg3, i32 1 28 %tmp17 = load <16 x i8>, ptr addrspace(4) %tmp16, !tbaa !0 29 %tmp17.cast.int = bitcast <16 x i8> %tmp17 to i128 30 %tmp17.cast = inttoptr i128 %tmp17.cast.int to ptr addrspace(8) 31 %tmp18 = call <4 x float> @llvm.amdgcn.struct.ptr.buffer.load.format.v4f32(ptr addrspace(8) %tmp17.cast, i32 %arg6, i32 0, i32 0, i32 0) 32 %tmp19 = extractelement <4 x float> %tmp18, i32 0 33 %tmp20 = extractelement <4 x float> %tmp18, i32 1 34 %tmp21 = extractelement <4 x float> %tmp18, i32 2 35 %tmp22 = extractelement <4 x float> %tmp18, i32 3 36 call void @llvm.amdgcn.exp.f32(i32 32, i32 15, float %tmp19, float %tmp20, float %tmp21, float %tmp22, i1 false, i1 false) #0 37 call void @llvm.amdgcn.exp.f32(i32 12, i32 15, float %tmp12, float %tmp13, float %tmp14, float %tmp15, i1 true, i1 false) #0 38 ret void 39} 40 41; ILPMAX-LABEL: {{^}}main2: 42; ILPMAX: s_load_dwordx8 43; ILPMAX: s_waitcnt lgkmcnt(0) 44; ILPMAX: buffer_load 45; ILPMAX: buffer_load 46; ILPMAX: s_waitcnt vmcnt(0) 47; ILPMAX: exp pos0 48; ILPMAX-NEXT: exp param0 49; ILPMAX: s_endpgm 50define amdgpu_vs void @main2(ptr addrspace(4) inreg %arg, ptr addrspace(4) inreg %arg1, ptr addrspace(4) inreg %arg2, ptr addrspace(4) inreg %arg3, ptr addrspace(4) inreg %arg4, i32 inreg %arg5, i32 inreg %arg6, i32 %arg7, i32 %arg8, i32 %arg9, i32 %arg10) #0 { 51main_body: 52 %tmp11 = load <16 x i8>, ptr addrspace(4) %arg4, align 16, !tbaa !0 53 %tmp12 = add i32 %arg5, %arg7 54 %tmp11.cast.int = bitcast <16 x i8> %tmp11 to i128 55 %tmp11.cast = inttoptr i128 %tmp11.cast.int to ptr addrspace(8) 56 %tmp13 = call <4 x float> @llvm.amdgcn.struct.ptr.buffer.load.format.v4f32(ptr addrspace(8) %tmp11.cast, i32 %tmp12, i32 0, i32 0, i32 0) 57 %tmp14 = extractelement <4 x float> %tmp13, i32 0 58 %tmp15 = extractelement <4 x float> %tmp13, i32 1 59 %tmp16 = extractelement <4 x float> %tmp13, i32 2 60 %tmp17 = extractelement <4 x float> %tmp13, i32 3 61 %tmp18 = getelementptr [16 x <16 x i8>], ptr addrspace(4) %arg4, i64 0, i64 1 62 %tmp19 = load <16 x i8>, ptr addrspace(4) %tmp18, align 16, !tbaa !0 63 %tmp20 = add i32 %arg5, %arg7 64 %tmp19.cast.int = bitcast <16 x i8> %tmp19 to i128 65 %tmp19.cast = inttoptr i128 %tmp19.cast.int to ptr addrspace(8) 66 %tmp21 = call <4 x float> @llvm.amdgcn.struct.ptr.buffer.load.format.v4f32(ptr addrspace(8) %tmp19.cast, i32 %tmp20, i32 0, i32 0, i32 0) 67 %tmp22 = extractelement <4 x float> %tmp21, i32 0 68 %tmp23 = extractelement <4 x float> %tmp21, i32 1 69 %tmp24 = extractelement <4 x float> %tmp21, i32 2 70 %tmp25 = extractelement <4 x float> %tmp21, i32 3 71 call void @llvm.amdgcn.exp.f32(i32 12, i32 15, float %tmp14, float %tmp15, float %tmp16, float %tmp17, i1 false, i1 false) #0 72 call void @llvm.amdgcn.exp.f32(i32 32, i32 15, float %tmp22, float %tmp23, float %tmp24, float %tmp25, i1 true, i1 false) #0 73 ret void 74} 75 76declare void @llvm.amdgcn.s.barrier() #1 77declare <4 x float> @llvm.amdgcn.struct.ptr.buffer.load.format.v4f32(ptr addrspace(8), i32, i32, i32, i32 immarg) #2 78declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #0 79 80attributes #0 = { nounwind } 81attributes #1 = { convergent nounwind } 82attributes #2 = { nounwind readonly } 83 84!0 = !{!1, !1, i64 0, i32 1} 85!1 = !{!"const", !2} 86!2 = !{!"tbaa root"} 87