xref: /llvm-project/llvm/test/CodeGen/AMDGPU/vtx-schedule.ll (revision 9e9907f1cfa424366fba58d9520f9305b537cec9)
1; RUN: llc < %s -mtriple=r600 -mcpu=redwood | FileCheck %s
2
3; This test is for a scheduler bug where VTX_READ instructions that used
4; the result of another VTX_READ instruction were being grouped in the
5; same fetch clasue.
6
7; CHECK: {{^}}test:
8; CHECK: Fetch clause
9; CHECK: VTX_READ_32 [[IN0:T[0-9]+\.X]], [[IN0]], 0
10; CHECK: Fetch clause
11; CHECK: VTX_READ_32 [[IN1:T[0-9]+\.X]], [[IN1]], 0
12define amdgpu_kernel void @test(ptr addrspace(1) nocapture %out, ptr addrspace(1) nocapture %in0) {
13entry:
14  %0 = load ptr addrspace(1), ptr addrspace(1) %in0
15  %1 = load i32, ptr addrspace(1) %0
16  store i32 %1, ptr addrspace(1) %out
17  ret void
18}
19