1; RUN: llc < %s -mtriple=r600 -show-mc-encoding -mcpu=cypress | FileCheck --check-prefix=EG --check-prefix=FUNC %s 2; RUN: llc < %s -mtriple=r600 -show-mc-encoding -mcpu=barts | FileCheck --check-prefix=EG --check-prefix=FUNC %s 3; RUN: llc < %s -mtriple=r600 -show-mc-encoding -mcpu=cayman | FileCheck --check-prefix=CM --check-prefix=FUNC %s 4 5; FUNC-LABEL: {{^}}vtx_fetch32: 6; EG: VTX_READ_32 T[[GPR:[0-9]]].X, T[[GPR]].X, 0, #1 ; encoding: [0x40,0x01,0x0[[GPR]],0x10,0x0[[GPR]],0xf0,0x5f,0x13,0x00,0x00,0x08,0x00 7; CM: VTX_READ_32 T[[GPR:[0-9]]].X, T[[GPR]].X, 0, #1 ; encoding: [0x40,0x01,0x0[[GPR]],0x00,0x0[[GPR]],0xf0,0x5f,0x13,0x00,0x00,0x00,0x00 8 9define amdgpu_kernel void @vtx_fetch32(ptr addrspace(1) %out, ptr addrspace(1) %in) { 10 %v = load i32, ptr addrspace(1) %in 11 store i32 %v, ptr addrspace(1) %out 12 ret void 13} 14 15; FUNC-LABEL: {{^}}vtx_fetch128: 16; EG: VTX_READ_128 T[[DST:[0-9]]].XYZW, T[[SRC:[0-9]]].X, 0, #1 ; encoding: [0x40,0x01,0x0[[SRC]],0x40,0x0[[DST]],0x10,0x8d,0x18,0x00,0x00,0x08,0x00 17; CM: VTX_READ_128 T[[DST:[0-9]]].XYZW, T[[SRC:[0-9]]].X, 0, #1 ; encoding: [0x40,0x01,0x0[[SRC]],0x00,0x0[[DST]],0x10,0x8d,0x18,0x00,0x00,0x00,0x00 18 19define amdgpu_kernel void @vtx_fetch128(ptr addrspace(1) %out, ptr addrspace(1) %in) { 20 %v = load <4 x i32>, ptr addrspace(1) %in 21 store <4 x i32> %v, ptr addrspace(1) %out 22 ret void 23} 24 25; FUNC-LABEL: {{^}}vtx_fetch32_id3: 26; EG: VTX_READ_32 T[[GPR:[0-9]]].X, T[[GPR]].X, 0, #3 ; encoding: [0x40,0x03,0x0[[GPR]],0x10,0x0[[GPR]],0xf0,0x5f,0x13,0x00,0x00,0x08,0x00 27; CM: VTX_READ_32 T[[GPR:[0-9]]].X, T[[GPR]].X, 0, #3 ; encoding: [0x40,0x03,0x0[[GPR]],0x00,0x0[[GPR]],0xf0,0x5f,0x13,0x00,0x00,0x00,0x00 28 29define amdgpu_kernel void @vtx_fetch32_id3(ptr addrspace(1) %out, ptr addrspace(7) %in) { 30 %v = load i32, ptr addrspace(7) %in 31 store i32 %v, ptr addrspace(1) %out 32 ret void 33} 34 35; FUNC-LABEL: {{^}}vtx_fetch32_id2: 36; EG: VTX_READ_32 T[[GPR:[0-9]]].X, T[[GPR]].X, 0, #2 ; encoding: [0x40,0x02,0x0[[GPR]],0x10,0x0[[GPR]],0xf0,0x5f,0x13,0x00,0x00,0x08,0x00 37; CM: VTX_READ_32 T[[GPR:[0-9]]].X, T[[GPR]].X, 0, #2 ; encoding: [0x40,0x02,0x0[[GPR]],0x00,0x0[[GPR]],0xf0,0x5f,0x13,0x00,0x00,0x00,0x00 38 39@t = internal addrspace(4) constant [4 x i32] [i32 0, i32 1, i32 2, i32 3] 40 41define amdgpu_kernel void @vtx_fetch32_id2(ptr addrspace(1) %out, i32 %in) { 42 %a = getelementptr inbounds [4 x i32], ptr addrspace(4) @t, i32 0, i32 %in 43 %v = load i32, ptr addrspace(4) %a 44 store i32 %v, ptr addrspace(1) %out 45 ret void 46} 47