xref: /llvm-project/llvm/test/CodeGen/AMDGPU/v1024.ll (revision 9e9907f1cfa424366fba58d9520f9305b537cec9)
1; RUN: llc -mtriple=amdgcn -mcpu=gfx908 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
2
3; Check that we do not use AGPRs for v32i32 type
4
5; GCN-LABEL: {{^}}test_v1024:
6; GCN-NOT: v_accvgpr
7; GCN-COUNT-8: global_store_dwordx4
8; GCN-NOT: v_accvgpr
9define amdgpu_kernel void @test_v1024(i1 %c0) {
10entry:
11  %alloca = alloca <32 x i32>, align 16, addrspace(5)
12  call void @llvm.memset.p5.i32(ptr addrspace(5) %alloca, i8 0, i32 128, i1 false)
13  br i1 %c0, label %if.then.i.i, label %if.else.i
14
15if.then.i.i:                                      ; preds = %entry
16  call void @llvm.memcpy.p5.p5.i64(ptr addrspace(5) align 16 %alloca, ptr addrspace(5) align 4 undef, i64 128, i1 false)
17  br label %if.then.i62.i
18
19if.else.i:                                        ; preds = %entry
20  br label %if.then.i62.i
21
22if.then.i62.i:                                    ; preds = %if.else.i, %if.then.i.i
23  call void @llvm.memcpy.p1.p5.i64(ptr addrspace(1) align 4 undef, ptr addrspace(5) align 16 %alloca, i64 128, i1 false)
24  ret void
25}
26
27declare void @llvm.memset.p5.i32(ptr addrspace(5) nocapture readonly, i8, i32, i1 immarg)
28declare void @llvm.memcpy.p5.p5.i64(ptr addrspace(5) nocapture writeonly, ptr addrspace(5) nocapture readonly, i64, i1 immarg)
29
30declare void @llvm.memcpy.p1.p5.i64(ptr addrspace(1) nocapture writeonly, ptr addrspace(5) nocapture readonly, i64, i1 immarg)
31