1; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=SI %s 2; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=VI %s 3; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=r600 -mcpu=cypress < %s | FileCheck -enable-var-scope -check-prefix=EG %s 4 5declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone 6 7define amdgpu_kernel void @trunc_i64_to_i32_store(ptr addrspace(1) %out, [8 x i32], i64 %in) { 8; GCN-LABEL: {{^}}trunc_i64_to_i32_store: 9; GCN: s_load_dword [[SLOAD:s[0-9]+]], s[4:5], 10; GCN: v_mov_b32_e32 [[VLOAD:v[0-9]+]], [[SLOAD]] 11; SI: buffer_store_dword [[VLOAD]] 12; VI: flat_store_dword v[{{[0-9:]+}}], [[VLOAD]] 13 14; EG-LABEL: {{^}}trunc_i64_to_i32_store: 15; EG: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1 16; EG: LSHR 17; EG-NEXT: 2( 18 19 %result = trunc i64 %in to i32 store i32 %result, ptr addrspace(1) %out, align 4 20 ret void 21} 22 23; GCN-LABEL: {{^}}trunc_load_shl_i64: 24; GCN-DAG: s_load_dwordx2 25; GCN-DAG: s_load_dword [[SREG:s[0-9]+]], 26; GCN: s_lshl_b32 [[SHL:s[0-9]+]], [[SREG]], 2 27; GCN: v_mov_b32_e32 [[VSHL:v[0-9]+]], [[SHL]] 28; SI: buffer_store_dword [[VSHL]] 29; VI: flat_store_dword v[{{[0-9:]+}}], [[VSHL]] 30 31define amdgpu_kernel void @trunc_load_shl_i64(ptr addrspace(1) %out, [8 x i32], i64 %a) { 32 %b = shl i64 %a, 2 33 %result = trunc i64 %b to i32 34 store i32 %result, ptr addrspace(1) %out, align 4 35 ret void 36} 37 38; GCN-LABEL: {{^}}trunc_shl_i64: 39; SI: s_load_dwordx2 s[[[LO_SREG:[0-9]+]]:{{[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0xd 40; VI: s_load_dwordx2 s[[[LO_SREG:[0-9]+]]:{{[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x34 41; GCN: s_lshl_b64 s[[[LO_SHL:[0-9]+]]:{{[0-9]+\]}}, s[[[LO_SREG]]:{{[0-9]+\]}}, 2 42; GCN: s_add_u32 s[[LO_SREG2:[0-9]+]], s[[LO_SHL]], 43; GCN: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], s[[LO_SREG2]] 44; SI: buffer_store_dword v[[LO_VREG]], 45; VI: flat_store_dword v[{{[0-9:]+}}], v[[LO_VREG]] 46; GCN: v_mov_b32_e32 47; GCN: v_mov_b32_e32 48define amdgpu_kernel void @trunc_shl_i64(ptr addrspace(1) %out2, ptr addrspace(1) %out, i64 %a) { 49 %aa = add i64 %a, 234 ; Prevent shrinking store. 50 %b = shl i64 %aa, 2 51 %result = trunc i64 %b to i32 52 store i32 %result, ptr addrspace(1) %out, align 4 53 store i64 %b, ptr addrspace(1) %out2, align 8 ; Prevent reducing ops to 32-bits 54 ret void 55} 56 57; GCN-LABEL: {{^}}trunc_i32_to_i1: 58; GCN: v_and_b32_e32 [[VREG:v[0-9]+]], 1, v{{[0-9]+}} 59define amdgpu_kernel void @trunc_i32_to_i1(ptr addrspace(1) %out, ptr addrspace(1) %ptr) { 60 %a = load i32, ptr addrspace(1) %ptr, align 4 61 %trunc = trunc i32 %a to i1 62 %result = select i1 %trunc, i32 1, i32 0 63 store i32 %result, ptr addrspace(1) %out, align 4 64 ret void 65} 66 67; GCN-LABEL: {{^}}trunc_i8_to_i1: 68; GCN: v_and_b32_e32 [[VREG:v[0-9]+]], 1, v{{[0-9]+}} 69define amdgpu_kernel void @trunc_i8_to_i1(ptr addrspace(1) %out, ptr addrspace(1) %ptr) { 70 %a = load i8, ptr addrspace(1) %ptr, align 4 71 %trunc = trunc i8 %a to i1 72 %result = select i1 %trunc, i8 1, i8 0 73 store i8 %result, ptr addrspace(1) %out, align 4 74 ret void 75} 76 77; GCN-LABEL: {{^}}sgpr_trunc_i16_to_i1: 78; GCN: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 1 79define amdgpu_kernel void @sgpr_trunc_i16_to_i1(ptr addrspace(1) %out, i16 %a) { 80 %trunc = trunc i16 %a to i1 81 %result = select i1 %trunc, i16 1, i16 0 82 store i16 %result, ptr addrspace(1) %out, align 4 83 ret void 84} 85 86; GCN-LABEL: {{^}}sgpr_trunc_i32_to_i1: 87; GCN: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 1 88define amdgpu_kernel void @sgpr_trunc_i32_to_i1(ptr addrspace(1) %out, i32 %a) { 89 %trunc = trunc i32 %a to i1 90 %result = select i1 %trunc, i32 1, i32 0 91 store i32 %result, ptr addrspace(1) %out, align 4 92 ret void 93} 94 95; GCN-LABEL: {{^}}s_trunc_i64_to_i1: 96; SI: s_load_dwordx2 s[[[SLO:[0-9]+]]:{{[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0x13 97; VI: s_load_dwordx2 s[[[SLO:[0-9]+]]:{{[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0x4c 98; GCN: s_bitcmp1_b32 s[[SLO]], 0 99; GCN: s_cselect_b32 {{s[0-9]+}}, 63, -12 100define amdgpu_kernel void @s_trunc_i64_to_i1(ptr addrspace(1) %out, [8 x i32], i64 %x) { 101 %trunc = trunc i64 %x to i1 102 %sel = select i1 %trunc, i32 63, i32 -12 103 store i32 %sel, ptr addrspace(1) %out 104 ret void 105} 106 107; GCN-LABEL: {{^}}v_trunc_i64_to_i1: 108; SI: buffer_load_dwordx2 v[[[VLO:[0-9]+]]:{{[0-9]+\]}} 109; VI: flat_load_dwordx2 v[[[VLO:[0-9]+]]:{{[0-9]+\]}} 110; GCN: v_and_b32_e32 [[MASKED:v[0-9]+]], 1, v[[VLO]] 111; GCN: v_cmp_eq_u32_e32 vcc, 1, [[MASKED]] 112; GCN: v_cndmask_b32_e64 {{v[0-9]+}}, -12, 63, vcc 113define amdgpu_kernel void @v_trunc_i64_to_i1(ptr addrspace(1) %out, ptr addrspace(1) %in) { 114 %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone 115 %gep = getelementptr i64, ptr addrspace(1) %in, i32 %tid 116 %out.gep = getelementptr i32, ptr addrspace(1) %out, i32 %tid 117 %x = load i64, ptr addrspace(1) %gep 118 119 %trunc = trunc i64 %x to i1 120 %sel = select i1 %trunc, i32 63, i32 -12 121 store i32 %sel, ptr addrspace(1) %out.gep 122 ret void 123} 124