1; RUN: llc -mtriple=amdgcn -disable-promote-alloca-to-vector -verify-machineinstrs < %s | FileCheck %s 2 3declare ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr() #1 4 5declare i32 @llvm.amdgcn.workitem.id.x() #1 6 7; CI+ intrinsic 8declare void @llvm.amdgcn.s.dcache.inv.vol() #0 9 10; VI+ intrinsic 11declare void @llvm.amdgcn.s.dcache.wb() #0 12 13; CHECK-LABEL: {{^}}target_none: 14; CHECK: s_movk_i32 [[OFFSETREG:s[0-9]+]], 0x400 15; CHECK: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, [[OFFSETREG]] 16; CHECK: buffer_store_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 17define amdgpu_kernel void @target_none() #0 { 18 %kernargs = call ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr() 19 %kernargs.gep = getelementptr inbounds i8, ptr addrspace(4) %kernargs, i64 1024 20 %ptr = load ptr addrspace(1), ptr addrspace(4) %kernargs.gep 21 %id = call i32 @llvm.amdgcn.workitem.id.x() 22 %id.ext = sext i32 %id to i64 23 %gep = getelementptr inbounds i32, ptr addrspace(1) %ptr, i64 %id.ext 24 store i32 0, ptr addrspace(1) %gep 25 ret void 26} 27 28; CHECK-LABEL: {{^}}target_tahiti: 29; CHECK: s_movk_i32 [[OFFSETREG:s[0-9]+]], 0x400 30; CHECK: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, [[OFFSETREG]] 31; CHECK: buffer_store_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 32define amdgpu_kernel void @target_tahiti() #1 { 33 %kernargs = call ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr() 34 %kernargs.gep = getelementptr inbounds i8, ptr addrspace(4) %kernargs, i64 1024 35 %ptr = load ptr addrspace(1), ptr addrspace(4) %kernargs.gep 36 %id = call i32 @llvm.amdgcn.workitem.id.x() 37 %id.ext = sext i32 %id to i64 38 %gep = getelementptr inbounds i32, ptr addrspace(1) %ptr, i64 %id.ext 39 store i32 0, ptr addrspace(1) %gep 40 ret void 41} 42 43; CHECK-LABEL: {{^}}target_bonaire: 44; CHECK: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x100 45; CHECK: buffer_store_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 46; CHECK: s_dcache_inv_vol 47define amdgpu_kernel void @target_bonaire() #3 { 48 %kernargs = call ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr() 49 %kernargs.gep = getelementptr inbounds i8, ptr addrspace(4) %kernargs, i64 1024 50 %ptr = load ptr addrspace(1), ptr addrspace(4) %kernargs.gep 51 %id = call i32 @llvm.amdgcn.workitem.id.x() 52 %id.ext = sext i32 %id to i64 53 %gep = getelementptr inbounds i32, ptr addrspace(1) %ptr, i64 %id.ext 54 store i32 0, ptr addrspace(1) %gep 55 call void @llvm.amdgcn.s.dcache.inv.vol() 56 ret void 57} 58 59; CHECK-LABEL: {{^}}target_fiji: 60; CHECK: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x400 61; CHECK: flat_store_dword 62; CHECK: s_dcache_wb{{$}} 63define amdgpu_kernel void @target_fiji() #4 { 64 %kernargs = call ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr() 65 %kernargs.gep = getelementptr inbounds i8, ptr addrspace(4) %kernargs, i64 1024 66 %ptr = load ptr addrspace(1), ptr addrspace(4) %kernargs.gep 67 %id = call i32 @llvm.amdgcn.workitem.id.x() 68 %id.ext = sext i32 %id to i64 69 %gep = getelementptr inbounds i32, ptr addrspace(1) %ptr, i64 %id.ext 70 store i32 0, ptr addrspace(1) %gep 71 call void @llvm.amdgcn.s.dcache.wb() 72 ret void 73} 74 75; CHECK-LABEL: {{^}}promote_alloca_enabled: 76; CHECK: ds_read_b32 77define amdgpu_kernel void @promote_alloca_enabled(ptr addrspace(1) nocapture %out, ptr addrspace(1) nocapture %in) #5 { 78entry: 79 %stack = alloca [5 x i32], align 4, addrspace(5) 80 %tmp = load i32, ptr addrspace(1) %in, align 4 81 %arrayidx1 = getelementptr inbounds [5 x i32], ptr addrspace(5) %stack, i32 0, i32 %tmp 82 %load = load i32, ptr addrspace(5) %arrayidx1 83 store i32 %load, ptr addrspace(1) %out 84 ret void 85} 86 87; CHECK-LABEL: {{^}}promote_alloca_disabled: 88; CHECK: SCRATCH_RSRC_DWORD0 89; CHECK: SCRATCH_RSRC_DWORD1 90; CHECK: ScratchSize: 24 91define amdgpu_kernel void @promote_alloca_disabled(ptr addrspace(1) nocapture %out, ptr addrspace(1) nocapture %in) #6 { 92entry: 93 %stack = alloca [5 x i32], align 4, addrspace(5) 94 %tmp = load i32, ptr addrspace(1) %in, align 4 95 %arrayidx1 = getelementptr inbounds [5 x i32], ptr addrspace(5) %stack, i32 0, i32 %tmp 96 %load = load i32, ptr addrspace(5) %arrayidx1 97 store i32 %load, ptr addrspace(1) %out 98 ret void 99} 100 101attributes #0 = { nounwind } 102attributes #1 = { nounwind readnone } 103attributes #2 = { nounwind "target-cpu"="tahiti" } 104attributes #3 = { nounwind "target-cpu"="bonaire" } 105attributes #4 = { nounwind "target-cpu"="fiji" } 106attributes #5 = { nounwind "target-features"="+promote-alloca" "amdgpu-waves-per-eu"="1,3" "amdgpu-flat-work-group-size"="1,256" } 107attributes #6 = { nounwind "target-features"="-promote-alloca" "amdgpu-waves-per-eu"="1,3" "amdgpu-flat-work-group-size"="1,256" } 108