1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -o - %s -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -verify-machineinstrs | FileCheck %s 3 4@global = external protected addrspace(4) externally_initialized global [4096 x i64], align 16 5 6define hidden fastcc void @bar(i32 %arg, ptr %arg1, ptr %arg2, ptr %arg3, ptr %arg4, ptr %arg5, ptr %arg6) unnamed_addr align 2 { 7; CHECK-LABEL: bar: 8; CHECK: ; %bb.0: ; %bb 9; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 10; CHECK-NEXT: v_mov_b32_e32 v15, v12 11; CHECK-NEXT: v_mov_b32_e32 v14, v11 12; CHECK-NEXT: v_mov_b32_e32 v13, v10 13; CHECK-NEXT: v_mov_b32_e32 v12, v9 14; CHECK-NEXT: v_mov_b32_e32 v11, v8 15; CHECK-NEXT: v_mov_b32_e32 v10, v7 16; CHECK-NEXT: v_mov_b32_e32 v9, v6 17; CHECK-NEXT: v_mov_b32_e32 v8, v5 18; CHECK-NEXT: v_mov_b32_e32 v7, v4 19; CHECK-NEXT: v_mov_b32_e32 v6, v3 20; CHECK-NEXT: s_branch .LBB0_3 21; CHECK-NEXT: ; %bb.1: ; %LeafBlock 22; CHECK-NEXT: s_cbranch_scc1 .LBB0_5 23; CHECK-NEXT: ; %bb.2: ; %bb7 24; CHECK-NEXT: flat_load_dwordx2 v[2:3], v[0:1] 25; CHECK-NEXT: s_getpc_b64 s[18:19] 26; CHECK-NEXT: s_add_u32 s18, s18, global@rel32@lo+1948 27; CHECK-NEXT: s_addc_u32 s19, s19, global@rel32@hi+1956 28; CHECK-NEXT: v_mov_b32_e32 v5, 0 29; CHECK-NEXT: v_mov_b32_e32 v0, s18 30; CHECK-NEXT: v_mov_b32_e32 v1, s19 31; CHECK-NEXT: s_getpc_b64 s[16:17] 32; CHECK-NEXT: s_add_u32 s16, s16, eggs@rel32@lo+4 33; CHECK-NEXT: s_addc_u32 s17, s17, eggs@rel32@hi+12 34; CHECK-NEXT: s_setpc_b64 s[16:17] 35; CHECK-NEXT: .LBB0_3: ; %LeafBlock1 36; CHECK-NEXT: s_cbranch_scc0 .LBB0_5 37; CHECK-NEXT: ; %bb.4: ; %bb8 38; CHECK-NEXT: v_mov_b32_e32 v0, v1 39; CHECK-NEXT: v_mov_b32_e32 v1, v2 40; CHECK-NEXT: v_mov_b32_e32 v2, v6 41; CHECK-NEXT: v_mov_b32_e32 v3, v7 42; CHECK-NEXT: v_mov_b32_e32 v4, v8 43; CHECK-NEXT: v_mov_b32_e32 v5, v9 44; CHECK-NEXT: v_mov_b32_e32 v6, v10 45; CHECK-NEXT: v_mov_b32_e32 v7, v11 46; CHECK-NEXT: v_mov_b32_e32 v8, v12 47; CHECK-NEXT: v_mov_b32_e32 v9, v13 48; CHECK-NEXT: v_mov_b32_e32 v10, v14 49; CHECK-NEXT: v_mov_b32_e32 v11, v15 50; CHECK-NEXT: s_getpc_b64 s[16:17] 51; CHECK-NEXT: s_add_u32 s16, s16, quux@rel32@lo+4 52; CHECK-NEXT: s_addc_u32 s17, s17, quux@rel32@hi+12 53; CHECK-NEXT: s_setpc_b64 s[16:17] 54; CHECK-NEXT: .LBB0_5: ; %bb9 55; CHECK-NEXT: s_setpc_b64 s[30:31] 56bb: 57 switch i32 undef, label %bb9 [ 58 i32 3, label %bb8 59 i32 1, label %bb7 60 ] 61 62bb7: ; preds = %bb 63 %tmp = load ptr, ptr undef, align 8 64 tail call fastcc void @eggs(ptr noundef addrspacecast (ptr addrspace(4) getelementptr inbounds ([4096 x i64], ptr addrspace(4) @global, i64 0, i64 243) to ptr), ptr %tmp, ptr undef, ptr noundef nonnull align 8 dereferenceable(24) %arg2, ptr noundef %arg3, ptr noundef %arg4, ptr noundef %arg5) 65 br label %bb9 66 67bb8: ; preds = %bb 68 tail call fastcc void @quux(ptr noundef nonnull align 8 dereferenceable(24) %arg1, ptr noundef nonnull align 8 dereferenceable(24) %arg2, ptr noundef %arg3, ptr noundef %arg4, ptr noundef %arg5, ptr noundef nonnull align 8 dereferenceable(8) %arg6) 69 br label %bb9 70 71bb9: ; preds = %bb8, %bb7, %bb 72 ret void 73} 74 75declare dso_local fastcc void @eggs(ptr, ptr, ptr, ptr, ptr, ptr, ptr) unnamed_addr align 2 76 77declare dso_local fastcc void @quux(ptr, ptr, ptr, ptr, ptr, ptr) unnamed_addr align 2 78