xref: /llvm-project/llvm/test/CodeGen/AMDGPU/subvector-test.mir (revision 9e9907f1cfa424366fba58d9520f9305b537cec9)
1# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -start-before=greedy -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
2# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -start-before=greedy -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
3...
4# GCN-LABEL: {{^}}"subvector-basic-bb"
5# GCN: s_subvector_loop_begin [[RS:s[0-9]]], .LBB0_2
6# GCN: s_subvector_loop_end [[RS]], .LBB0_1
7name:            subvector-basic-bb
8tracksRegLiveness: true
9machineFunctionInfo:
10  scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr3
11  frameOffsetReg: $sgpr5
12  stackPtrOffsetReg: $sgpr32
13body:             |
14  bb.0:
15    liveins: $sgpr0_sgpr1
16    successors: %bb.1, %bb.2
17
18    %1:sgpr_64 = COPY $sgpr0_sgpr1
19    %4:sgpr_128 = S_LOAD_DWORDX4_IMM %1, 36, 0
20    %11:sreg_64_xexec = S_LOAD_DWORDX2_IMM %4.sub2_sub3, 0, 0
21    undef %15.sub0:vreg_64 = COPY %4.sub0
22    %15.sub1:vreg_64 = COPY %4.sub1
23    %16:vgpr_32 = COPY %1.sub0
24    S_SUBVECTOR_LOOP_BEGIN %bb.2, undef %19:sreg_32, implicit-def $exec, implicit $exec, implicit-def %19
25
26  bb.1:
27    successors: %bb.1, %bb.2
28
29    %14:sreg_32_xm0 = S_ADD_I32 %11.sub0, %11.sub1, implicit-def dead $scc
30    %16:vgpr_32 = COPY %14
31    S_SUBVECTOR_LOOP_END %bb.1, %19:sreg_32, implicit-def $exec, implicit $exec, implicit-def %19
32
33  bb.2:
34
35    GLOBAL_STORE_DWORD %15, %16, 0, 0, implicit $exec
36    S_ENDPGM 0
37...
38