xref: /llvm-project/llvm/test/CodeGen/AMDGPU/srem64.ll (revision eeac0ffaf46cf9f9b0f680b9940cc4b68a0286d8) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
3; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -amdgpu-codegenprepare-expand-div64 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-IR %s
4
5define amdgpu_kernel void @s_test_srem(ptr addrspace(1) %out, i64 %x, i64 %y) {
6; GCN-LABEL: s_test_srem:
7; GCN:       ; %bb.0:
8; GCN-NEXT:    s_load_dwordx2 s[12:13], s[4:5], 0xd
9; GCN-NEXT:    s_load_dwordx4 s[8:11], s[4:5], 0x9
10; GCN-NEXT:    s_mov_b32 s7, 0xf000
11; GCN-NEXT:    s_mov_b32 s6, -1
12; GCN-NEXT:    s_waitcnt lgkmcnt(0)
13; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s12
14; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s13
15; GCN-NEXT:    s_sub_u32 s0, 0, s12
16; GCN-NEXT:    s_subb_u32 s1, 0, s13
17; GCN-NEXT:    s_mov_b32 s4, s8
18; GCN-NEXT:    v_madmk_f32 v0, v1, 0x4f800000, v0
19; GCN-NEXT:    v_rcp_f32_e32 v0, v0
20; GCN-NEXT:    s_mov_b32 s5, s9
21; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
22; GCN-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
23; GCN-NEXT:    v_trunc_f32_e32 v1, v1
24; GCN-NEXT:    v_madmk_f32 v0, v1, 0xcf800000, v0
25; GCN-NEXT:    v_cvt_u32_f32_e32 v1, v1
26; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
27; GCN-NEXT:    v_mul_lo_u32 v2, s0, v1
28; GCN-NEXT:    v_mul_hi_u32 v3, s0, v0
29; GCN-NEXT:    v_mul_lo_u32 v5, s1, v0
30; GCN-NEXT:    v_mul_lo_u32 v4, s0, v0
31; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
32; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
33; GCN-NEXT:    v_mul_hi_u32 v3, v0, v4
34; GCN-NEXT:    v_mul_lo_u32 v5, v0, v2
35; GCN-NEXT:    v_mul_hi_u32 v7, v0, v2
36; GCN-NEXT:    v_mul_hi_u32 v6, v1, v4
37; GCN-NEXT:    v_mul_lo_u32 v4, v1, v4
38; GCN-NEXT:    v_mul_hi_u32 v8, v1, v2
39; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
40; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v7, vcc
41; GCN-NEXT:    v_mul_lo_u32 v2, v1, v2
42; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v4
43; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v5, v6, vcc
44; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v8, vcc
45; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
46; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
47; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
48; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
49; GCN-NEXT:    v_mul_lo_u32 v2, s0, v1
50; GCN-NEXT:    v_mul_hi_u32 v3, s0, v0
51; GCN-NEXT:    v_mul_lo_u32 v4, s1, v0
52; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
53; GCN-NEXT:    v_mul_lo_u32 v3, s0, v0
54; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
55; GCN-NEXT:    v_mul_lo_u32 v6, v0, v2
56; GCN-NEXT:    v_mul_hi_u32 v7, v0, v3
57; GCN-NEXT:    v_mul_hi_u32 v8, v0, v2
58; GCN-NEXT:    v_mul_hi_u32 v5, v1, v3
59; GCN-NEXT:    v_mul_lo_u32 v3, v1, v3
60; GCN-NEXT:    v_mul_hi_u32 v4, v1, v2
61; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
62; GCN-NEXT:    v_addc_u32_e32 v7, vcc, 0, v8, vcc
63; GCN-NEXT:    v_mul_lo_u32 v2, v1, v2
64; GCN-NEXT:    v_add_i32_e32 v3, vcc, v6, v3
65; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v7, v5, vcc
66; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v4, vcc
67; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
68; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
69; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
70; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
71; GCN-NEXT:    v_mul_lo_u32 v2, s10, v1
72; GCN-NEXT:    v_mul_hi_u32 v3, s10, v0
73; GCN-NEXT:    v_mul_hi_u32 v4, s10, v1
74; GCN-NEXT:    v_mul_hi_u32 v5, s11, v1
75; GCN-NEXT:    v_mul_lo_u32 v1, s11, v1
76; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
77; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
78; GCN-NEXT:    v_mul_lo_u32 v4, s11, v0
79; GCN-NEXT:    v_mul_hi_u32 v0, s11, v0
80; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
81; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
82; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v5, vcc
83; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
84; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v2, vcc
85; GCN-NEXT:    v_mul_lo_u32 v1, s12, v1
86; GCN-NEXT:    v_mul_hi_u32 v2, s12, v0
87; GCN-NEXT:    v_mul_lo_u32 v3, s13, v0
88; GCN-NEXT:    v_mul_lo_u32 v0, s12, v0
89; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v2
90; GCN-NEXT:    v_add_i32_e32 v1, vcc, v3, v1
91; GCN-NEXT:    v_sub_i32_e32 v2, vcc, s11, v1
92; GCN-NEXT:    v_mov_b32_e32 v3, s13
93; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s10, v0
94; GCN-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, vcc
95; GCN-NEXT:    v_subrev_i32_e64 v4, s[0:1], s12, v0
96; GCN-NEXT:    v_subbrev_u32_e64 v5, s[2:3], 0, v2, s[0:1]
97; GCN-NEXT:    v_cmp_le_u32_e64 s[2:3], s13, v5
98; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[2:3]
99; GCN-NEXT:    v_cmp_le_u32_e64 s[2:3], s12, v4
100; GCN-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, s[0:1]
101; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[2:3]
102; GCN-NEXT:    v_cmp_eq_u32_e64 s[2:3], s13, v5
103; GCN-NEXT:    v_subrev_i32_e64 v3, s[0:1], s12, v4
104; GCN-NEXT:    v_cndmask_b32_e64 v6, v6, v7, s[2:3]
105; GCN-NEXT:    v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1]
106; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v6
107; GCN-NEXT:    v_cndmask_b32_e64 v3, v4, v3, s[0:1]
108; GCN-NEXT:    v_mov_b32_e32 v4, s11
109; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v4, v1, vcc
110; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s13, v1
111; GCN-NEXT:    v_cndmask_b32_e64 v4, 0, -1, vcc
112; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s12, v0
113; GCN-NEXT:    v_cndmask_b32_e64 v2, v5, v2, s[0:1]
114; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
115; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s13, v1
116; GCN-NEXT:    v_cndmask_b32_e32 v4, v4, v5, vcc
117; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v4
118; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
119; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
120; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
121; GCN-NEXT:    s_endpgm
122;
123; GCN-IR-LABEL: s_test_srem:
124; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
125; GCN-IR-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0xd
126; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x9
127; GCN-IR-NEXT:    s_mov_b64 s[4:5], 0
128; GCN-IR-NEXT:    s_mov_b32 s11, 0
129; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
130; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[8:9], s[6:7], 0
131; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[12:13], s[2:3], 0
132; GCN-IR-NEXT:    s_flbit_i32_b64 s10, s[6:7]
133; GCN-IR-NEXT:    s_flbit_i32_b64 s18, s[2:3]
134; GCN-IR-NEXT:    s_or_b64 s[8:9], s[8:9], s[12:13]
135; GCN-IR-NEXT:    s_sub_u32 s12, s10, s18
136; GCN-IR-NEXT:    s_subb_u32 s13, 0, 0
137; GCN-IR-NEXT:    v_cmp_gt_u64_e64 s[14:15], s[12:13], 63
138; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[16:17], s[12:13], 63
139; GCN-IR-NEXT:    s_or_b64 s[14:15], s[8:9], s[14:15]
140; GCN-IR-NEXT:    s_and_b64 s[8:9], s[14:15], exec
141; GCN-IR-NEXT:    s_cselect_b32 s9, 0, s3
142; GCN-IR-NEXT:    s_cselect_b32 s8, 0, s2
143; GCN-IR-NEXT:    s_or_b64 s[14:15], s[14:15], s[16:17]
144; GCN-IR-NEXT:    s_andn2_b64 vcc, exec, s[14:15]
145; GCN-IR-NEXT:    s_cbranch_vccz .LBB0_5
146; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
147; GCN-IR-NEXT:    s_add_u32 s14, s12, 1
148; GCN-IR-NEXT:    s_addc_u32 s15, s13, 0
149; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[8:9], s[14:15], 0
150; GCN-IR-NEXT:    s_sub_i32 s12, 63, s12
151; GCN-IR-NEXT:    s_andn2_b64 vcc, exec, s[8:9]
152; GCN-IR-NEXT:    s_lshl_b64 s[8:9], s[2:3], s12
153; GCN-IR-NEXT:    s_cbranch_vccz .LBB0_4
154; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
155; GCN-IR-NEXT:    s_lshr_b64 s[12:13], s[2:3], s14
156; GCN-IR-NEXT:    s_add_u32 s16, s6, -1
157; GCN-IR-NEXT:    s_addc_u32 s17, s7, -1
158; GCN-IR-NEXT:    s_not_b64 s[4:5], s[10:11]
159; GCN-IR-NEXT:    s_add_u32 s10, s4, s18
160; GCN-IR-NEXT:    s_addc_u32 s11, s5, 0
161; GCN-IR-NEXT:    s_mov_b64 s[14:15], 0
162; GCN-IR-NEXT:    s_mov_b32 s5, 0
163; GCN-IR-NEXT:  .LBB0_3: ; %udiv-do-while
164; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
165; GCN-IR-NEXT:    s_lshl_b64 s[12:13], s[12:13], 1
166; GCN-IR-NEXT:    s_lshr_b32 s4, s9, 31
167; GCN-IR-NEXT:    s_lshl_b64 s[8:9], s[8:9], 1
168; GCN-IR-NEXT:    s_or_b64 s[12:13], s[12:13], s[4:5]
169; GCN-IR-NEXT:    s_or_b64 s[8:9], s[14:15], s[8:9]
170; GCN-IR-NEXT:    s_sub_u32 s4, s16, s12
171; GCN-IR-NEXT:    s_subb_u32 s4, s17, s13
172; GCN-IR-NEXT:    s_ashr_i32 s14, s4, 31
173; GCN-IR-NEXT:    s_mov_b32 s15, s14
174; GCN-IR-NEXT:    s_and_b32 s4, s14, 1
175; GCN-IR-NEXT:    s_and_b64 s[14:15], s[14:15], s[6:7]
176; GCN-IR-NEXT:    s_sub_u32 s12, s12, s14
177; GCN-IR-NEXT:    s_subb_u32 s13, s13, s15
178; GCN-IR-NEXT:    s_add_u32 s10, s10, 1
179; GCN-IR-NEXT:    s_addc_u32 s11, s11, 0
180; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[18:19], s[10:11], 0
181; GCN-IR-NEXT:    s_mov_b64 s[14:15], s[4:5]
182; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[18:19]
183; GCN-IR-NEXT:    s_cbranch_vccz .LBB0_3
184; GCN-IR-NEXT:  .LBB0_4: ; %Flow7
185; GCN-IR-NEXT:    s_lshl_b64 s[8:9], s[8:9], 1
186; GCN-IR-NEXT:    s_or_b64 s[8:9], s[4:5], s[8:9]
187; GCN-IR-NEXT:  .LBB0_5: ; %udiv-end
188; GCN-IR-NEXT:    v_mov_b32_e32 v0, s8
189; GCN-IR-NEXT:    v_mul_hi_u32 v0, s6, v0
190; GCN-IR-NEXT:    s_mov_b32 s12, s0
191; GCN-IR-NEXT:    s_mul_i32 s0, s6, s9
192; GCN-IR-NEXT:    v_mov_b32_e32 v2, s3
193; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, s0, v0
194; GCN-IR-NEXT:    s_mul_i32 s0, s7, s8
195; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, s0, v0
196; GCN-IR-NEXT:    s_mul_i32 s0, s6, s8
197; GCN-IR-NEXT:    v_mov_b32_e32 v0, s0
198; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
199; GCN-IR-NEXT:    s_mov_b32 s15, 0xf000
200; GCN-IR-NEXT:    s_mov_b32 s14, -1
201; GCN-IR-NEXT:    s_mov_b32 s13, s1
202; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v2, v1, vcc
203; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[12:15], 0
204; GCN-IR-NEXT:    s_endpgm
205  %result = urem i64 %x, %y
206  store i64 %result, ptr addrspace(1) %out
207  ret void
208}
209
210define i64 @v_test_srem(i64 %x, i64 %y) {
211; GCN-LABEL: v_test_srem:
212; GCN:       ; %bb.0:
213; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
214; GCN-NEXT:    v_ashrrev_i32_e32 v4, 31, v3
215; GCN-NEXT:    v_add_i32_e32 v5, vcc, v2, v4
216; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v3, v4, vcc
217; GCN-NEXT:    v_xor_b32_e32 v2, v2, v4
218; GCN-NEXT:    v_xor_b32_e32 v3, v5, v4
219; GCN-NEXT:    v_cvt_f32_u32_e32 v4, v3
220; GCN-NEXT:    v_cvt_f32_u32_e32 v5, v2
221; GCN-NEXT:    v_sub_i32_e32 v6, vcc, 0, v3
222; GCN-NEXT:    v_subb_u32_e32 v7, vcc, 0, v2, vcc
223; GCN-NEXT:    v_madmk_f32 v4, v5, 0x4f800000, v4
224; GCN-NEXT:    v_rcp_f32_e32 v4, v4
225; GCN-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v4
226; GCN-NEXT:    v_mul_f32_e32 v5, 0x2f800000, v4
227; GCN-NEXT:    v_trunc_f32_e32 v5, v5
228; GCN-NEXT:    v_madmk_f32 v4, v5, 0xcf800000, v4
229; GCN-NEXT:    v_cvt_u32_f32_e32 v4, v4
230; GCN-NEXT:    v_cvt_u32_f32_e32 v5, v5
231; GCN-NEXT:    v_mul_hi_u32 v8, v6, v4
232; GCN-NEXT:    v_mul_lo_u32 v9, v6, v5
233; GCN-NEXT:    v_mul_lo_u32 v10, v7, v4
234; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
235; GCN-NEXT:    v_mul_lo_u32 v9, v6, v4
236; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
237; GCN-NEXT:    v_mul_lo_u32 v10, v4, v8
238; GCN-NEXT:    v_mul_hi_u32 v11, v4, v9
239; GCN-NEXT:    v_mul_hi_u32 v12, v4, v8
240; GCN-NEXT:    v_mul_hi_u32 v13, v5, v8
241; GCN-NEXT:    v_mul_lo_u32 v8, v5, v8
242; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
243; GCN-NEXT:    v_addc_u32_e32 v11, vcc, 0, v12, vcc
244; GCN-NEXT:    v_mul_lo_u32 v12, v5, v9
245; GCN-NEXT:    v_mul_hi_u32 v9, v5, v9
246; GCN-NEXT:    v_add_i32_e32 v10, vcc, v10, v12
247; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v11, v9, vcc
248; GCN-NEXT:    v_addc_u32_e32 v10, vcc, 0, v13, vcc
249; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
250; GCN-NEXT:    v_addc_u32_e32 v9, vcc, 0, v10, vcc
251; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
252; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v5, v9, vcc
253; GCN-NEXT:    v_mul_lo_u32 v8, v6, v5
254; GCN-NEXT:    v_mul_hi_u32 v9, v6, v4
255; GCN-NEXT:    v_mul_lo_u32 v7, v7, v4
256; GCN-NEXT:    v_mul_lo_u32 v6, v6, v4
257; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
258; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
259; GCN-NEXT:    v_mul_lo_u32 v10, v4, v7
260; GCN-NEXT:    v_mul_hi_u32 v11, v4, v6
261; GCN-NEXT:    v_mul_hi_u32 v12, v4, v7
262; GCN-NEXT:    v_mul_hi_u32 v9, v5, v6
263; GCN-NEXT:    v_mul_lo_u32 v6, v5, v6
264; GCN-NEXT:    v_mul_hi_u32 v8, v5, v7
265; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
266; GCN-NEXT:    v_addc_u32_e32 v11, vcc, 0, v12, vcc
267; GCN-NEXT:    v_mul_lo_u32 v7, v5, v7
268; GCN-NEXT:    v_add_i32_e32 v6, vcc, v10, v6
269; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v11, v9, vcc
270; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v8, vcc
271; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
272; GCN-NEXT:    v_addc_u32_e32 v7, vcc, 0, v8, vcc
273; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
274; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v5, v7, vcc
275; GCN-NEXT:    v_ashrrev_i32_e32 v6, 31, v1
276; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v6
277; GCN-NEXT:    v_xor_b32_e32 v0, v0, v6
278; GCN-NEXT:    v_mul_lo_u32 v7, v0, v5
279; GCN-NEXT:    v_mul_hi_u32 v8, v0, v4
280; GCN-NEXT:    v_mul_hi_u32 v9, v0, v5
281; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v6, vcc
282; GCN-NEXT:    v_xor_b32_e32 v1, v1, v6
283; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
284; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v9, vcc
285; GCN-NEXT:    v_mul_lo_u32 v9, v1, v4
286; GCN-NEXT:    v_mul_hi_u32 v4, v1, v4
287; GCN-NEXT:    v_mul_hi_u32 v10, v1, v5
288; GCN-NEXT:    v_mul_lo_u32 v5, v1, v5
289; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
290; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v8, v4, vcc
291; GCN-NEXT:    v_addc_u32_e32 v7, vcc, 0, v10, vcc
292; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
293; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v7, vcc
294; GCN-NEXT:    v_mul_lo_u32 v5, v3, v5
295; GCN-NEXT:    v_mul_hi_u32 v7, v3, v4
296; GCN-NEXT:    v_mul_lo_u32 v8, v2, v4
297; GCN-NEXT:    v_mul_lo_u32 v4, v3, v4
298; GCN-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
299; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v8
300; GCN-NEXT:    v_sub_i32_e32 v7, vcc, v1, v5
301; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v4
302; GCN-NEXT:    v_subb_u32_e64 v4, s[4:5], v7, v2, vcc
303; GCN-NEXT:    v_sub_i32_e64 v7, s[4:5], v0, v3
304; GCN-NEXT:    v_subbrev_u32_e64 v8, s[6:7], 0, v4, s[4:5]
305; GCN-NEXT:    v_cmp_ge_u32_e64 s[6:7], v8, v2
306; GCN-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[6:7]
307; GCN-NEXT:    v_cmp_ge_u32_e64 s[6:7], v7, v3
308; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v5, vcc
309; GCN-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s[6:7]
310; GCN-NEXT:    v_cmp_eq_u32_e64 s[6:7], v8, v2
311; GCN-NEXT:    v_subb_u32_e64 v4, s[4:5], v4, v2, s[4:5]
312; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v1, v2
313; GCN-NEXT:    v_cndmask_b32_e64 v9, v9, v10, s[6:7]
314; GCN-NEXT:    v_sub_i32_e64 v10, s[4:5], v7, v3
315; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
316; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v3
317; GCN-NEXT:    v_subbrev_u32_e64 v4, s[4:5], 0, v4, s[4:5]
318; GCN-NEXT:    v_cndmask_b32_e64 v3, 0, -1, vcc
319; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v1, v2
320; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v9
321; GCN-NEXT:    v_cndmask_b32_e32 v2, v5, v3, vcc
322; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
323; GCN-NEXT:    v_cndmask_b32_e64 v2, v7, v10, s[4:5]
324; GCN-NEXT:    v_cndmask_b32_e64 v4, v8, v4, s[4:5]
325; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
326; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
327; GCN-NEXT:    v_xor_b32_e32 v0, v0, v6
328; GCN-NEXT:    v_xor_b32_e32 v1, v1, v6
329; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v6
330; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v6, vcc
331; GCN-NEXT:    s_setpc_b64 s[30:31]
332;
333; GCN-IR-LABEL: v_test_srem:
334; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
335; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
336; GCN-IR-NEXT:    v_ashrrev_i32_e32 v14, 31, v1
337; GCN-IR-NEXT:    v_xor_b32_e32 v0, v0, v14
338; GCN-IR-NEXT:    v_xor_b32_e32 v1, v1, v14
339; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v14
340; GCN-IR-NEXT:    v_ashrrev_i32_e32 v4, 31, v3
341; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v14, vcc
342; GCN-IR-NEXT:    v_xor_b32_e32 v2, v2, v4
343; GCN-IR-NEXT:    v_xor_b32_e32 v3, v3, v4
344; GCN-IR-NEXT:    v_sub_i32_e32 v2, vcc, v2, v4
345; GCN-IR-NEXT:    v_subb_u32_e32 v3, vcc, v3, v4, vcc
346; GCN-IR-NEXT:    v_ffbh_u32_e32 v4, v2
347; GCN-IR-NEXT:    v_add_i32_e64 v4, s[6:7], 32, v4
348; GCN-IR-NEXT:    v_ffbh_u32_e32 v5, v3
349; GCN-IR-NEXT:    v_min_u32_e32 v12, v4, v5
350; GCN-IR-NEXT:    v_ffbh_u32_e32 v4, v0
351; GCN-IR-NEXT:    v_add_i32_e64 v4, s[6:7], 32, v4
352; GCN-IR-NEXT:    v_ffbh_u32_e32 v5, v1
353; GCN-IR-NEXT:    v_min_u32_e32 v13, v4, v5
354; GCN-IR-NEXT:    v_sub_i32_e64 v4, s[6:7], v12, v13
355; GCN-IR-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[2:3]
356; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
357; GCN-IR-NEXT:    v_subb_u32_e64 v5, s[6:7], 0, 0, s[6:7]
358; GCN-IR-NEXT:    v_cmp_lt_u64_e64 s[6:7], 63, v[4:5]
359; GCN-IR-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
360; GCN-IR-NEXT:    s_or_b64 s[4:5], s[4:5], s[6:7]
361; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[4:5]
362; GCN-IR-NEXT:    s_xor_b64 s[6:7], s[4:5], -1
363; GCN-IR-NEXT:    v_mov_b32_e32 v15, v14
364; GCN-IR-NEXT:    v_cndmask_b32_e64 v7, v1, 0, s[4:5]
365; GCN-IR-NEXT:    v_cndmask_b32_e64 v6, v0, 0, s[4:5]
366; GCN-IR-NEXT:    s_and_b64 s[4:5], s[6:7], vcc
367; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
368; GCN-IR-NEXT:    s_cbranch_execz .LBB1_6
369; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
370; GCN-IR-NEXT:    v_add_i32_e32 v8, vcc, 1, v4
371; GCN-IR-NEXT:    v_addc_u32_e32 v9, vcc, 0, v5, vcc
372; GCN-IR-NEXT:    v_sub_i32_e64 v4, s[4:5], 63, v4
373; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 0, v[8:9]
374; GCN-IR-NEXT:    v_lshl_b64 v[4:5], v[0:1], v4
375; GCN-IR-NEXT:    v_mov_b32_e32 v6, 0
376; GCN-IR-NEXT:    v_mov_b32_e32 v7, 0
377; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
378; GCN-IR-NEXT:    s_xor_b64 s[8:9], exec, s[4:5]
379; GCN-IR-NEXT:    s_cbranch_execz .LBB1_5
380; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
381; GCN-IR-NEXT:    v_add_i32_e32 v16, vcc, -1, v2
382; GCN-IR-NEXT:    v_addc_u32_e32 v17, vcc, -1, v3, vcc
383; GCN-IR-NEXT:    v_not_b32_e32 v7, v12
384; GCN-IR-NEXT:    v_lshr_b64 v[10:11], v[0:1], v8
385; GCN-IR-NEXT:    v_not_b32_e32 v6, 0
386; GCN-IR-NEXT:    v_add_i32_e32 v8, vcc, v7, v13
387; GCN-IR-NEXT:    v_mov_b32_e32 v12, 0
388; GCN-IR-NEXT:    v_addc_u32_e32 v9, vcc, 0, v6, vcc
389; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
390; GCN-IR-NEXT:    v_mov_b32_e32 v13, 0
391; GCN-IR-NEXT:    v_mov_b32_e32 v7, 0
392; GCN-IR-NEXT:  .LBB1_3: ; %udiv-do-while
393; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
394; GCN-IR-NEXT:    v_lshl_b64 v[10:11], v[10:11], 1
395; GCN-IR-NEXT:    v_lshrrev_b32_e32 v6, 31, v5
396; GCN-IR-NEXT:    v_or_b32_e32 v10, v10, v6
397; GCN-IR-NEXT:    v_lshl_b64 v[4:5], v[4:5], 1
398; GCN-IR-NEXT:    v_sub_i32_e32 v6, vcc, v16, v10
399; GCN-IR-NEXT:    v_subb_u32_e32 v6, vcc, v17, v11, vcc
400; GCN-IR-NEXT:    v_or_b32_e32 v4, v12, v4
401; GCN-IR-NEXT:    v_ashrrev_i32_e32 v12, 31, v6
402; GCN-IR-NEXT:    v_add_i32_e32 v8, vcc, 1, v8
403; GCN-IR-NEXT:    v_or_b32_e32 v5, v13, v5
404; GCN-IR-NEXT:    v_and_b32_e32 v6, 1, v12
405; GCN-IR-NEXT:    v_and_b32_e32 v13, v12, v3
406; GCN-IR-NEXT:    v_and_b32_e32 v12, v12, v2
407; GCN-IR-NEXT:    v_addc_u32_e32 v9, vcc, 0, v9, vcc
408; GCN-IR-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[8:9]
409; GCN-IR-NEXT:    v_sub_i32_e64 v10, s[4:5], v10, v12
410; GCN-IR-NEXT:    v_subb_u32_e64 v11, s[4:5], v11, v13, s[4:5]
411; GCN-IR-NEXT:    v_mov_b32_e32 v13, v7
412; GCN-IR-NEXT:    s_or_b64 s[10:11], vcc, s[10:11]
413; GCN-IR-NEXT:    v_mov_b32_e32 v12, v6
414; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[10:11]
415; GCN-IR-NEXT:    s_cbranch_execnz .LBB1_3
416; GCN-IR-NEXT:  ; %bb.4: ; %Flow
417; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
418; GCN-IR-NEXT:  .LBB1_5: ; %Flow4
419; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
420; GCN-IR-NEXT:    v_lshl_b64 v[4:5], v[4:5], 1
421; GCN-IR-NEXT:    v_or_b32_e32 v7, v7, v5
422; GCN-IR-NEXT:    v_or_b32_e32 v6, v6, v4
423; GCN-IR-NEXT:  .LBB1_6: ; %Flow5
424; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
425; GCN-IR-NEXT:    v_mul_lo_u32 v4, v2, v7
426; GCN-IR-NEXT:    v_mul_hi_u32 v5, v2, v6
427; GCN-IR-NEXT:    v_mul_lo_u32 v3, v3, v6
428; GCN-IR-NEXT:    v_mul_lo_u32 v2, v2, v6
429; GCN-IR-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
430; GCN-IR-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
431; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
432; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v3, vcc
433; GCN-IR-NEXT:    v_xor_b32_e32 v0, v0, v14
434; GCN-IR-NEXT:    v_xor_b32_e32 v1, v1, v15
435; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v14
436; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v15, vcc
437; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
438  %result = srem i64 %x, %y
439  ret i64 %result
440}
441
442define amdgpu_kernel void @s_test_srem23_64(ptr addrspace(1) %out, i64 %x, i64 %y) {
443; GCN-LABEL: s_test_srem23_64:
444; GCN:       ; %bb.0:
445; GCN-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x9
446; GCN-NEXT:    s_load_dword s5, s[4:5], 0xe
447; GCN-NEXT:    s_mov_b32 s7, 0xf000
448; GCN-NEXT:    s_mov_b32 s6, -1
449; GCN-NEXT:    s_waitcnt lgkmcnt(0)
450; GCN-NEXT:    s_mov_b32 s4, s0
451; GCN-NEXT:    s_ashr_i64 s[8:9], s[4:5], 41
452; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s8
453; GCN-NEXT:    s_mov_b32 s5, s1
454; GCN-NEXT:    s_ashr_i64 s[0:1], s[2:3], 41
455; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s0
456; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
457; GCN-NEXT:    s_xor_b32 s1, s0, s8
458; GCN-NEXT:    s_ashr_i32 s1, s1, 30
459; GCN-NEXT:    s_or_b32 s1, s1, 1
460; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
461; GCN-NEXT:    v_trunc_f32_e32 v2, v2
462; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
463; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
464; GCN-NEXT:    v_cmp_ge_f32_e64 s[2:3], |v1|, |v0|
465; GCN-NEXT:    s_and_b64 s[2:3], s[2:3], exec
466; GCN-NEXT:    s_cselect_b32 s1, s1, 0
467; GCN-NEXT:    v_readfirstlane_b32 s2, v2
468; GCN-NEXT:    s_add_i32 s1, s2, s1
469; GCN-NEXT:    s_mul_i32 s1, s1, s8
470; GCN-NEXT:    s_sub_i32 s0, s0, s1
471; GCN-NEXT:    s_bfe_i32 s0, s0, 0x170000
472; GCN-NEXT:    s_ashr_i32 s1, s0, 31
473; GCN-NEXT:    v_mov_b32_e32 v0, s0
474; GCN-NEXT:    v_mov_b32_e32 v1, s1
475; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
476; GCN-NEXT:    s_endpgm
477;
478; GCN-IR-LABEL: s_test_srem23_64:
479; GCN-IR:       ; %bb.0:
480; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x9
481; GCN-IR-NEXT:    s_load_dword s5, s[4:5], 0xe
482; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
483; GCN-IR-NEXT:    s_mov_b32 s6, -1
484; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
485; GCN-IR-NEXT:    s_mov_b32 s4, s0
486; GCN-IR-NEXT:    s_ashr_i64 s[8:9], s[4:5], 41
487; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s8
488; GCN-IR-NEXT:    s_mov_b32 s5, s1
489; GCN-IR-NEXT:    s_ashr_i64 s[0:1], s[2:3], 41
490; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, s0
491; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
492; GCN-IR-NEXT:    s_xor_b32 s1, s0, s8
493; GCN-IR-NEXT:    s_ashr_i32 s1, s1, 30
494; GCN-IR-NEXT:    s_or_b32 s1, s1, 1
495; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
496; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
497; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
498; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
499; GCN-IR-NEXT:    v_cmp_ge_f32_e64 s[2:3], |v1|, |v0|
500; GCN-IR-NEXT:    s_and_b64 s[2:3], s[2:3], exec
501; GCN-IR-NEXT:    s_cselect_b32 s1, s1, 0
502; GCN-IR-NEXT:    v_readfirstlane_b32 s2, v2
503; GCN-IR-NEXT:    s_add_i32 s1, s2, s1
504; GCN-IR-NEXT:    s_mul_i32 s1, s1, s8
505; GCN-IR-NEXT:    s_sub_i32 s0, s0, s1
506; GCN-IR-NEXT:    s_bfe_i32 s0, s0, 0x170000
507; GCN-IR-NEXT:    s_ashr_i32 s1, s0, 31
508; GCN-IR-NEXT:    v_mov_b32_e32 v0, s0
509; GCN-IR-NEXT:    v_mov_b32_e32 v1, s1
510; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
511; GCN-IR-NEXT:    s_endpgm
512  %1 = ashr i64 %x, 41
513  %2 = ashr i64 %y, 41
514  %result = srem i64 %1, %2
515  store i64 %result, ptr addrspace(1) %out
516  ret void
517}
518
519define amdgpu_kernel void @s_test_srem24_64(ptr addrspace(1) %out, i64 %x, i64 %y) {
520; GCN-LABEL: s_test_srem24_64:
521; GCN:       ; %bb.0:
522; GCN-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x9
523; GCN-NEXT:    s_load_dword s5, s[4:5], 0xe
524; GCN-NEXT:    s_mov_b32 s7, 0xf000
525; GCN-NEXT:    s_mov_b32 s6, -1
526; GCN-NEXT:    s_waitcnt lgkmcnt(0)
527; GCN-NEXT:    s_mov_b32 s4, s0
528; GCN-NEXT:    s_ashr_i64 s[8:9], s[4:5], 40
529; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s8
530; GCN-NEXT:    s_mov_b32 s5, s1
531; GCN-NEXT:    s_ashr_i64 s[0:1], s[2:3], 40
532; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s0
533; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
534; GCN-NEXT:    s_xor_b32 s1, s0, s8
535; GCN-NEXT:    s_ashr_i32 s1, s1, 30
536; GCN-NEXT:    s_or_b32 s1, s1, 1
537; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
538; GCN-NEXT:    v_trunc_f32_e32 v2, v2
539; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
540; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
541; GCN-NEXT:    v_cmp_ge_f32_e64 s[2:3], |v1|, |v0|
542; GCN-NEXT:    s_and_b64 s[2:3], s[2:3], exec
543; GCN-NEXT:    s_cselect_b32 s1, s1, 0
544; GCN-NEXT:    v_readfirstlane_b32 s2, v2
545; GCN-NEXT:    s_add_i32 s1, s2, s1
546; GCN-NEXT:    s_mul_i32 s1, s1, s8
547; GCN-NEXT:    s_sub_i32 s0, s0, s1
548; GCN-NEXT:    s_bfe_i32 s0, s0, 0x180000
549; GCN-NEXT:    s_ashr_i32 s1, s0, 31
550; GCN-NEXT:    v_mov_b32_e32 v0, s0
551; GCN-NEXT:    v_mov_b32_e32 v1, s1
552; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
553; GCN-NEXT:    s_endpgm
554;
555; GCN-IR-LABEL: s_test_srem24_64:
556; GCN-IR:       ; %bb.0:
557; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x9
558; GCN-IR-NEXT:    s_load_dword s5, s[4:5], 0xe
559; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
560; GCN-IR-NEXT:    s_mov_b32 s6, -1
561; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
562; GCN-IR-NEXT:    s_mov_b32 s4, s0
563; GCN-IR-NEXT:    s_ashr_i64 s[8:9], s[4:5], 40
564; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s8
565; GCN-IR-NEXT:    s_mov_b32 s5, s1
566; GCN-IR-NEXT:    s_ashr_i64 s[0:1], s[2:3], 40
567; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, s0
568; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
569; GCN-IR-NEXT:    s_xor_b32 s1, s0, s8
570; GCN-IR-NEXT:    s_ashr_i32 s1, s1, 30
571; GCN-IR-NEXT:    s_or_b32 s1, s1, 1
572; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
573; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
574; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
575; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
576; GCN-IR-NEXT:    v_cmp_ge_f32_e64 s[2:3], |v1|, |v0|
577; GCN-IR-NEXT:    s_and_b64 s[2:3], s[2:3], exec
578; GCN-IR-NEXT:    s_cselect_b32 s1, s1, 0
579; GCN-IR-NEXT:    v_readfirstlane_b32 s2, v2
580; GCN-IR-NEXT:    s_add_i32 s1, s2, s1
581; GCN-IR-NEXT:    s_mul_i32 s1, s1, s8
582; GCN-IR-NEXT:    s_sub_i32 s0, s0, s1
583; GCN-IR-NEXT:    s_bfe_i32 s0, s0, 0x180000
584; GCN-IR-NEXT:    s_ashr_i32 s1, s0, 31
585; GCN-IR-NEXT:    v_mov_b32_e32 v0, s0
586; GCN-IR-NEXT:    v_mov_b32_e32 v1, s1
587; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
588; GCN-IR-NEXT:    s_endpgm
589  %1 = ashr i64 %x, 40
590  %2 = ashr i64 %y, 40
591  %result = srem i64 %1, %2
592  store i64 %result, ptr addrspace(1) %out
593  ret void
594}
595
596define i64 @v_test_srem24_64(i64 %x, i64 %y) {
597; GCN-LABEL: v_test_srem24_64:
598; GCN:       ; %bb.0:
599; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
600; GCN-NEXT:    v_ashr_i64 v[2:3], v[2:3], 40
601; GCN-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
602; GCN-NEXT:    v_cvt_f32_i32_e32 v3, v2
603; GCN-NEXT:    v_cvt_f32_i32_e32 v1, v0
604; GCN-NEXT:    v_xor_b32_e32 v5, v0, v2
605; GCN-NEXT:    v_ashrrev_i32_e32 v5, 30, v5
606; GCN-NEXT:    v_rcp_iflag_f32_e32 v4, v3
607; GCN-NEXT:    v_or_b32_e32 v5, 1, v5
608; GCN-NEXT:    v_mul_f32_e32 v4, v1, v4
609; GCN-NEXT:    v_trunc_f32_e32 v4, v4
610; GCN-NEXT:    v_mad_f32 v1, -v4, v3, v1
611; GCN-NEXT:    v_cvt_i32_f32_e32 v4, v4
612; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v3|
613; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v5, vcc
614; GCN-NEXT:    v_add_i32_e32 v1, vcc, v4, v1
615; GCN-NEXT:    v_mul_lo_u32 v1, v1, v2
616; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v1
617; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
618; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
619; GCN-NEXT:    s_setpc_b64 s[30:31]
620;
621; GCN-IR-LABEL: v_test_srem24_64:
622; GCN-IR:       ; %bb.0:
623; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
624; GCN-IR-NEXT:    v_ashr_i64 v[2:3], v[2:3], 40
625; GCN-IR-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
626; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v3, v2
627; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, v0
628; GCN-IR-NEXT:    v_xor_b32_e32 v5, v0, v2
629; GCN-IR-NEXT:    v_ashrrev_i32_e32 v5, 30, v5
630; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v4, v3
631; GCN-IR-NEXT:    v_or_b32_e32 v5, 1, v5
632; GCN-IR-NEXT:    v_mul_f32_e32 v4, v1, v4
633; GCN-IR-NEXT:    v_trunc_f32_e32 v4, v4
634; GCN-IR-NEXT:    v_mad_f32 v1, -v4, v3, v1
635; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v4, v4
636; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v3|
637; GCN-IR-NEXT:    v_cndmask_b32_e32 v1, 0, v5, vcc
638; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v4, v1
639; GCN-IR-NEXT:    v_mul_lo_u32 v1, v1, v2
640; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v1
641; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
642; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
643; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
644  %1 = ashr i64 %x, 40
645  %2 = ashr i64 %y, 40
646  %result = srem i64 %1, %2
647  ret i64 %result
648}
649
650define amdgpu_kernel void @s_test_srem25_64(ptr addrspace(1) %out, i64 %x, i64 %y) {
651; GCN-LABEL: s_test_srem25_64:
652; GCN:       ; %bb.0:
653; GCN-NEXT:    s_load_dword s1, s[4:5], 0xe
654; GCN-NEXT:    s_mov_b32 s7, 0xf000
655; GCN-NEXT:    s_mov_b32 s6, -1
656; GCN-NEXT:    s_waitcnt lgkmcnt(0)
657; GCN-NEXT:    s_ashr_i64 s[0:1], s[0:1], 39
658; GCN-NEXT:    s_abs_i32 s8, s0
659; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s8
660; GCN-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x9
661; GCN-NEXT:    s_waitcnt lgkmcnt(0)
662; GCN-NEXT:    s_sub_i32 s2, 0, s8
663; GCN-NEXT:    v_rcp_iflag_f32_e32 v0, v0
664; GCN-NEXT:    s_mov_b32 s5, s1
665; GCN-NEXT:    s_mov_b32 s4, s0
666; GCN-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
667; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
668; GCN-NEXT:    v_mul_lo_u32 v1, s2, v0
669; GCN-NEXT:    s_ashr_i64 s[2:3], s[2:3], 39
670; GCN-NEXT:    s_abs_i32 s3, s2
671; GCN-NEXT:    s_ashr_i32 s0, s2, 31
672; GCN-NEXT:    v_mul_hi_u32 v1, v0, v1
673; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
674; GCN-NEXT:    v_mul_hi_u32 v0, s3, v0
675; GCN-NEXT:    v_readfirstlane_b32 s1, v0
676; GCN-NEXT:    s_mul_i32 s1, s1, s8
677; GCN-NEXT:    s_sub_i32 s1, s3, s1
678; GCN-NEXT:    s_sub_i32 s2, s1, s8
679; GCN-NEXT:    s_cmp_ge_u32 s1, s8
680; GCN-NEXT:    s_cselect_b32 s1, s2, s1
681; GCN-NEXT:    s_sub_i32 s2, s1, s8
682; GCN-NEXT:    s_cmp_ge_u32 s1, s8
683; GCN-NEXT:    s_cselect_b32 s1, s2, s1
684; GCN-NEXT:    s_xor_b32 s1, s1, s0
685; GCN-NEXT:    s_sub_i32 s0, s1, s0
686; GCN-NEXT:    s_ashr_i32 s1, s0, 31
687; GCN-NEXT:    v_mov_b32_e32 v0, s0
688; GCN-NEXT:    v_mov_b32_e32 v1, s1
689; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
690; GCN-NEXT:    s_endpgm
691;
692; GCN-IR-LABEL: s_test_srem25_64:
693; GCN-IR:       ; %bb.0:
694; GCN-IR-NEXT:    s_load_dword s1, s[4:5], 0xe
695; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
696; GCN-IR-NEXT:    s_mov_b32 s6, -1
697; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
698; GCN-IR-NEXT:    s_ashr_i64 s[0:1], s[0:1], 39
699; GCN-IR-NEXT:    s_abs_i32 s8, s0
700; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s8
701; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x9
702; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
703; GCN-IR-NEXT:    s_sub_i32 s2, 0, s8
704; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v0, v0
705; GCN-IR-NEXT:    s_mov_b32 s5, s1
706; GCN-IR-NEXT:    s_mov_b32 s4, s0
707; GCN-IR-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
708; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v0, v0
709; GCN-IR-NEXT:    v_mul_lo_u32 v1, s2, v0
710; GCN-IR-NEXT:    s_ashr_i64 s[2:3], s[2:3], 39
711; GCN-IR-NEXT:    s_abs_i32 s3, s2
712; GCN-IR-NEXT:    s_ashr_i32 s0, s2, 31
713; GCN-IR-NEXT:    v_mul_hi_u32 v1, v0, v1
714; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
715; GCN-IR-NEXT:    v_mul_hi_u32 v0, s3, v0
716; GCN-IR-NEXT:    v_readfirstlane_b32 s1, v0
717; GCN-IR-NEXT:    s_mul_i32 s1, s1, s8
718; GCN-IR-NEXT:    s_sub_i32 s1, s3, s1
719; GCN-IR-NEXT:    s_sub_i32 s2, s1, s8
720; GCN-IR-NEXT:    s_cmp_ge_u32 s1, s8
721; GCN-IR-NEXT:    s_cselect_b32 s1, s2, s1
722; GCN-IR-NEXT:    s_sub_i32 s2, s1, s8
723; GCN-IR-NEXT:    s_cmp_ge_u32 s1, s8
724; GCN-IR-NEXT:    s_cselect_b32 s1, s2, s1
725; GCN-IR-NEXT:    s_xor_b32 s1, s1, s0
726; GCN-IR-NEXT:    s_sub_i32 s0, s1, s0
727; GCN-IR-NEXT:    s_ashr_i32 s1, s0, 31
728; GCN-IR-NEXT:    v_mov_b32_e32 v0, s0
729; GCN-IR-NEXT:    v_mov_b32_e32 v1, s1
730; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
731; GCN-IR-NEXT:    s_endpgm
732  %1 = ashr i64 %x, 39
733  %2 = ashr i64 %y, 39
734  %result = srem i64 %1, %2
735  store i64 %result, ptr addrspace(1) %out
736  ret void
737}
738
739define amdgpu_kernel void @s_test_srem31_64(ptr addrspace(1) %out, i64 %x, i64 %y) {
740; GCN-LABEL: s_test_srem31_64:
741; GCN:       ; %bb.0:
742; GCN-NEXT:    s_load_dword s1, s[4:5], 0xe
743; GCN-NEXT:    s_mov_b32 s7, 0xf000
744; GCN-NEXT:    s_mov_b32 s6, -1
745; GCN-NEXT:    s_waitcnt lgkmcnt(0)
746; GCN-NEXT:    s_ashr_i64 s[0:1], s[0:1], 33
747; GCN-NEXT:    s_abs_i32 s8, s0
748; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s8
749; GCN-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x9
750; GCN-NEXT:    s_waitcnt lgkmcnt(0)
751; GCN-NEXT:    s_sub_i32 s2, 0, s8
752; GCN-NEXT:    v_rcp_iflag_f32_e32 v0, v0
753; GCN-NEXT:    s_mov_b32 s5, s1
754; GCN-NEXT:    s_mov_b32 s4, s0
755; GCN-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
756; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
757; GCN-NEXT:    v_mul_lo_u32 v1, s2, v0
758; GCN-NEXT:    s_ashr_i64 s[2:3], s[2:3], 33
759; GCN-NEXT:    s_abs_i32 s3, s2
760; GCN-NEXT:    s_ashr_i32 s0, s2, 31
761; GCN-NEXT:    v_mul_hi_u32 v1, v0, v1
762; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
763; GCN-NEXT:    v_mul_hi_u32 v0, s3, v0
764; GCN-NEXT:    v_readfirstlane_b32 s1, v0
765; GCN-NEXT:    s_mul_i32 s1, s1, s8
766; GCN-NEXT:    s_sub_i32 s1, s3, s1
767; GCN-NEXT:    s_sub_i32 s2, s1, s8
768; GCN-NEXT:    s_cmp_ge_u32 s1, s8
769; GCN-NEXT:    s_cselect_b32 s1, s2, s1
770; GCN-NEXT:    s_sub_i32 s2, s1, s8
771; GCN-NEXT:    s_cmp_ge_u32 s1, s8
772; GCN-NEXT:    s_cselect_b32 s1, s2, s1
773; GCN-NEXT:    s_xor_b32 s1, s1, s0
774; GCN-NEXT:    s_sub_i32 s0, s1, s0
775; GCN-NEXT:    s_ashr_i32 s1, s0, 31
776; GCN-NEXT:    v_mov_b32_e32 v0, s0
777; GCN-NEXT:    v_mov_b32_e32 v1, s1
778; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
779; GCN-NEXT:    s_endpgm
780;
781; GCN-IR-LABEL: s_test_srem31_64:
782; GCN-IR:       ; %bb.0:
783; GCN-IR-NEXT:    s_load_dword s1, s[4:5], 0xe
784; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
785; GCN-IR-NEXT:    s_mov_b32 s6, -1
786; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
787; GCN-IR-NEXT:    s_ashr_i64 s[0:1], s[0:1], 33
788; GCN-IR-NEXT:    s_abs_i32 s8, s0
789; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s8
790; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x9
791; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
792; GCN-IR-NEXT:    s_sub_i32 s2, 0, s8
793; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v0, v0
794; GCN-IR-NEXT:    s_mov_b32 s5, s1
795; GCN-IR-NEXT:    s_mov_b32 s4, s0
796; GCN-IR-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
797; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v0, v0
798; GCN-IR-NEXT:    v_mul_lo_u32 v1, s2, v0
799; GCN-IR-NEXT:    s_ashr_i64 s[2:3], s[2:3], 33
800; GCN-IR-NEXT:    s_abs_i32 s3, s2
801; GCN-IR-NEXT:    s_ashr_i32 s0, s2, 31
802; GCN-IR-NEXT:    v_mul_hi_u32 v1, v0, v1
803; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
804; GCN-IR-NEXT:    v_mul_hi_u32 v0, s3, v0
805; GCN-IR-NEXT:    v_readfirstlane_b32 s1, v0
806; GCN-IR-NEXT:    s_mul_i32 s1, s1, s8
807; GCN-IR-NEXT:    s_sub_i32 s1, s3, s1
808; GCN-IR-NEXT:    s_sub_i32 s2, s1, s8
809; GCN-IR-NEXT:    s_cmp_ge_u32 s1, s8
810; GCN-IR-NEXT:    s_cselect_b32 s1, s2, s1
811; GCN-IR-NEXT:    s_sub_i32 s2, s1, s8
812; GCN-IR-NEXT:    s_cmp_ge_u32 s1, s8
813; GCN-IR-NEXT:    s_cselect_b32 s1, s2, s1
814; GCN-IR-NEXT:    s_xor_b32 s1, s1, s0
815; GCN-IR-NEXT:    s_sub_i32 s0, s1, s0
816; GCN-IR-NEXT:    s_ashr_i32 s1, s0, 31
817; GCN-IR-NEXT:    v_mov_b32_e32 v0, s0
818; GCN-IR-NEXT:    v_mov_b32_e32 v1, s1
819; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
820; GCN-IR-NEXT:    s_endpgm
821  %1 = ashr i64 %x, 33
822  %2 = ashr i64 %y, 33
823  %result = srem i64 %1, %2
824  store i64 %result, ptr addrspace(1) %out
825  ret void
826}
827
828; 32 known sign bits
829define amdgpu_kernel void @s_test_srem32_64(ptr addrspace(1) %out, i64 %x, i64 %y) {
830; GCN-LABEL: s_test_srem32_64:
831; GCN:       ; %bb.0:
832; GCN-NEXT:    s_load_dword s0, s[4:5], 0xe
833; GCN-NEXT:    s_mov_b32 s7, 0xf000
834; GCN-NEXT:    s_mov_b32 s6, -1
835; GCN-NEXT:    s_waitcnt lgkmcnt(0)
836; GCN-NEXT:    s_abs_i32 s8, s0
837; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s8
838; GCN-NEXT:    s_sub_i32 s0, 0, s8
839; GCN-NEXT:    v_rcp_iflag_f32_e32 v0, v0
840; GCN-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
841; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
842; GCN-NEXT:    v_mul_lo_u32 v1, s0, v0
843; GCN-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x9
844; GCN-NEXT:    v_mul_hi_u32 v1, v0, v1
845; GCN-NEXT:    s_waitcnt lgkmcnt(0)
846; GCN-NEXT:    s_abs_i32 s2, s3
847; GCN-NEXT:    s_mov_b32 s5, s1
848; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
849; GCN-NEXT:    v_mul_hi_u32 v0, s2, v0
850; GCN-NEXT:    s_mov_b32 s4, s0
851; GCN-NEXT:    s_ashr_i32 s0, s3, 31
852; GCN-NEXT:    v_readfirstlane_b32 s1, v0
853; GCN-NEXT:    s_mul_i32 s1, s1, s8
854; GCN-NEXT:    s_sub_i32 s1, s2, s1
855; GCN-NEXT:    s_sub_i32 s2, s1, s8
856; GCN-NEXT:    s_cmp_ge_u32 s1, s8
857; GCN-NEXT:    s_cselect_b32 s1, s2, s1
858; GCN-NEXT:    s_sub_i32 s2, s1, s8
859; GCN-NEXT:    s_cmp_ge_u32 s1, s8
860; GCN-NEXT:    s_cselect_b32 s1, s2, s1
861; GCN-NEXT:    s_xor_b32 s1, s1, s0
862; GCN-NEXT:    s_sub_i32 s0, s1, s0
863; GCN-NEXT:    s_ashr_i32 s1, s0, 31
864; GCN-NEXT:    v_mov_b32_e32 v0, s0
865; GCN-NEXT:    v_mov_b32_e32 v1, s1
866; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
867; GCN-NEXT:    s_endpgm
868;
869; GCN-IR-LABEL: s_test_srem32_64:
870; GCN-IR:       ; %bb.0:
871; GCN-IR-NEXT:    s_load_dword s0, s[4:5], 0xe
872; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
873; GCN-IR-NEXT:    s_mov_b32 s6, -1
874; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
875; GCN-IR-NEXT:    s_abs_i32 s8, s0
876; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s8
877; GCN-IR-NEXT:    s_sub_i32 s0, 0, s8
878; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v0, v0
879; GCN-IR-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
880; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v0, v0
881; GCN-IR-NEXT:    v_mul_lo_u32 v1, s0, v0
882; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x9
883; GCN-IR-NEXT:    v_mul_hi_u32 v1, v0, v1
884; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
885; GCN-IR-NEXT:    s_abs_i32 s2, s3
886; GCN-IR-NEXT:    s_mov_b32 s5, s1
887; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
888; GCN-IR-NEXT:    v_mul_hi_u32 v0, s2, v0
889; GCN-IR-NEXT:    s_mov_b32 s4, s0
890; GCN-IR-NEXT:    s_ashr_i32 s0, s3, 31
891; GCN-IR-NEXT:    v_readfirstlane_b32 s1, v0
892; GCN-IR-NEXT:    s_mul_i32 s1, s1, s8
893; GCN-IR-NEXT:    s_sub_i32 s1, s2, s1
894; GCN-IR-NEXT:    s_sub_i32 s2, s1, s8
895; GCN-IR-NEXT:    s_cmp_ge_u32 s1, s8
896; GCN-IR-NEXT:    s_cselect_b32 s1, s2, s1
897; GCN-IR-NEXT:    s_sub_i32 s2, s1, s8
898; GCN-IR-NEXT:    s_cmp_ge_u32 s1, s8
899; GCN-IR-NEXT:    s_cselect_b32 s1, s2, s1
900; GCN-IR-NEXT:    s_xor_b32 s1, s1, s0
901; GCN-IR-NEXT:    s_sub_i32 s0, s1, s0
902; GCN-IR-NEXT:    s_ashr_i32 s1, s0, 31
903; GCN-IR-NEXT:    v_mov_b32_e32 v0, s0
904; GCN-IR-NEXT:    v_mov_b32_e32 v1, s1
905; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
906; GCN-IR-NEXT:    s_endpgm
907  %1 = ashr i64 %x, 32
908  %2 = ashr i64 %y, 32
909  %result = srem i64 %1, %2
910  store i64 %result, ptr addrspace(1) %out
911  ret void
912}
913
914; 33 known sign bits
915define amdgpu_kernel void @s_test_srem33_64(ptr addrspace(1) %out, i64 %x, i64 %y) {
916; GCN-LABEL: s_test_srem33_64:
917; GCN:       ; %bb.0:
918; GCN-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x9
919; GCN-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0xd
920; GCN-NEXT:    s_waitcnt lgkmcnt(0)
921; GCN-NEXT:    s_ashr_i64 s[10:11], s[2:3], 31
922; GCN-NEXT:    s_ashr_i64 s[6:7], s[4:5], 31
923; GCN-NEXT:    s_ashr_i32 s4, s5, 31
924; GCN-NEXT:    s_add_u32 s6, s6, s4
925; GCN-NEXT:    s_mov_b32 s5, s4
926; GCN-NEXT:    s_addc_u32 s7, s7, s4
927; GCN-NEXT:    s_xor_b64 s[8:9], s[6:7], s[4:5]
928; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s8
929; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s9
930; GCN-NEXT:    s_sub_u32 s2, 0, s8
931; GCN-NEXT:    s_subb_u32 s4, 0, s9
932; GCN-NEXT:    s_ashr_i32 s12, s3, 31
933; GCN-NEXT:    v_madmk_f32 v0, v1, 0x4f800000, v0
934; GCN-NEXT:    v_rcp_f32_e32 v0, v0
935; GCN-NEXT:    s_mov_b32 s13, s12
936; GCN-NEXT:    s_mov_b32 s5, s1
937; GCN-NEXT:    s_mov_b32 s7, 0xf000
938; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
939; GCN-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
940; GCN-NEXT:    v_trunc_f32_e32 v1, v1
941; GCN-NEXT:    v_madmk_f32 v0, v1, 0xcf800000, v0
942; GCN-NEXT:    v_cvt_u32_f32_e32 v1, v1
943; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
944; GCN-NEXT:    s_mov_b32 s6, -1
945; GCN-NEXT:    v_mul_lo_u32 v2, s2, v1
946; GCN-NEXT:    v_mul_hi_u32 v3, s2, v0
947; GCN-NEXT:    v_mul_lo_u32 v5, s4, v0
948; GCN-NEXT:    v_mul_lo_u32 v4, s2, v0
949; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
950; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
951; GCN-NEXT:    v_mul_hi_u32 v3, v0, v4
952; GCN-NEXT:    v_mul_lo_u32 v5, v0, v2
953; GCN-NEXT:    v_mul_hi_u32 v6, v0, v2
954; GCN-NEXT:    v_mul_hi_u32 v7, v1, v2
955; GCN-NEXT:    v_mul_lo_u32 v2, v1, v2
956; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
957; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
958; GCN-NEXT:    v_mul_lo_u32 v6, v1, v4
959; GCN-NEXT:    v_mul_hi_u32 v4, v1, v4
960; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
961; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v5, v4, vcc
962; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v7, vcc
963; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
964; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
965; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
966; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
967; GCN-NEXT:    v_mul_lo_u32 v2, s2, v1
968; GCN-NEXT:    v_mul_hi_u32 v3, s2, v0
969; GCN-NEXT:    v_mul_lo_u32 v4, s4, v0
970; GCN-NEXT:    s_mov_b32 s4, s0
971; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
972; GCN-NEXT:    v_mul_lo_u32 v3, s2, v0
973; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
974; GCN-NEXT:    v_mul_lo_u32 v6, v0, v2
975; GCN-NEXT:    v_mul_hi_u32 v7, v0, v3
976; GCN-NEXT:    v_mul_hi_u32 v8, v0, v2
977; GCN-NEXT:    v_mul_hi_u32 v5, v1, v3
978; GCN-NEXT:    v_mul_lo_u32 v3, v1, v3
979; GCN-NEXT:    v_mul_hi_u32 v4, v1, v2
980; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
981; GCN-NEXT:    v_addc_u32_e32 v7, vcc, 0, v8, vcc
982; GCN-NEXT:    v_mul_lo_u32 v2, v1, v2
983; GCN-NEXT:    v_add_i32_e32 v3, vcc, v6, v3
984; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v7, v5, vcc
985; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v4, vcc
986; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
987; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
988; GCN-NEXT:    s_add_u32 s2, s10, s12
989; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
990; GCN-NEXT:    s_addc_u32 s3, s11, s12
991; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
992; GCN-NEXT:    s_xor_b64 s[10:11], s[2:3], s[12:13]
993; GCN-NEXT:    v_mul_lo_u32 v2, s10, v1
994; GCN-NEXT:    v_mul_hi_u32 v3, s10, v0
995; GCN-NEXT:    v_mul_hi_u32 v4, s10, v1
996; GCN-NEXT:    v_mul_hi_u32 v5, s11, v1
997; GCN-NEXT:    v_mul_lo_u32 v1, s11, v1
998; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
999; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
1000; GCN-NEXT:    v_mul_lo_u32 v4, s11, v0
1001; GCN-NEXT:    v_mul_hi_u32 v0, s11, v0
1002; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
1003; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
1004; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v5, vcc
1005; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
1006; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v2, vcc
1007; GCN-NEXT:    v_mul_lo_u32 v1, s8, v1
1008; GCN-NEXT:    v_mul_hi_u32 v2, s8, v0
1009; GCN-NEXT:    v_mul_lo_u32 v3, s9, v0
1010; GCN-NEXT:    v_mul_lo_u32 v0, s8, v0
1011; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v2
1012; GCN-NEXT:    v_add_i32_e32 v1, vcc, v3, v1
1013; GCN-NEXT:    v_sub_i32_e32 v2, vcc, s11, v1
1014; GCN-NEXT:    v_mov_b32_e32 v3, s9
1015; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s10, v0
1016; GCN-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, vcc
1017; GCN-NEXT:    v_subrev_i32_e64 v4, s[0:1], s8, v0
1018; GCN-NEXT:    v_subbrev_u32_e64 v5, s[2:3], 0, v2, s[0:1]
1019; GCN-NEXT:    v_cmp_le_u32_e64 s[2:3], s9, v5
1020; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[2:3]
1021; GCN-NEXT:    v_cmp_le_u32_e64 s[2:3], s8, v4
1022; GCN-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, s[0:1]
1023; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[2:3]
1024; GCN-NEXT:    v_cmp_eq_u32_e64 s[2:3], s9, v5
1025; GCN-NEXT:    v_subrev_i32_e64 v3, s[0:1], s8, v4
1026; GCN-NEXT:    v_cndmask_b32_e64 v6, v6, v7, s[2:3]
1027; GCN-NEXT:    v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1]
1028; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v6
1029; GCN-NEXT:    v_cndmask_b32_e64 v3, v4, v3, s[0:1]
1030; GCN-NEXT:    v_mov_b32_e32 v4, s11
1031; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v4, v1, vcc
1032; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s9, v1
1033; GCN-NEXT:    v_cndmask_b32_e64 v4, 0, -1, vcc
1034; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s8, v0
1035; GCN-NEXT:    v_cndmask_b32_e64 v2, v5, v2, s[0:1]
1036; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
1037; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s9, v1
1038; GCN-NEXT:    v_cndmask_b32_e32 v4, v4, v5, vcc
1039; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v4
1040; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
1041; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
1042; GCN-NEXT:    v_xor_b32_e32 v0, s12, v0
1043; GCN-NEXT:    v_xor_b32_e32 v1, s12, v1
1044; GCN-NEXT:    v_mov_b32_e32 v2, s12
1045; GCN-NEXT:    v_subrev_i32_e32 v0, vcc, s12, v0
1046; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
1047; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1048; GCN-NEXT:    s_endpgm
1049;
1050; GCN-IR-LABEL: s_test_srem33_64:
1051; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1052; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x9
1053; GCN-IR-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0xd
1054; GCN-IR-NEXT:    s_mov_b32 s13, 0
1055; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1056; GCN-IR-NEXT:    s_ashr_i64 s[2:3], s[2:3], 31
1057; GCN-IR-NEXT:    s_ashr_i64 s[8:9], s[4:5], 31
1058; GCN-IR-NEXT:    s_ashr_i32 s4, s3, 31
1059; GCN-IR-NEXT:    s_mov_b32 s5, s4
1060; GCN-IR-NEXT:    s_xor_b64 s[2:3], s[2:3], s[4:5]
1061; GCN-IR-NEXT:    s_sub_u32 s6, s2, s4
1062; GCN-IR-NEXT:    s_subb_u32 s7, s3, s4
1063; GCN-IR-NEXT:    s_ashr_i32 s2, s9, 31
1064; GCN-IR-NEXT:    s_mov_b32 s3, s2
1065; GCN-IR-NEXT:    s_xor_b64 s[8:9], s[8:9], s[2:3]
1066; GCN-IR-NEXT:    s_sub_u32 s8, s8, s2
1067; GCN-IR-NEXT:    s_subb_u32 s9, s9, s2
1068; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[10:11], s[6:7], 0
1069; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[2:3], s[8:9], 0
1070; GCN-IR-NEXT:    s_flbit_i32_b64 s12, s[8:9]
1071; GCN-IR-NEXT:    s_or_b64 s[10:11], s[2:3], s[10:11]
1072; GCN-IR-NEXT:    s_flbit_i32_b64 s20, s[6:7]
1073; GCN-IR-NEXT:    s_sub_u32 s14, s12, s20
1074; GCN-IR-NEXT:    s_subb_u32 s15, 0, 0
1075; GCN-IR-NEXT:    v_cmp_gt_u64_e64 s[16:17], s[14:15], 63
1076; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[18:19], s[14:15], 63
1077; GCN-IR-NEXT:    s_or_b64 s[16:17], s[10:11], s[16:17]
1078; GCN-IR-NEXT:    s_and_b64 s[10:11], s[16:17], exec
1079; GCN-IR-NEXT:    s_cselect_b32 s11, 0, s7
1080; GCN-IR-NEXT:    s_cselect_b32 s10, 0, s6
1081; GCN-IR-NEXT:    s_or_b64 s[16:17], s[16:17], s[18:19]
1082; GCN-IR-NEXT:    s_mov_b64 s[2:3], 0
1083; GCN-IR-NEXT:    s_andn2_b64 vcc, exec, s[16:17]
1084; GCN-IR-NEXT:    s_cbranch_vccz .LBB8_5
1085; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1086; GCN-IR-NEXT:    s_add_u32 s16, s14, 1
1087; GCN-IR-NEXT:    s_addc_u32 s17, s15, 0
1088; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[10:11], s[16:17], 0
1089; GCN-IR-NEXT:    s_sub_i32 s14, 63, s14
1090; GCN-IR-NEXT:    s_andn2_b64 vcc, exec, s[10:11]
1091; GCN-IR-NEXT:    s_lshl_b64 s[10:11], s[6:7], s14
1092; GCN-IR-NEXT:    s_cbranch_vccz .LBB8_4
1093; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1094; GCN-IR-NEXT:    s_lshr_b64 s[14:15], s[6:7], s16
1095; GCN-IR-NEXT:    s_add_u32 s18, s8, -1
1096; GCN-IR-NEXT:    s_addc_u32 s19, s9, -1
1097; GCN-IR-NEXT:    s_not_b64 s[2:3], s[12:13]
1098; GCN-IR-NEXT:    s_add_u32 s12, s2, s20
1099; GCN-IR-NEXT:    s_addc_u32 s13, s3, 0
1100; GCN-IR-NEXT:    s_mov_b64 s[16:17], 0
1101; GCN-IR-NEXT:    s_mov_b32 s3, 0
1102; GCN-IR-NEXT:  .LBB8_3: ; %udiv-do-while
1103; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1104; GCN-IR-NEXT:    s_lshl_b64 s[14:15], s[14:15], 1
1105; GCN-IR-NEXT:    s_lshr_b32 s2, s11, 31
1106; GCN-IR-NEXT:    s_lshl_b64 s[10:11], s[10:11], 1
1107; GCN-IR-NEXT:    s_or_b64 s[14:15], s[14:15], s[2:3]
1108; GCN-IR-NEXT:    s_or_b64 s[10:11], s[16:17], s[10:11]
1109; GCN-IR-NEXT:    s_sub_u32 s2, s18, s14
1110; GCN-IR-NEXT:    s_subb_u32 s2, s19, s15
1111; GCN-IR-NEXT:    s_ashr_i32 s16, s2, 31
1112; GCN-IR-NEXT:    s_mov_b32 s17, s16
1113; GCN-IR-NEXT:    s_and_b32 s2, s16, 1
1114; GCN-IR-NEXT:    s_and_b64 s[16:17], s[16:17], s[8:9]
1115; GCN-IR-NEXT:    s_sub_u32 s14, s14, s16
1116; GCN-IR-NEXT:    s_subb_u32 s15, s15, s17
1117; GCN-IR-NEXT:    s_add_u32 s12, s12, 1
1118; GCN-IR-NEXT:    s_addc_u32 s13, s13, 0
1119; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[20:21], s[12:13], 0
1120; GCN-IR-NEXT:    s_mov_b64 s[16:17], s[2:3]
1121; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[20:21]
1122; GCN-IR-NEXT:    s_cbranch_vccz .LBB8_3
1123; GCN-IR-NEXT:  .LBB8_4: ; %Flow7
1124; GCN-IR-NEXT:    s_lshl_b64 s[10:11], s[10:11], 1
1125; GCN-IR-NEXT:    s_or_b64 s[10:11], s[2:3], s[10:11]
1126; GCN-IR-NEXT:  .LBB8_5: ; %udiv-end
1127; GCN-IR-NEXT:    v_mov_b32_e32 v0, s10
1128; GCN-IR-NEXT:    v_mul_hi_u32 v0, s8, v0
1129; GCN-IR-NEXT:    s_mul_i32 s11, s8, s11
1130; GCN-IR-NEXT:    s_mul_i32 s9, s9, s10
1131; GCN-IR-NEXT:    s_mul_i32 s8, s8, s10
1132; GCN-IR-NEXT:    v_readfirstlane_b32 s12, v0
1133; GCN-IR-NEXT:    s_add_i32 s11, s12, s11
1134; GCN-IR-NEXT:    s_add_i32 s11, s11, s9
1135; GCN-IR-NEXT:    s_sub_u32 s6, s6, s8
1136; GCN-IR-NEXT:    s_subb_u32 s7, s7, s11
1137; GCN-IR-NEXT:    s_xor_b64 s[6:7], s[6:7], s[4:5]
1138; GCN-IR-NEXT:    s_sub_u32 s4, s6, s4
1139; GCN-IR-NEXT:    s_subb_u32 s5, s7, s5
1140; GCN-IR-NEXT:    v_mov_b32_e32 v0, s4
1141; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
1142; GCN-IR-NEXT:    s_mov_b32 s2, -1
1143; GCN-IR-NEXT:    v_mov_b32_e32 v1, s5
1144; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1145; GCN-IR-NEXT:    s_endpgm
1146  %1 = ashr i64 %x, 31
1147  %2 = ashr i64 %y, 31
1148  %result = srem i64 %1, %2
1149  store i64 %result, ptr addrspace(1) %out
1150  ret void
1151}
1152
1153define amdgpu_kernel void @s_test_srem24_48(ptr addrspace(1) %out, i48 %x, i48 %y) {
1154; GCN-LABEL: s_test_srem24_48:
1155; GCN:       ; %bb.0:
1156; GCN-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x9
1157; GCN-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0xd
1158; GCN-NEXT:    s_mov_b32 s7, 0xf000
1159; GCN-NEXT:    s_mov_b32 s6, -1
1160; GCN-NEXT:    s_waitcnt lgkmcnt(0)
1161; GCN-NEXT:    s_sext_i32_i16 s3, s3
1162; GCN-NEXT:    s_sext_i32_i16 s5, s5
1163; GCN-NEXT:    v_mov_b32_e32 v0, s4
1164; GCN-NEXT:    v_alignbit_b32 v0, s5, v0, 24
1165; GCN-NEXT:    v_cvt_f32_i32_e32 v1, v0
1166; GCN-NEXT:    v_mov_b32_e32 v2, s2
1167; GCN-NEXT:    v_alignbit_b32 v2, s3, v2, 24
1168; GCN-NEXT:    v_cvt_f32_i32_e32 v3, v2
1169; GCN-NEXT:    v_rcp_iflag_f32_e32 v4, v1
1170; GCN-NEXT:    v_xor_b32_e32 v5, v2, v0
1171; GCN-NEXT:    v_ashrrev_i32_e32 v5, 30, v5
1172; GCN-NEXT:    v_or_b32_e32 v5, 1, v5
1173; GCN-NEXT:    v_mul_f32_e32 v4, v3, v4
1174; GCN-NEXT:    v_trunc_f32_e32 v4, v4
1175; GCN-NEXT:    v_mad_f32 v3, -v4, v1, v3
1176; GCN-NEXT:    v_cvt_i32_f32_e32 v4, v4
1177; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v1|
1178; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v5, vcc
1179; GCN-NEXT:    s_mov_b32 s4, s0
1180; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v4
1181; GCN-NEXT:    v_mul_lo_u32 v0, v1, v0
1182; GCN-NEXT:    s_mov_b32 s5, s1
1183; GCN-NEXT:    v_subrev_i32_e32 v0, vcc, v0, v2
1184; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
1185; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
1186; GCN-NEXT:    buffer_store_dword v0, off, s[4:7], 0
1187; GCN-NEXT:    buffer_store_short v1, off, s[4:7], 0 offset:4
1188; GCN-NEXT:    s_endpgm
1189;
1190; GCN-IR-LABEL: s_test_srem24_48:
1191; GCN-IR:       ; %bb.0:
1192; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x9
1193; GCN-IR-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0xd
1194; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
1195; GCN-IR-NEXT:    s_mov_b32 s6, -1
1196; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1197; GCN-IR-NEXT:    s_sext_i32_i16 s3, s3
1198; GCN-IR-NEXT:    s_sext_i32_i16 s5, s5
1199; GCN-IR-NEXT:    v_mov_b32_e32 v0, s4
1200; GCN-IR-NEXT:    v_alignbit_b32 v0, s5, v0, 24
1201; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, v0
1202; GCN-IR-NEXT:    v_mov_b32_e32 v2, s2
1203; GCN-IR-NEXT:    v_alignbit_b32 v2, s3, v2, 24
1204; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v3, v2
1205; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v4, v1
1206; GCN-IR-NEXT:    v_xor_b32_e32 v5, v2, v0
1207; GCN-IR-NEXT:    v_ashrrev_i32_e32 v5, 30, v5
1208; GCN-IR-NEXT:    v_or_b32_e32 v5, 1, v5
1209; GCN-IR-NEXT:    v_mul_f32_e32 v4, v3, v4
1210; GCN-IR-NEXT:    v_trunc_f32_e32 v4, v4
1211; GCN-IR-NEXT:    v_mad_f32 v3, -v4, v1, v3
1212; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v4, v4
1213; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v1|
1214; GCN-IR-NEXT:    v_cndmask_b32_e32 v1, 0, v5, vcc
1215; GCN-IR-NEXT:    s_mov_b32 s4, s0
1216; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v1, v4
1217; GCN-IR-NEXT:    v_mul_lo_u32 v0, v1, v0
1218; GCN-IR-NEXT:    s_mov_b32 s5, s1
1219; GCN-IR-NEXT:    v_subrev_i32_e32 v0, vcc, v0, v2
1220; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
1221; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
1222; GCN-IR-NEXT:    buffer_store_dword v0, off, s[4:7], 0
1223; GCN-IR-NEXT:    buffer_store_short v1, off, s[4:7], 0 offset:4
1224; GCN-IR-NEXT:    s_endpgm
1225  %1 = ashr i48 %x, 24
1226  %2 = ashr i48 %y, 24
1227  %result = srem i48 %1, %2
1228  store i48 %result, ptr addrspace(1) %out
1229  ret void
1230}
1231
1232define amdgpu_kernel void @s_test_srem_k_num_i64(ptr addrspace(1) %out, i64 %x) {
1233; GCN-LABEL: s_test_srem_k_num_i64:
1234; GCN:       ; %bb.0:
1235; GCN-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x9
1236; GCN-NEXT:    s_mov_b32 s7, 0xf000
1237; GCN-NEXT:    s_mov_b32 s6, -1
1238; GCN-NEXT:    s_waitcnt lgkmcnt(0)
1239; GCN-NEXT:    s_ashr_i32 s4, s3, 31
1240; GCN-NEXT:    s_add_u32 s2, s2, s4
1241; GCN-NEXT:    s_mov_b32 s5, s4
1242; GCN-NEXT:    s_addc_u32 s3, s3, s4
1243; GCN-NEXT:    s_xor_b64 s[8:9], s[2:3], s[4:5]
1244; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s8
1245; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s9
1246; GCN-NEXT:    s_sub_u32 s2, 0, s8
1247; GCN-NEXT:    s_subb_u32 s3, 0, s9
1248; GCN-NEXT:    s_mov_b32 s4, s0
1249; GCN-NEXT:    v_madmk_f32 v0, v1, 0x4f800000, v0
1250; GCN-NEXT:    v_rcp_f32_e32 v0, v0
1251; GCN-NEXT:    s_mov_b32 s5, s1
1252; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
1253; GCN-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
1254; GCN-NEXT:    v_trunc_f32_e32 v1, v1
1255; GCN-NEXT:    v_madmk_f32 v0, v1, 0xcf800000, v0
1256; GCN-NEXT:    v_cvt_u32_f32_e32 v1, v1
1257; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
1258; GCN-NEXT:    v_mul_lo_u32 v2, s2, v1
1259; GCN-NEXT:    v_mul_hi_u32 v3, s2, v0
1260; GCN-NEXT:    v_mul_lo_u32 v5, s3, v0
1261; GCN-NEXT:    v_mul_lo_u32 v4, s2, v0
1262; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
1263; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
1264; GCN-NEXT:    v_mul_hi_u32 v3, v0, v4
1265; GCN-NEXT:    v_mul_lo_u32 v5, v0, v2
1266; GCN-NEXT:    v_mul_hi_u32 v7, v0, v2
1267; GCN-NEXT:    v_mul_hi_u32 v6, v1, v4
1268; GCN-NEXT:    v_mul_lo_u32 v4, v1, v4
1269; GCN-NEXT:    v_mul_hi_u32 v8, v1, v2
1270; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
1271; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v7, vcc
1272; GCN-NEXT:    v_mul_lo_u32 v2, v1, v2
1273; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v4
1274; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v5, v6, vcc
1275; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v8, vcc
1276; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
1277; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
1278; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
1279; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
1280; GCN-NEXT:    v_mul_lo_u32 v2, s2, v1
1281; GCN-NEXT:    v_mul_hi_u32 v3, s2, v0
1282; GCN-NEXT:    v_mul_lo_u32 v4, s3, v0
1283; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
1284; GCN-NEXT:    v_mul_lo_u32 v3, s2, v0
1285; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
1286; GCN-NEXT:    v_mul_lo_u32 v6, v0, v2
1287; GCN-NEXT:    v_mul_hi_u32 v7, v0, v3
1288; GCN-NEXT:    v_mul_hi_u32 v8, v0, v2
1289; GCN-NEXT:    v_mul_hi_u32 v5, v1, v3
1290; GCN-NEXT:    v_mul_lo_u32 v3, v1, v3
1291; GCN-NEXT:    v_mul_hi_u32 v4, v1, v2
1292; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
1293; GCN-NEXT:    v_addc_u32_e32 v7, vcc, 0, v8, vcc
1294; GCN-NEXT:    v_mul_lo_u32 v2, v1, v2
1295; GCN-NEXT:    v_add_i32_e32 v3, vcc, v6, v3
1296; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v7, v5, vcc
1297; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v4, vcc
1298; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
1299; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
1300; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
1301; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
1302; GCN-NEXT:    v_mul_lo_u32 v2, v1, 24
1303; GCN-NEXT:    v_mul_hi_u32 v0, v0, 24
1304; GCN-NEXT:    v_mul_hi_u32 v1, v1, 24
1305; GCN-NEXT:    v_mov_b32_e32 v3, s9
1306; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
1307; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v1, vcc
1308; GCN-NEXT:    v_mul_lo_u32 v1, s9, v0
1309; GCN-NEXT:    v_mul_hi_u32 v2, s8, v0
1310; GCN-NEXT:    v_mul_lo_u32 v0, s8, v0
1311; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v2
1312; GCN-NEXT:    v_sub_i32_e32 v2, vcc, 0, v1
1313; GCN-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
1314; GCN-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, vcc
1315; GCN-NEXT:    v_subrev_i32_e64 v4, s[0:1], s8, v0
1316; GCN-NEXT:    v_subbrev_u32_e64 v5, s[2:3], 0, v2, s[0:1]
1317; GCN-NEXT:    v_cmp_le_u32_e64 s[2:3], s9, v5
1318; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[2:3]
1319; GCN-NEXT:    v_cmp_le_u32_e64 s[2:3], s8, v4
1320; GCN-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, s[0:1]
1321; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[2:3]
1322; GCN-NEXT:    v_cmp_eq_u32_e64 s[2:3], s9, v5
1323; GCN-NEXT:    v_subrev_i32_e64 v3, s[0:1], s8, v4
1324; GCN-NEXT:    v_cndmask_b32_e64 v6, v6, v7, s[2:3]
1325; GCN-NEXT:    v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1]
1326; GCN-NEXT:    v_subb_u32_e32 v1, vcc, 0, v1, vcc
1327; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v6
1328; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s9, v1
1329; GCN-NEXT:    v_cndmask_b32_e64 v3, v4, v3, s[0:1]
1330; GCN-NEXT:    v_cndmask_b32_e64 v4, 0, -1, vcc
1331; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s8, v0
1332; GCN-NEXT:    v_cndmask_b32_e64 v2, v5, v2, s[0:1]
1333; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
1334; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s9, v1
1335; GCN-NEXT:    v_cndmask_b32_e32 v4, v4, v5, vcc
1336; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v4
1337; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
1338; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
1339; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1340; GCN-NEXT:    s_endpgm
1341;
1342; GCN-IR-LABEL: s_test_srem_k_num_i64:
1343; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1344; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x9
1345; GCN-IR-NEXT:    s_mov_b64 s[6:7], 0
1346; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1347; GCN-IR-NEXT:    s_ashr_i32 s8, s3, 31
1348; GCN-IR-NEXT:    s_mov_b32 s9, s8
1349; GCN-IR-NEXT:    s_xor_b64 s[2:3], s[2:3], s[8:9]
1350; GCN-IR-NEXT:    s_sub_u32 s4, s2, s8
1351; GCN-IR-NEXT:    s_subb_u32 s5, s3, s8
1352; GCN-IR-NEXT:    s_flbit_i32_b64 s12, s[4:5]
1353; GCN-IR-NEXT:    s_add_u32 s2, s12, 0xffffffc5
1354; GCN-IR-NEXT:    s_addc_u32 s3, 0, -1
1355; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[8:9], s[4:5], 0
1356; GCN-IR-NEXT:    v_cmp_gt_u64_e64 s[10:11], s[2:3], 63
1357; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[14:15], s[2:3], 63
1358; GCN-IR-NEXT:    s_or_b64 s[10:11], s[8:9], s[10:11]
1359; GCN-IR-NEXT:    s_and_b64 s[8:9], s[10:11], exec
1360; GCN-IR-NEXT:    s_cselect_b32 s8, 0, 24
1361; GCN-IR-NEXT:    s_or_b64 s[10:11], s[10:11], s[14:15]
1362; GCN-IR-NEXT:    s_andn2_b64 vcc, exec, s[10:11]
1363; GCN-IR-NEXT:    s_mov_b32 s9, 0
1364; GCN-IR-NEXT:    s_cbranch_vccz .LBB10_5
1365; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1366; GCN-IR-NEXT:    s_add_u32 s8, s2, 1
1367; GCN-IR-NEXT:    s_addc_u32 s9, s3, 0
1368; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[10:11], s[8:9], 0
1369; GCN-IR-NEXT:    s_sub_i32 s2, 63, s2
1370; GCN-IR-NEXT:    s_andn2_b64 vcc, exec, s[10:11]
1371; GCN-IR-NEXT:    s_lshl_b64 s[2:3], 24, s2
1372; GCN-IR-NEXT:    s_cbranch_vccz .LBB10_4
1373; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1374; GCN-IR-NEXT:    s_lshr_b64 s[10:11], 24, s8
1375; GCN-IR-NEXT:    s_add_u32 s14, s4, -1
1376; GCN-IR-NEXT:    s_addc_u32 s15, s5, -1
1377; GCN-IR-NEXT:    s_sub_u32 s8, 58, s12
1378; GCN-IR-NEXT:    s_subb_u32 s9, 0, 0
1379; GCN-IR-NEXT:    s_mov_b64 s[12:13], 0
1380; GCN-IR-NEXT:    s_mov_b32 s7, 0
1381; GCN-IR-NEXT:  .LBB10_3: ; %udiv-do-while
1382; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1383; GCN-IR-NEXT:    s_lshl_b64 s[10:11], s[10:11], 1
1384; GCN-IR-NEXT:    s_lshr_b32 s6, s3, 31
1385; GCN-IR-NEXT:    s_lshl_b64 s[2:3], s[2:3], 1
1386; GCN-IR-NEXT:    s_or_b64 s[10:11], s[10:11], s[6:7]
1387; GCN-IR-NEXT:    s_or_b64 s[2:3], s[12:13], s[2:3]
1388; GCN-IR-NEXT:    s_sub_u32 s6, s14, s10
1389; GCN-IR-NEXT:    s_subb_u32 s6, s15, s11
1390; GCN-IR-NEXT:    s_ashr_i32 s12, s6, 31
1391; GCN-IR-NEXT:    s_mov_b32 s13, s12
1392; GCN-IR-NEXT:    s_and_b32 s6, s12, 1
1393; GCN-IR-NEXT:    s_and_b64 s[12:13], s[12:13], s[4:5]
1394; GCN-IR-NEXT:    s_sub_u32 s10, s10, s12
1395; GCN-IR-NEXT:    s_subb_u32 s11, s11, s13
1396; GCN-IR-NEXT:    s_add_u32 s8, s8, 1
1397; GCN-IR-NEXT:    s_addc_u32 s9, s9, 0
1398; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[16:17], s[8:9], 0
1399; GCN-IR-NEXT:    s_mov_b64 s[12:13], s[6:7]
1400; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[16:17]
1401; GCN-IR-NEXT:    s_cbranch_vccz .LBB10_3
1402; GCN-IR-NEXT:  .LBB10_4: ; %Flow6
1403; GCN-IR-NEXT:    s_lshl_b64 s[2:3], s[2:3], 1
1404; GCN-IR-NEXT:    s_or_b64 s[8:9], s[6:7], s[2:3]
1405; GCN-IR-NEXT:  .LBB10_5: ; %udiv-end
1406; GCN-IR-NEXT:    v_mov_b32_e32 v0, s8
1407; GCN-IR-NEXT:    v_mul_hi_u32 v0, s4, v0
1408; GCN-IR-NEXT:    s_mul_i32 s6, s4, s9
1409; GCN-IR-NEXT:    s_mul_i32 s5, s5, s8
1410; GCN-IR-NEXT:    s_mul_i32 s4, s4, s8
1411; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, s6, v0
1412; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, s5, v0
1413; GCN-IR-NEXT:    v_sub_i32_e64 v0, vcc, 24, s4
1414; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
1415; GCN-IR-NEXT:    s_mov_b32 s2, -1
1416; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, 0, v1, vcc
1417; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1418; GCN-IR-NEXT:    s_endpgm
1419  %result = srem i64 24, %x
1420  store i64 %result, ptr addrspace(1) %out
1421  ret void
1422}
1423
1424define i64 @v_test_srem_k_num_i64(i64 %x) {
1425; GCN-LABEL: v_test_srem_k_num_i64:
1426; GCN:       ; %bb.0:
1427; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1428; GCN-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1429; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
1430; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v2, vcc
1431; GCN-NEXT:    v_xor_b32_e32 v1, v1, v2
1432; GCN-NEXT:    v_xor_b32_e32 v0, v0, v2
1433; GCN-NEXT:    v_cvt_f32_u32_e32 v2, v0
1434; GCN-NEXT:    v_cvt_f32_u32_e32 v3, v1
1435; GCN-NEXT:    v_sub_i32_e32 v4, vcc, 0, v0
1436; GCN-NEXT:    v_subb_u32_e32 v5, vcc, 0, v1, vcc
1437; GCN-NEXT:    v_madmk_f32 v2, v3, 0x4f800000, v2
1438; GCN-NEXT:    v_rcp_f32_e32 v2, v2
1439; GCN-NEXT:    v_mul_f32_e32 v2, 0x5f7ffffc, v2
1440; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v2
1441; GCN-NEXT:    v_trunc_f32_e32 v3, v3
1442; GCN-NEXT:    v_madmk_f32 v2, v3, 0xcf800000, v2
1443; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
1444; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
1445; GCN-NEXT:    v_mul_hi_u32 v6, v4, v2
1446; GCN-NEXT:    v_mul_lo_u32 v7, v4, v3
1447; GCN-NEXT:    v_mul_lo_u32 v8, v5, v2
1448; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
1449; GCN-NEXT:    v_mul_lo_u32 v7, v4, v2
1450; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
1451; GCN-NEXT:    v_mul_lo_u32 v8, v2, v6
1452; GCN-NEXT:    v_mul_hi_u32 v9, v2, v7
1453; GCN-NEXT:    v_mul_hi_u32 v10, v2, v6
1454; GCN-NEXT:    v_mul_hi_u32 v11, v3, v6
1455; GCN-NEXT:    v_mul_lo_u32 v6, v3, v6
1456; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
1457; GCN-NEXT:    v_addc_u32_e32 v9, vcc, 0, v10, vcc
1458; GCN-NEXT:    v_mul_lo_u32 v10, v3, v7
1459; GCN-NEXT:    v_mul_hi_u32 v7, v3, v7
1460; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
1461; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v9, v7, vcc
1462; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v11, vcc
1463; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
1464; GCN-NEXT:    v_addc_u32_e32 v7, vcc, 0, v8, vcc
1465; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v6
1466; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v3, v7, vcc
1467; GCN-NEXT:    v_mul_lo_u32 v6, v4, v3
1468; GCN-NEXT:    v_mul_hi_u32 v7, v4, v2
1469; GCN-NEXT:    v_mul_lo_u32 v5, v5, v2
1470; GCN-NEXT:    v_mul_lo_u32 v4, v4, v2
1471; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
1472; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
1473; GCN-NEXT:    v_mul_lo_u32 v8, v2, v5
1474; GCN-NEXT:    v_mul_hi_u32 v9, v2, v4
1475; GCN-NEXT:    v_mul_hi_u32 v10, v2, v5
1476; GCN-NEXT:    v_mul_hi_u32 v7, v3, v4
1477; GCN-NEXT:    v_mul_lo_u32 v4, v3, v4
1478; GCN-NEXT:    v_mul_hi_u32 v6, v3, v5
1479; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
1480; GCN-NEXT:    v_addc_u32_e32 v9, vcc, 0, v10, vcc
1481; GCN-NEXT:    v_mul_lo_u32 v5, v3, v5
1482; GCN-NEXT:    v_add_i32_e32 v4, vcc, v8, v4
1483; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v9, v7, vcc
1484; GCN-NEXT:    v_addc_u32_e32 v6, vcc, 0, v6, vcc
1485; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
1486; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
1487; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
1488; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v3, v5, vcc
1489; GCN-NEXT:    v_mul_lo_u32 v4, v3, 24
1490; GCN-NEXT:    v_mul_hi_u32 v2, v2, 24
1491; GCN-NEXT:    v_mul_hi_u32 v3, v3, 24
1492; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
1493; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v3, vcc
1494; GCN-NEXT:    v_mul_lo_u32 v3, v1, v2
1495; GCN-NEXT:    v_mul_hi_u32 v4, v0, v2
1496; GCN-NEXT:    v_mul_lo_u32 v2, v0, v2
1497; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
1498; GCN-NEXT:    v_sub_i32_e32 v4, vcc, 0, v3
1499; GCN-NEXT:    v_sub_i32_e32 v2, vcc, 24, v2
1500; GCN-NEXT:    v_subb_u32_e64 v4, s[4:5], v4, v1, vcc
1501; GCN-NEXT:    v_sub_i32_e64 v5, s[4:5], v2, v0
1502; GCN-NEXT:    v_subbrev_u32_e64 v6, s[6:7], 0, v4, s[4:5]
1503; GCN-NEXT:    v_cmp_ge_u32_e64 s[6:7], v6, v1
1504; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[6:7]
1505; GCN-NEXT:    v_cmp_ge_u32_e64 s[6:7], v5, v0
1506; GCN-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[6:7]
1507; GCN-NEXT:    v_cmp_eq_u32_e64 s[6:7], v6, v1
1508; GCN-NEXT:    v_subb_u32_e64 v4, s[4:5], v4, v1, s[4:5]
1509; GCN-NEXT:    v_cndmask_b32_e64 v7, v7, v8, s[6:7]
1510; GCN-NEXT:    v_sub_i32_e64 v8, s[4:5], v5, v0
1511; GCN-NEXT:    v_subb_u32_e32 v3, vcc, 0, v3, vcc
1512; GCN-NEXT:    v_subbrev_u32_e64 v4, s[4:5], 0, v4, s[4:5]
1513; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v3, v1
1514; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v7
1515; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
1516; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v2, v0
1517; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
1518; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v3, v1
1519; GCN-NEXT:    v_cndmask_b32_e32 v0, v7, v0, vcc
1520; GCN-NEXT:    v_cndmask_b32_e64 v5, v5, v8, s[4:5]
1521; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
1522; GCN-NEXT:    v_cndmask_b32_e64 v1, v6, v4, s[4:5]
1523; GCN-NEXT:    v_cndmask_b32_e32 v0, v2, v5, vcc
1524; GCN-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
1525; GCN-NEXT:    s_setpc_b64 s[30:31]
1526;
1527; GCN-IR-LABEL: v_test_srem_k_num_i64:
1528; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1529; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1530; GCN-IR-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1531; GCN-IR-NEXT:    v_xor_b32_e32 v0, v0, v2
1532; GCN-IR-NEXT:    v_xor_b32_e32 v1, v1, v2
1533; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1534; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
1535; GCN-IR-NEXT:    v_ffbh_u32_e32 v2, v0
1536; GCN-IR-NEXT:    v_add_i32_e32 v2, vcc, 32, v2
1537; GCN-IR-NEXT:    v_ffbh_u32_e32 v3, v1
1538; GCN-IR-NEXT:    v_min_u32_e32 v10, v2, v3
1539; GCN-IR-NEXT:    s_movk_i32 s6, 0xffc5
1540; GCN-IR-NEXT:    v_add_i32_e32 v2, vcc, s6, v10
1541; GCN-IR-NEXT:    v_addc_u32_e64 v3, s[6:7], 0, -1, vcc
1542; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
1543; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, 63, v[2:3]
1544; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[6:7], 63, v[2:3]
1545; GCN-IR-NEXT:    s_or_b64 s[4:5], s[4:5], vcc
1546; GCN-IR-NEXT:    v_cndmask_b32_e64 v4, 24, 0, s[4:5]
1547; GCN-IR-NEXT:    s_xor_b64 s[4:5], s[4:5], -1
1548; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1549; GCN-IR-NEXT:    s_and_b64 s[4:5], s[4:5], s[6:7]
1550; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
1551; GCN-IR-NEXT:    s_cbranch_execz .LBB11_6
1552; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1553; GCN-IR-NEXT:    v_add_i32_e32 v6, vcc, 1, v2
1554; GCN-IR-NEXT:    v_addc_u32_e32 v7, vcc, 0, v3, vcc
1555; GCN-IR-NEXT:    v_sub_i32_e64 v2, s[4:5], 63, v2
1556; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 0, v[6:7]
1557; GCN-IR-NEXT:    v_lshl_b64 v[2:3], 24, v2
1558; GCN-IR-NEXT:    v_mov_b32_e32 v4, 0
1559; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1560; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
1561; GCN-IR-NEXT:    s_xor_b64 s[8:9], exec, s[4:5]
1562; GCN-IR-NEXT:    s_cbranch_execz .LBB11_5
1563; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1564; GCN-IR-NEXT:    v_add_i32_e32 v12, vcc, -1, v0
1565; GCN-IR-NEXT:    v_addc_u32_e32 v13, vcc, -1, v1, vcc
1566; GCN-IR-NEXT:    v_lshr_b64 v[8:9], 24, v6
1567; GCN-IR-NEXT:    v_sub_i32_e32 v6, vcc, 58, v10
1568; GCN-IR-NEXT:    v_mov_b32_e32 v10, 0
1569; GCN-IR-NEXT:    v_subb_u32_e64 v7, s[4:5], 0, 0, vcc
1570; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
1571; GCN-IR-NEXT:    v_mov_b32_e32 v11, 0
1572; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1573; GCN-IR-NEXT:  .LBB11_3: ; %udiv-do-while
1574; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1575; GCN-IR-NEXT:    v_lshl_b64 v[8:9], v[8:9], 1
1576; GCN-IR-NEXT:    v_lshrrev_b32_e32 v4, 31, v3
1577; GCN-IR-NEXT:    v_or_b32_e32 v8, v8, v4
1578; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[2:3], 1
1579; GCN-IR-NEXT:    v_sub_i32_e32 v4, vcc, v12, v8
1580; GCN-IR-NEXT:    v_subb_u32_e32 v4, vcc, v13, v9, vcc
1581; GCN-IR-NEXT:    v_or_b32_e32 v2, v10, v2
1582; GCN-IR-NEXT:    v_ashrrev_i32_e32 v10, 31, v4
1583; GCN-IR-NEXT:    v_add_i32_e32 v6, vcc, 1, v6
1584; GCN-IR-NEXT:    v_or_b32_e32 v3, v11, v3
1585; GCN-IR-NEXT:    v_and_b32_e32 v4, 1, v10
1586; GCN-IR-NEXT:    v_and_b32_e32 v11, v10, v1
1587; GCN-IR-NEXT:    v_and_b32_e32 v10, v10, v0
1588; GCN-IR-NEXT:    v_addc_u32_e32 v7, vcc, 0, v7, vcc
1589; GCN-IR-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[6:7]
1590; GCN-IR-NEXT:    v_sub_i32_e64 v8, s[4:5], v8, v10
1591; GCN-IR-NEXT:    v_subb_u32_e64 v9, s[4:5], v9, v11, s[4:5]
1592; GCN-IR-NEXT:    v_mov_b32_e32 v11, v5
1593; GCN-IR-NEXT:    s_or_b64 s[10:11], vcc, s[10:11]
1594; GCN-IR-NEXT:    v_mov_b32_e32 v10, v4
1595; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[10:11]
1596; GCN-IR-NEXT:    s_cbranch_execnz .LBB11_3
1597; GCN-IR-NEXT:  ; %bb.4: ; %Flow
1598; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
1599; GCN-IR-NEXT:  .LBB11_5: ; %Flow4
1600; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
1601; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[2:3], 1
1602; GCN-IR-NEXT:    v_or_b32_e32 v5, v5, v3
1603; GCN-IR-NEXT:    v_or_b32_e32 v4, v4, v2
1604; GCN-IR-NEXT:  .LBB11_6: ; %Flow5
1605; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
1606; GCN-IR-NEXT:    v_mul_lo_u32 v2, v0, v5
1607; GCN-IR-NEXT:    v_mul_hi_u32 v3, v0, v4
1608; GCN-IR-NEXT:    v_mul_lo_u32 v1, v1, v4
1609; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, v4
1610; GCN-IR-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
1611; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
1612; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
1613; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, 0, v1, vcc
1614; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1615  %result = srem i64 24, %x
1616  ret i64 %result
1617}
1618
1619define i64 @v_test_srem_pow2_k_num_i64(i64 %x) {
1620; GCN-LABEL: v_test_srem_pow2_k_num_i64:
1621; GCN:       ; %bb.0:
1622; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1623; GCN-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1624; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
1625; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v2, vcc
1626; GCN-NEXT:    v_xor_b32_e32 v1, v1, v2
1627; GCN-NEXT:    v_xor_b32_e32 v0, v0, v2
1628; GCN-NEXT:    v_cvt_f32_u32_e32 v2, v0
1629; GCN-NEXT:    v_cvt_f32_u32_e32 v3, v1
1630; GCN-NEXT:    v_sub_i32_e32 v4, vcc, 0, v0
1631; GCN-NEXT:    v_subb_u32_e32 v5, vcc, 0, v1, vcc
1632; GCN-NEXT:    v_madmk_f32 v2, v3, 0x4f800000, v2
1633; GCN-NEXT:    v_rcp_f32_e32 v2, v2
1634; GCN-NEXT:    v_mul_f32_e32 v2, 0x5f7ffffc, v2
1635; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v2
1636; GCN-NEXT:    v_trunc_f32_e32 v3, v3
1637; GCN-NEXT:    v_madmk_f32 v2, v3, 0xcf800000, v2
1638; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
1639; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
1640; GCN-NEXT:    v_mul_hi_u32 v6, v4, v2
1641; GCN-NEXT:    v_mul_lo_u32 v7, v4, v3
1642; GCN-NEXT:    v_mul_lo_u32 v8, v5, v2
1643; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
1644; GCN-NEXT:    v_mul_lo_u32 v7, v4, v2
1645; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
1646; GCN-NEXT:    v_mul_lo_u32 v8, v2, v6
1647; GCN-NEXT:    v_mul_hi_u32 v9, v2, v7
1648; GCN-NEXT:    v_mul_hi_u32 v10, v2, v6
1649; GCN-NEXT:    v_mul_hi_u32 v11, v3, v6
1650; GCN-NEXT:    v_mul_lo_u32 v6, v3, v6
1651; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
1652; GCN-NEXT:    v_addc_u32_e32 v9, vcc, 0, v10, vcc
1653; GCN-NEXT:    v_mul_lo_u32 v10, v3, v7
1654; GCN-NEXT:    v_mul_hi_u32 v7, v3, v7
1655; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
1656; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v9, v7, vcc
1657; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v11, vcc
1658; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
1659; GCN-NEXT:    v_addc_u32_e32 v7, vcc, 0, v8, vcc
1660; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v6
1661; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v3, v7, vcc
1662; GCN-NEXT:    v_mul_lo_u32 v6, v4, v3
1663; GCN-NEXT:    v_mul_hi_u32 v7, v4, v2
1664; GCN-NEXT:    v_mul_lo_u32 v5, v5, v2
1665; GCN-NEXT:    v_mul_lo_u32 v4, v4, v2
1666; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
1667; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
1668; GCN-NEXT:    v_mul_lo_u32 v8, v2, v5
1669; GCN-NEXT:    v_mul_hi_u32 v9, v2, v4
1670; GCN-NEXT:    v_mul_hi_u32 v10, v2, v5
1671; GCN-NEXT:    v_mul_hi_u32 v7, v3, v4
1672; GCN-NEXT:    v_mul_lo_u32 v4, v3, v4
1673; GCN-NEXT:    v_mul_hi_u32 v6, v3, v5
1674; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
1675; GCN-NEXT:    v_addc_u32_e32 v9, vcc, 0, v10, vcc
1676; GCN-NEXT:    v_mul_lo_u32 v5, v3, v5
1677; GCN-NEXT:    v_add_i32_e32 v4, vcc, v8, v4
1678; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v9, v7, vcc
1679; GCN-NEXT:    v_addc_u32_e32 v6, vcc, 0, v6, vcc
1680; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
1681; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
1682; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
1683; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v3, v5, vcc
1684; GCN-NEXT:    v_lshrrev_b32_e32 v2, 17, v2
1685; GCN-NEXT:    v_mul_lo_u32 v3, v1, v2
1686; GCN-NEXT:    v_mul_hi_u32 v4, v0, v2
1687; GCN-NEXT:    v_mul_lo_u32 v2, v0, v2
1688; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
1689; GCN-NEXT:    v_sub_i32_e32 v4, vcc, 0, v3
1690; GCN-NEXT:    v_sub_i32_e32 v2, vcc, 0x8000, v2
1691; GCN-NEXT:    v_subb_u32_e64 v4, s[4:5], v4, v1, vcc
1692; GCN-NEXT:    v_sub_i32_e64 v5, s[4:5], v2, v0
1693; GCN-NEXT:    v_subbrev_u32_e64 v6, s[6:7], 0, v4, s[4:5]
1694; GCN-NEXT:    v_cmp_ge_u32_e64 s[6:7], v6, v1
1695; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[6:7]
1696; GCN-NEXT:    v_cmp_ge_u32_e64 s[6:7], v5, v0
1697; GCN-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[6:7]
1698; GCN-NEXT:    v_cmp_eq_u32_e64 s[6:7], v6, v1
1699; GCN-NEXT:    v_subb_u32_e64 v4, s[4:5], v4, v1, s[4:5]
1700; GCN-NEXT:    v_cndmask_b32_e64 v7, v7, v8, s[6:7]
1701; GCN-NEXT:    v_sub_i32_e64 v8, s[4:5], v5, v0
1702; GCN-NEXT:    v_subb_u32_e32 v3, vcc, 0, v3, vcc
1703; GCN-NEXT:    v_subbrev_u32_e64 v4, s[4:5], 0, v4, s[4:5]
1704; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v3, v1
1705; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v7
1706; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
1707; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v2, v0
1708; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
1709; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v3, v1
1710; GCN-NEXT:    v_cndmask_b32_e32 v0, v7, v0, vcc
1711; GCN-NEXT:    v_cndmask_b32_e64 v5, v5, v8, s[4:5]
1712; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
1713; GCN-NEXT:    v_cndmask_b32_e64 v1, v6, v4, s[4:5]
1714; GCN-NEXT:    v_cndmask_b32_e32 v0, v2, v5, vcc
1715; GCN-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
1716; GCN-NEXT:    s_setpc_b64 s[30:31]
1717;
1718; GCN-IR-LABEL: v_test_srem_pow2_k_num_i64:
1719; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1720; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1721; GCN-IR-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1722; GCN-IR-NEXT:    v_xor_b32_e32 v0, v0, v2
1723; GCN-IR-NEXT:    v_xor_b32_e32 v1, v1, v2
1724; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1725; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
1726; GCN-IR-NEXT:    v_ffbh_u32_e32 v2, v0
1727; GCN-IR-NEXT:    v_add_i32_e32 v2, vcc, 32, v2
1728; GCN-IR-NEXT:    v_ffbh_u32_e32 v3, v1
1729; GCN-IR-NEXT:    v_min_u32_e32 v10, v2, v3
1730; GCN-IR-NEXT:    s_movk_i32 s6, 0xffd0
1731; GCN-IR-NEXT:    v_add_i32_e32 v2, vcc, s6, v10
1732; GCN-IR-NEXT:    v_addc_u32_e64 v3, s[6:7], 0, -1, vcc
1733; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
1734; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, 63, v[2:3]
1735; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[6:7], 63, v[2:3]
1736; GCN-IR-NEXT:    v_mov_b32_e32 v4, 0x8000
1737; GCN-IR-NEXT:    s_or_b64 s[4:5], s[4:5], vcc
1738; GCN-IR-NEXT:    v_cndmask_b32_e64 v4, v4, 0, s[4:5]
1739; GCN-IR-NEXT:    s_xor_b64 s[4:5], s[4:5], -1
1740; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1741; GCN-IR-NEXT:    s_and_b64 s[4:5], s[4:5], s[6:7]
1742; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
1743; GCN-IR-NEXT:    s_cbranch_execz .LBB12_6
1744; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1745; GCN-IR-NEXT:    v_add_i32_e32 v6, vcc, 1, v2
1746; GCN-IR-NEXT:    v_sub_i32_e64 v2, s[4:5], 63, v2
1747; GCN-IR-NEXT:    v_addc_u32_e32 v7, vcc, 0, v3, vcc
1748; GCN-IR-NEXT:    s_mov_b64 s[4:5], 0x8000
1749; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 0, v[6:7]
1750; GCN-IR-NEXT:    v_lshl_b64 v[2:3], s[4:5], v2
1751; GCN-IR-NEXT:    v_mov_b32_e32 v4, 0
1752; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1753; GCN-IR-NEXT:    s_and_saveexec_b64 s[8:9], vcc
1754; GCN-IR-NEXT:    s_xor_b64 s[8:9], exec, s[8:9]
1755; GCN-IR-NEXT:    s_cbranch_execz .LBB12_5
1756; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1757; GCN-IR-NEXT:    v_add_i32_e32 v12, vcc, -1, v0
1758; GCN-IR-NEXT:    v_addc_u32_e32 v13, vcc, -1, v1, vcc
1759; GCN-IR-NEXT:    v_lshr_b64 v[8:9], s[4:5], v6
1760; GCN-IR-NEXT:    v_sub_i32_e32 v6, vcc, 47, v10
1761; GCN-IR-NEXT:    v_mov_b32_e32 v10, 0
1762; GCN-IR-NEXT:    v_subb_u32_e64 v7, s[4:5], 0, 0, vcc
1763; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
1764; GCN-IR-NEXT:    v_mov_b32_e32 v11, 0
1765; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1766; GCN-IR-NEXT:  .LBB12_3: ; %udiv-do-while
1767; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1768; GCN-IR-NEXT:    v_lshl_b64 v[8:9], v[8:9], 1
1769; GCN-IR-NEXT:    v_lshrrev_b32_e32 v4, 31, v3
1770; GCN-IR-NEXT:    v_or_b32_e32 v8, v8, v4
1771; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[2:3], 1
1772; GCN-IR-NEXT:    v_sub_i32_e32 v4, vcc, v12, v8
1773; GCN-IR-NEXT:    v_subb_u32_e32 v4, vcc, v13, v9, vcc
1774; GCN-IR-NEXT:    v_or_b32_e32 v2, v10, v2
1775; GCN-IR-NEXT:    v_ashrrev_i32_e32 v10, 31, v4
1776; GCN-IR-NEXT:    v_add_i32_e32 v6, vcc, 1, v6
1777; GCN-IR-NEXT:    v_or_b32_e32 v3, v11, v3
1778; GCN-IR-NEXT:    v_and_b32_e32 v4, 1, v10
1779; GCN-IR-NEXT:    v_and_b32_e32 v11, v10, v1
1780; GCN-IR-NEXT:    v_and_b32_e32 v10, v10, v0
1781; GCN-IR-NEXT:    v_addc_u32_e32 v7, vcc, 0, v7, vcc
1782; GCN-IR-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[6:7]
1783; GCN-IR-NEXT:    v_sub_i32_e64 v8, s[4:5], v8, v10
1784; GCN-IR-NEXT:    v_subb_u32_e64 v9, s[4:5], v9, v11, s[4:5]
1785; GCN-IR-NEXT:    v_mov_b32_e32 v11, v5
1786; GCN-IR-NEXT:    s_or_b64 s[10:11], vcc, s[10:11]
1787; GCN-IR-NEXT:    v_mov_b32_e32 v10, v4
1788; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[10:11]
1789; GCN-IR-NEXT:    s_cbranch_execnz .LBB12_3
1790; GCN-IR-NEXT:  ; %bb.4: ; %Flow
1791; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
1792; GCN-IR-NEXT:  .LBB12_5: ; %Flow4
1793; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
1794; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[2:3], 1
1795; GCN-IR-NEXT:    v_or_b32_e32 v5, v5, v3
1796; GCN-IR-NEXT:    v_or_b32_e32 v4, v4, v2
1797; GCN-IR-NEXT:  .LBB12_6: ; %Flow5
1798; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
1799; GCN-IR-NEXT:    v_mul_lo_u32 v2, v0, v5
1800; GCN-IR-NEXT:    v_mul_hi_u32 v3, v0, v4
1801; GCN-IR-NEXT:    v_mul_lo_u32 v1, v1, v4
1802; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, v4
1803; GCN-IR-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
1804; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
1805; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 0x8000, v0
1806; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, 0, v1, vcc
1807; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1808  %result = srem i64 32768, %x
1809  ret i64 %result
1810}
1811
1812define i64 @v_test_srem_pow2_k_den_i64(i64 %x) {
1813; GCN-LABEL: v_test_srem_pow2_k_den_i64:
1814; GCN:       ; %bb.0:
1815; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1816; GCN-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1817; GCN-NEXT:    v_lshrrev_b32_e32 v2, 17, v2
1818; GCN-NEXT:    v_add_i32_e32 v2, vcc, v0, v2
1819; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v1, vcc
1820; GCN-NEXT:    v_and_b32_e32 v2, 0xffff8000, v2
1821; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1822; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v3, vcc
1823; GCN-NEXT:    s_setpc_b64 s[30:31]
1824;
1825; GCN-IR-LABEL: v_test_srem_pow2_k_den_i64:
1826; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1827; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1828; GCN-IR-NEXT:    v_ashrrev_i32_e32 v12, 31, v1
1829; GCN-IR-NEXT:    v_xor_b32_e32 v0, v0, v12
1830; GCN-IR-NEXT:    v_xor_b32_e32 v1, v1, v12
1831; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v12
1832; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v12, vcc
1833; GCN-IR-NEXT:    v_ffbh_u32_e32 v2, v0
1834; GCN-IR-NEXT:    v_add_i32_e64 v2, s[4:5], 32, v2
1835; GCN-IR-NEXT:    v_ffbh_u32_e32 v3, v1
1836; GCN-IR-NEXT:    v_min_u32_e32 v10, v2, v3
1837; GCN-IR-NEXT:    v_sub_i32_e64 v2, s[4:5], 48, v10
1838; GCN-IR-NEXT:    v_subb_u32_e64 v3, s[4:5], 0, 0, s[4:5]
1839; GCN-IR-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[0:1]
1840; GCN-IR-NEXT:    v_cmp_lt_u64_e64 s[4:5], 63, v[2:3]
1841; GCN-IR-NEXT:    v_mov_b32_e32 v13, v12
1842; GCN-IR-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
1843; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[2:3]
1844; GCN-IR-NEXT:    s_xor_b64 s[6:7], s[4:5], -1
1845; GCN-IR-NEXT:    v_cndmask_b32_e64 v5, v1, 0, s[4:5]
1846; GCN-IR-NEXT:    v_cndmask_b32_e64 v4, v0, 0, s[4:5]
1847; GCN-IR-NEXT:    s_and_b64 s[4:5], s[6:7], vcc
1848; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
1849; GCN-IR-NEXT:    s_cbranch_execz .LBB13_6
1850; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1851; GCN-IR-NEXT:    v_add_i32_e32 v6, vcc, 1, v2
1852; GCN-IR-NEXT:    v_addc_u32_e32 v7, vcc, 0, v3, vcc
1853; GCN-IR-NEXT:    v_sub_i32_e64 v2, s[4:5], 63, v2
1854; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 0, v[6:7]
1855; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[0:1], v2
1856; GCN-IR-NEXT:    v_mov_b32_e32 v4, 0
1857; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1858; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
1859; GCN-IR-NEXT:    s_xor_b64 s[8:9], exec, s[4:5]
1860; GCN-IR-NEXT:    s_cbranch_execz .LBB13_5
1861; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1862; GCN-IR-NEXT:    v_lshr_b64 v[8:9], v[0:1], v6
1863; GCN-IR-NEXT:    v_add_i32_e32 v6, vcc, 0xffffffcf, v10
1864; GCN-IR-NEXT:    v_mov_b32_e32 v10, 0
1865; GCN-IR-NEXT:    v_addc_u32_e64 v7, s[4:5], 0, -1, vcc
1866; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
1867; GCN-IR-NEXT:    v_mov_b32_e32 v11, 0
1868; GCN-IR-NEXT:    s_movk_i32 s12, 0x7fff
1869; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1870; GCN-IR-NEXT:  .LBB13_3: ; %udiv-do-while
1871; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1872; GCN-IR-NEXT:    v_lshl_b64 v[8:9], v[8:9], 1
1873; GCN-IR-NEXT:    v_lshrrev_b32_e32 v4, 31, v3
1874; GCN-IR-NEXT:    v_or_b32_e32 v8, v8, v4
1875; GCN-IR-NEXT:    v_sub_i32_e32 v4, vcc, s12, v8
1876; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[2:3], 1
1877; GCN-IR-NEXT:    v_subb_u32_e32 v4, vcc, 0, v9, vcc
1878; GCN-IR-NEXT:    v_add_i32_e32 v6, vcc, 1, v6
1879; GCN-IR-NEXT:    v_or_b32_e32 v2, v10, v2
1880; GCN-IR-NEXT:    v_ashrrev_i32_e32 v10, 31, v4
1881; GCN-IR-NEXT:    v_addc_u32_e32 v7, vcc, 0, v7, vcc
1882; GCN-IR-NEXT:    v_and_b32_e32 v4, 1, v10
1883; GCN-IR-NEXT:    v_and_b32_e32 v10, 0x8000, v10
1884; GCN-IR-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[6:7]
1885; GCN-IR-NEXT:    v_or_b32_e32 v3, v11, v3
1886; GCN-IR-NEXT:    v_sub_i32_e64 v8, s[4:5], v8, v10
1887; GCN-IR-NEXT:    v_mov_b32_e32 v11, v5
1888; GCN-IR-NEXT:    v_subbrev_u32_e64 v9, s[4:5], 0, v9, s[4:5]
1889; GCN-IR-NEXT:    s_or_b64 s[10:11], vcc, s[10:11]
1890; GCN-IR-NEXT:    v_mov_b32_e32 v10, v4
1891; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[10:11]
1892; GCN-IR-NEXT:    s_cbranch_execnz .LBB13_3
1893; GCN-IR-NEXT:  ; %bb.4: ; %Flow
1894; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
1895; GCN-IR-NEXT:  .LBB13_5: ; %Flow4
1896; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
1897; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[2:3], 1
1898; GCN-IR-NEXT:    v_or_b32_e32 v5, v5, v3
1899; GCN-IR-NEXT:    v_or_b32_e32 v4, v4, v2
1900; GCN-IR-NEXT:  .LBB13_6: ; %Flow5
1901; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
1902; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[4:5], 15
1903; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1904; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v3, vcc
1905; GCN-IR-NEXT:    v_xor_b32_e32 v0, v0, v12
1906; GCN-IR-NEXT:    v_xor_b32_e32 v1, v1, v13
1907; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v12
1908; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v13, vcc
1909; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1910  %result = srem i64 %x, 32768
1911  ret i64 %result
1912}
1913
1914define amdgpu_kernel void @s_test_srem24_k_num_i64(ptr addrspace(1) %out, i64 %x) {
1915; GCN-LABEL: s_test_srem24_k_num_i64:
1916; GCN:       ; %bb.0:
1917; GCN-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x9
1918; GCN-NEXT:    s_mov_b32 s7, 0xf000
1919; GCN-NEXT:    s_mov_b32 s6, -1
1920; GCN-NEXT:    s_waitcnt lgkmcnt(0)
1921; GCN-NEXT:    s_ashr_i64 s[2:3], s[2:3], 40
1922; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s2
1923; GCN-NEXT:    s_mov_b32 s3, 0x41c00000
1924; GCN-NEXT:    s_mov_b32 s4, s0
1925; GCN-NEXT:    s_ashr_i32 s0, s2, 30
1926; GCN-NEXT:    v_rcp_iflag_f32_e32 v1, v0
1927; GCN-NEXT:    s_mov_b32 s5, s1
1928; GCN-NEXT:    s_or_b32 s8, s0, 1
1929; GCN-NEXT:    v_mul_f32_e32 v1, 0x41c00000, v1
1930; GCN-NEXT:    v_trunc_f32_e32 v1, v1
1931; GCN-NEXT:    v_mad_f32 v2, -v1, v0, s3
1932; GCN-NEXT:    v_cvt_i32_f32_e32 v1, v1
1933; GCN-NEXT:    v_cmp_ge_f32_e64 s[0:1], |v2|, |v0|
1934; GCN-NEXT:    s_and_b64 s[0:1], s[0:1], exec
1935; GCN-NEXT:    s_cselect_b32 s0, s8, 0
1936; GCN-NEXT:    v_readfirstlane_b32 s1, v1
1937; GCN-NEXT:    s_add_i32 s0, s1, s0
1938; GCN-NEXT:    s_mul_i32 s0, s0, s2
1939; GCN-NEXT:    s_sub_i32 s0, 24, s0
1940; GCN-NEXT:    s_bfe_i32 s0, s0, 0x180000
1941; GCN-NEXT:    s_ashr_i32 s1, s0, 31
1942; GCN-NEXT:    v_mov_b32_e32 v0, s0
1943; GCN-NEXT:    v_mov_b32_e32 v1, s1
1944; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1945; GCN-NEXT:    s_endpgm
1946;
1947; GCN-IR-LABEL: s_test_srem24_k_num_i64:
1948; GCN-IR:       ; %bb.0:
1949; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x9
1950; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
1951; GCN-IR-NEXT:    s_mov_b32 s6, -1
1952; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1953; GCN-IR-NEXT:    s_ashr_i64 s[2:3], s[2:3], 40
1954; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s2
1955; GCN-IR-NEXT:    s_mov_b32 s3, 0x41c00000
1956; GCN-IR-NEXT:    s_mov_b32 s4, s0
1957; GCN-IR-NEXT:    s_ashr_i32 s0, s2, 30
1958; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v1, v0
1959; GCN-IR-NEXT:    s_mov_b32 s5, s1
1960; GCN-IR-NEXT:    s_or_b32 s8, s0, 1
1961; GCN-IR-NEXT:    v_mul_f32_e32 v1, 0x41c00000, v1
1962; GCN-IR-NEXT:    v_trunc_f32_e32 v1, v1
1963; GCN-IR-NEXT:    v_mad_f32 v2, -v1, v0, s3
1964; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v1, v1
1965; GCN-IR-NEXT:    v_cmp_ge_f32_e64 s[0:1], |v2|, |v0|
1966; GCN-IR-NEXT:    s_and_b64 s[0:1], s[0:1], exec
1967; GCN-IR-NEXT:    s_cselect_b32 s0, s8, 0
1968; GCN-IR-NEXT:    v_readfirstlane_b32 s1, v1
1969; GCN-IR-NEXT:    s_add_i32 s0, s1, s0
1970; GCN-IR-NEXT:    s_mul_i32 s0, s0, s2
1971; GCN-IR-NEXT:    s_sub_i32 s0, 24, s0
1972; GCN-IR-NEXT:    s_bfe_i32 s0, s0, 0x180000
1973; GCN-IR-NEXT:    s_ashr_i32 s1, s0, 31
1974; GCN-IR-NEXT:    v_mov_b32_e32 v0, s0
1975; GCN-IR-NEXT:    v_mov_b32_e32 v1, s1
1976; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1977; GCN-IR-NEXT:    s_endpgm
1978  %x.shr = ashr i64 %x, 40
1979  %result = srem i64 24, %x.shr
1980  store i64 %result, ptr addrspace(1) %out
1981  ret void
1982}
1983
1984define amdgpu_kernel void @s_test_srem24_k_den_i64(ptr addrspace(1) %out, i64 %x) {
1985; GCN-LABEL: s_test_srem24_k_den_i64:
1986; GCN:       ; %bb.0:
1987; GCN-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x9
1988; GCN-NEXT:    s_mov_b32 s8, 0x46b6fe00
1989; GCN-NEXT:    s_mov_b32 s7, 0xf000
1990; GCN-NEXT:    s_mov_b32 s6, -1
1991; GCN-NEXT:    s_waitcnt lgkmcnt(0)
1992; GCN-NEXT:    s_ashr_i64 s[2:3], s[2:3], 40
1993; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s2
1994; GCN-NEXT:    s_mov_b32 s4, s0
1995; GCN-NEXT:    s_ashr_i32 s0, s2, 30
1996; GCN-NEXT:    s_mov_b32 s5, s1
1997; GCN-NEXT:    v_mul_f32_e32 v1, 0x38331158, v0
1998; GCN-NEXT:    v_trunc_f32_e32 v1, v1
1999; GCN-NEXT:    v_mad_f32 v0, -v1, s8, v0
2000; GCN-NEXT:    v_cvt_i32_f32_e32 v1, v1
2001; GCN-NEXT:    s_or_b32 s3, s0, 1
2002; GCN-NEXT:    v_cmp_ge_f32_e64 s[0:1], |v0|, s8
2003; GCN-NEXT:    s_and_b64 s[0:1], s[0:1], exec
2004; GCN-NEXT:    s_cselect_b32 s0, s3, 0
2005; GCN-NEXT:    v_readfirstlane_b32 s1, v1
2006; GCN-NEXT:    s_add_i32 s0, s1, s0
2007; GCN-NEXT:    s_mulk_i32 s0, 0x5b7f
2008; GCN-NEXT:    s_sub_i32 s0, s2, s0
2009; GCN-NEXT:    s_bfe_i32 s0, s0, 0x180000
2010; GCN-NEXT:    s_ashr_i32 s1, s0, 31
2011; GCN-NEXT:    v_mov_b32_e32 v0, s0
2012; GCN-NEXT:    v_mov_b32_e32 v1, s1
2013; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
2014; GCN-NEXT:    s_endpgm
2015;
2016; GCN-IR-LABEL: s_test_srem24_k_den_i64:
2017; GCN-IR:       ; %bb.0:
2018; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x9
2019; GCN-IR-NEXT:    s_mov_b32 s8, 0x46b6fe00
2020; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
2021; GCN-IR-NEXT:    s_mov_b32 s6, -1
2022; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
2023; GCN-IR-NEXT:    s_ashr_i64 s[2:3], s[2:3], 40
2024; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s2
2025; GCN-IR-NEXT:    s_mov_b32 s4, s0
2026; GCN-IR-NEXT:    s_ashr_i32 s0, s2, 30
2027; GCN-IR-NEXT:    s_mov_b32 s5, s1
2028; GCN-IR-NEXT:    v_mul_f32_e32 v1, 0x38331158, v0
2029; GCN-IR-NEXT:    v_trunc_f32_e32 v1, v1
2030; GCN-IR-NEXT:    v_mad_f32 v0, -v1, s8, v0
2031; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v1, v1
2032; GCN-IR-NEXT:    s_or_b32 s3, s0, 1
2033; GCN-IR-NEXT:    v_cmp_ge_f32_e64 s[0:1], |v0|, s8
2034; GCN-IR-NEXT:    s_and_b64 s[0:1], s[0:1], exec
2035; GCN-IR-NEXT:    s_cselect_b32 s0, s3, 0
2036; GCN-IR-NEXT:    v_readfirstlane_b32 s1, v1
2037; GCN-IR-NEXT:    s_add_i32 s0, s1, s0
2038; GCN-IR-NEXT:    s_mulk_i32 s0, 0x5b7f
2039; GCN-IR-NEXT:    s_sub_i32 s0, s2, s0
2040; GCN-IR-NEXT:    s_bfe_i32 s0, s0, 0x180000
2041; GCN-IR-NEXT:    s_ashr_i32 s1, s0, 31
2042; GCN-IR-NEXT:    v_mov_b32_e32 v0, s0
2043; GCN-IR-NEXT:    v_mov_b32_e32 v1, s1
2044; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
2045; GCN-IR-NEXT:    s_endpgm
2046  %x.shr = ashr i64 %x, 40
2047  %result = srem i64 %x.shr, 23423
2048  store i64 %result, ptr addrspace(1) %out
2049  ret void
2050}
2051
2052define i64 @v_test_srem24_k_num_i64(i64 %x) {
2053; GCN-LABEL: v_test_srem24_k_num_i64:
2054; GCN:       ; %bb.0:
2055; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2056; GCN-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
2057; GCN-NEXT:    s_mov_b32 s4, 0x41c00000
2058; GCN-NEXT:    v_cvt_f32_i32_e32 v1, v0
2059; GCN-NEXT:    v_ashrrev_i32_e32 v3, 30, v0
2060; GCN-NEXT:    v_or_b32_e32 v3, 1, v3
2061; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v1
2062; GCN-NEXT:    v_mul_f32_e32 v2, 0x41c00000, v2
2063; GCN-NEXT:    v_trunc_f32_e32 v2, v2
2064; GCN-NEXT:    v_mad_f32 v4, -v2, v1, s4
2065; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
2066; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, |v1|
2067; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v3, vcc
2068; GCN-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
2069; GCN-NEXT:    v_mul_lo_u32 v0, v1, v0
2070; GCN-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
2071; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
2072; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2073; GCN-NEXT:    s_setpc_b64 s[30:31]
2074;
2075; GCN-IR-LABEL: v_test_srem24_k_num_i64:
2076; GCN-IR:       ; %bb.0:
2077; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2078; GCN-IR-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
2079; GCN-IR-NEXT:    s_mov_b32 s4, 0x41c00000
2080; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, v0
2081; GCN-IR-NEXT:    v_ashrrev_i32_e32 v3, 30, v0
2082; GCN-IR-NEXT:    v_or_b32_e32 v3, 1, v3
2083; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v1
2084; GCN-IR-NEXT:    v_mul_f32_e32 v2, 0x41c00000, v2
2085; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
2086; GCN-IR-NEXT:    v_mad_f32 v4, -v2, v1, s4
2087; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
2088; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, |v1|
2089; GCN-IR-NEXT:    v_cndmask_b32_e32 v1, 0, v3, vcc
2090; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
2091; GCN-IR-NEXT:    v_mul_lo_u32 v0, v1, v0
2092; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
2093; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
2094; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2095; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
2096  %x.shr = ashr i64 %x, 40
2097  %result = srem i64 24, %x.shr
2098  ret i64 %result
2099}
2100
2101define i64 @v_test_srem24_pow2_k_num_i64(i64 %x) {
2102; GCN-LABEL: v_test_srem24_pow2_k_num_i64:
2103; GCN:       ; %bb.0:
2104; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2105; GCN-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
2106; GCN-NEXT:    s_mov_b32 s4, 0x47000000
2107; GCN-NEXT:    v_cvt_f32_i32_e32 v1, v0
2108; GCN-NEXT:    v_ashrrev_i32_e32 v3, 30, v0
2109; GCN-NEXT:    v_or_b32_e32 v3, 1, v3
2110; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v1
2111; GCN-NEXT:    v_mul_f32_e32 v2, 0x47000000, v2
2112; GCN-NEXT:    v_trunc_f32_e32 v2, v2
2113; GCN-NEXT:    v_mad_f32 v4, -v2, v1, s4
2114; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
2115; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, |v1|
2116; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v3, vcc
2117; GCN-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
2118; GCN-NEXT:    v_mul_lo_u32 v0, v1, v0
2119; GCN-NEXT:    v_sub_i32_e32 v0, vcc, 0x8000, v0
2120; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
2121; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2122; GCN-NEXT:    s_setpc_b64 s[30:31]
2123;
2124; GCN-IR-LABEL: v_test_srem24_pow2_k_num_i64:
2125; GCN-IR:       ; %bb.0:
2126; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2127; GCN-IR-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
2128; GCN-IR-NEXT:    s_mov_b32 s4, 0x47000000
2129; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, v0
2130; GCN-IR-NEXT:    v_ashrrev_i32_e32 v3, 30, v0
2131; GCN-IR-NEXT:    v_or_b32_e32 v3, 1, v3
2132; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v1
2133; GCN-IR-NEXT:    v_mul_f32_e32 v2, 0x47000000, v2
2134; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
2135; GCN-IR-NEXT:    v_mad_f32 v4, -v2, v1, s4
2136; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
2137; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, |v1|
2138; GCN-IR-NEXT:    v_cndmask_b32_e32 v1, 0, v3, vcc
2139; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
2140; GCN-IR-NEXT:    v_mul_lo_u32 v0, v1, v0
2141; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 0x8000, v0
2142; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
2143; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2144; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
2145  %x.shr = ashr i64 %x, 40
2146  %result = srem i64 32768, %x.shr
2147  ret i64 %result
2148}
2149
2150define i64 @v_test_srem24_pow2_k_den_i64(i64 %x) {
2151; GCN-LABEL: v_test_srem24_pow2_k_den_i64:
2152; GCN:       ; %bb.0:
2153; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2154; GCN-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
2155; GCN-NEXT:    v_lshrrev_b32_e32 v2, 17, v1
2156; GCN-NEXT:    v_add_i32_e32 v2, vcc, v0, v2
2157; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v1, vcc
2158; GCN-NEXT:    v_and_b32_e32 v2, 0xffff8000, v2
2159; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
2160; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v3, vcc
2161; GCN-NEXT:    s_setpc_b64 s[30:31]
2162;
2163; GCN-IR-LABEL: v_test_srem24_pow2_k_den_i64:
2164; GCN-IR:       ; %bb.0:
2165; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2166; GCN-IR-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
2167; GCN-IR-NEXT:    s_mov_b32 s4, 0x47000000
2168; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, v0
2169; GCN-IR-NEXT:    v_ashrrev_i32_e32 v2, 30, v0
2170; GCN-IR-NEXT:    v_or_b32_e32 v2, 1, v2
2171; GCN-IR-NEXT:    v_mul_f32_e32 v3, 0x38000000, v1
2172; GCN-IR-NEXT:    v_trunc_f32_e32 v3, v3
2173; GCN-IR-NEXT:    v_mad_f32 v1, -v3, s4, v1
2174; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v3, v3
2175; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, s4
2176; GCN-IR-NEXT:    v_cndmask_b32_e32 v1, 0, v2, vcc
2177; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v3, v1
2178; GCN-IR-NEXT:    v_lshlrev_b32_e32 v1, 15, v1
2179; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v1
2180; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
2181; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2182; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
2183  %x.shr = ashr i64 %x, 40
2184  %result = srem i64 %x.shr, 32768
2185  ret i64 %result
2186}
2187