xref: /llvm-project/llvm/test/CodeGen/AMDGPU/si-fold-reg-sequence.mir (revision 04db60d15069494f4effad7a1001965904b36e6f)
1# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=si-fold-operands -verify-machineinstrs -o - %s
2
3---
4name:            fold_reg_sequence
5body:             |
6  bb.0:
7    liveins: $vgpr0_vgpr1, $vgpr2
8
9    %0:sreg_32 = S_MOV_B32 0
10    %1:sreg_32 = S_MOV_B32 429
11    %2:sreg_64 = REG_SEQUENCE killed %1, %subreg.sub0, %0, %subreg.sub1
12    %3:vgpr_32 = V_MUL_HI_U32_e64 $vgpr2, %2.sub0, implicit $exec
13    %4:vgpr_32 = GLOBAL_LOAD_DWORD $vgpr0_vgpr1, 0, 0, implicit $exec :: (load (s32), addrspace 1)
14    %5:vgpr_32 = V_MUL_HI_U32_e64 %4, %2.sub0, implicit $exec
15    S_ENDPGM 0
16
17...
18
19