1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt -mtriple=amdgcn-amd-amdhsa -p simplifycfg,amdgpu-unify-divergent-exit-nodes %s -S -o - | FileCheck %s --check-prefix=OPT 3; RUN: llc -mtriple=amdgcn-amd-amdhsa %s -o - | FileCheck %s --check-prefix=ISA 4 5define void @nested_inf_loop(i1 %0, i1 %1) { 6; OPT-LABEL: @nested_inf_loop( 7; OPT-NEXT: BB: 8; OPT-NEXT: br label [[BB1:%.*]] 9; OPT: BB1: 10; OPT-NEXT: [[BRMERGE:%.*]] = select i1 [[TMP0:%.*]], i1 true, i1 [[TMP1:%.*]] 11; OPT-NEXT: br i1 [[BRMERGE]], label [[BB1]], label [[INFLOOP:%.*]] 12; OPT: infloop: 13; OPT-NEXT: br i1 true, label [[INFLOOP]], label [[DUMMYRETURNBLOCK:%.*]] 14; OPT: DummyReturnBlock: 15; OPT-NEXT: ret void 16; 17; ISA-LABEL: nested_inf_loop: 18; ISA-NEXT: %bb.0: ; %BB 19; ISA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 20; ISA-NEXT: v_and_b32_e32 v1, 1, v1 21; ISA-NEXT: v_and_b32_e32 v0, 1, v0 22; ISA-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v1 23; ISA-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0 24; ISA-NEXT: s_xor_b64 s[6:7], vcc, -1 25; ISA-NEXT: s_mov_b64 s[8:9], 0 26; ISA-NEXT: .LBB0_1: ; %BB1 27; ISA: s_and_b64 s[10:11], exec, s[6:7] 28; ISA-NEXT: s_or_b64 s[8:9], s[10:11], s[8:9] 29; ISA-NEXT: s_andn2_b64 exec, exec, s[8:9] 30; ISA-NEXT: s_cbranch_execnz .LBB0_1 31; ISA-NEXT: %bb.2: ; %BB2 32; ISA: s_or_b64 exec, exec, s[8:9] 33; ISA-NEXT: s_mov_b64 s[8:9], 0 34; ISA-NEXT: .LBB0_3: ; %BB4 35; ISA: s_and_b64 s[10:11], exec, s[4:5] 36; ISA-NEXT: s_or_b64 s[8:9], s[10:11], s[8:9] 37; ISA-NEXT: s_andn2_b64 exec, exec, s[8:9] 38; ISA-NEXT: s_cbranch_execnz .LBB0_3 39; ISA-NEXT: %bb.4: ; %loop.exit.guard 40; ISA: s_or_b64 exec, exec, s[8:9] 41; ISA-NEXT: s_mov_b64 vcc, 0 42; ISA-NEXT: s_mov_b64 s[8:9], 0 43; ISA-NEXT: s_branch .LBB0_1 44; ISA-NEXT: %bb.5: ; %DummyReturnBlock 45; ISA-NEXT: s_setpc_b64 s[30:31] 46BB: 47 br label %BB1 48 49BB1: 50 br i1 %0, label %BB3, label %BB2 51 52BB2: 53 br label %BB4 54 55BB4: 56 br i1 %1, label %BB3, label %BB4 57 58BB3: 59 br label %BB1 60} 61