xref: /llvm-project/llvm/test/CodeGen/AMDGPU/select64.ll (revision 9e9907f1cfa424366fba58d9520f9305b537cec9)
1; RUN: llc < %s -mtriple=amdgcn -mcpu=tahiti -verify-machineinstrs | FileCheck -check-prefix=GCN %s
2; RUN: llc < %s -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck -check-prefix=GCN %s
3
4; GCN-LABEL: {{^}}select0:
5; i64 select should be split into two i32 selects, and we shouldn't need
6; to use a shfit to extract the hi dword of the input.
7; GCN-NOT: s_lshr_b64
8; GCN: s_cselect_b32
9; GCN: s_cselect_b32
10define amdgpu_kernel void @select0(ptr addrspace(1) %out, i32 %cond, i64 %in) {
11entry:
12  %0 = icmp ugt i32 %cond, 5
13  %1 = select i1 %0, i64 0, i64 %in
14  store i64 %1, ptr addrspace(1) %out
15  ret void
16}
17
18; GCN-LABEL: {{^}}select_trunc_i64:
19; GCN: s_cselect_b32
20; GCN-NOT: s_cselect_b32
21define amdgpu_kernel void @select_trunc_i64(ptr addrspace(1) %out, i32 %cond, i64 %in) nounwind {
22  %cmp = icmp ugt i32 %cond, 5
23  %sel = select i1 %cmp, i64 0, i64 %in
24  %trunc = trunc i64 %sel to i32
25  store i32 %trunc, ptr addrspace(1) %out, align 4
26  ret void
27}
28
29; GCN-LABEL: {{^}}select_trunc_i64_2:
30; GCN: s_cselect_b32
31; GCN-NOT: s_cselect_b32
32define amdgpu_kernel void @select_trunc_i64_2(ptr addrspace(1) %out, i32 %cond, i64 %a, i64 %b) nounwind {
33  %cmp = icmp ugt i32 %cond, 5
34  %sel = select i1 %cmp, i64 %a, i64 %b
35  %trunc = trunc i64 %sel to i32
36  store i32 %trunc, ptr addrspace(1) %out, align 4
37  ret void
38}
39
40; GCN-LABEL: {{^}}v_select_trunc_i64_2:
41; GCN: s_cselect_b32
42; GCN-NOT: s_cselect_b32
43define amdgpu_kernel void @v_select_trunc_i64_2(ptr addrspace(1) %out, i32 %cond, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr) nounwind {
44  %cmp = icmp ugt i32 %cond, 5
45  %a = load i64, ptr addrspace(1) %aptr, align 8
46  %b = load i64, ptr addrspace(1) %bptr, align 8
47  %sel = select i1 %cmp, i64 %a, i64 %b
48  %trunc = trunc i64 %sel to i32
49  store i32 %trunc, ptr addrspace(1) %out, align 4
50  ret void
51}
52
53; GCN-LABEL: {{^}}v_select_i64_split_imm:
54; GCN-DAG: s_cselect_b32
55; GCN-DAG: s_cselect_b32
56; GCN: s_endpgm
57define amdgpu_kernel void @v_select_i64_split_imm(ptr addrspace(1) %out, i32 %cond, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr) nounwind {
58  %cmp = icmp ugt i32 %cond, 5
59  %a = load i64, ptr addrspace(1) %aptr, align 8
60  %b = load i64, ptr addrspace(1) %bptr, align 8
61  %sel = select i1 %cmp, i64 %a, i64 270582939648 ; 63 << 32
62  store i64 %sel, ptr addrspace(1) %out, align 8
63  ret void
64}
65