1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 %s -o - | FileCheck %s 3 4define i32 @xori64i32(i64 %a) { 5; CHECK-LABEL: xori64i32: 6; CHECK: ; %bb.0: 7; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 8; CHECK-NEXT: v_ashrrev_i32_e32 v0, 31, v1 9; CHECK-NEXT: v_xor_b32_e32 v0, 0x7fffffff, v0 10; CHECK-NEXT: s_setpc_b64 s[30:31] 11 %shr4 = ashr i64 %a, 63 12 %conv5 = trunc i64 %shr4 to i32 13 %xor = xor i32 %conv5, 2147483647 14 ret i32 %xor 15} 16 17define i64 @selecti64i64(i64 %a) { 18; CHECK-LABEL: selecti64i64: 19; CHECK: ; %bb.0: 20; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 21; CHECK-NEXT: v_ashrrev_i32_e32 v1, 31, v1 22; CHECK-NEXT: v_xor_b32_e32 v0, 0x7fffffff, v1 23; CHECK-NEXT: s_setpc_b64 s[30:31] 24 %c = icmp sgt i64 %a, -1 25 %s = select i1 %c, i64 2147483647, i64 -2147483648 26 ret i64 %s 27} 28 29define i32 @selecti64i32(i64 %a) { 30; CHECK-LABEL: selecti64i32: 31; CHECK: ; %bb.0: 32; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 33; CHECK-NEXT: v_ashrrev_i32_e32 v0, 31, v1 34; CHECK-NEXT: v_xor_b32_e32 v0, 0x7fffffff, v0 35; CHECK-NEXT: s_setpc_b64 s[30:31] 36 %c = icmp sgt i64 %a, -1 37 %s = select i1 %c, i32 2147483647, i32 -2147483648 38 ret i32 %s 39} 40 41define i64 @selecti32i64(i32 %a) { 42; CHECK-LABEL: selecti32i64: 43; CHECK: ; %bb.0: 44; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 45; CHECK-NEXT: v_ashrrev_i32_e32 v1, 31, v0 46; CHECK-NEXT: v_xor_b32_e32 v0, 0x7fffffff, v1 47; CHECK-NEXT: v_ashrrev_i32_e32 v1, 31, v1 48; CHECK-NEXT: s_setpc_b64 s[30:31] 49 %c = icmp sgt i32 %a, -1 50 %s = select i1 %c, i64 2147483647, i64 -2147483648 51 ret i64 %s 52} 53 54 55 56define i8 @xori32i8(i32 %a) { 57; CHECK-LABEL: xori32i8: 58; CHECK: ; %bb.0: 59; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 60; CHECK-NEXT: v_ashrrev_i32_e32 v0, 31, v0 61; CHECK-NEXT: v_xor_b32_e32 v0, 0x54, v0 62; CHECK-NEXT: s_setpc_b64 s[30:31] 63 %shr4 = ashr i32 %a, 31 64 %conv5 = trunc i32 %shr4 to i8 65 %xor = xor i8 %conv5, 84 66 ret i8 %xor 67} 68 69define i32 @selecti32i32(i32 %a) { 70; CHECK-LABEL: selecti32i32: 71; CHECK: ; %bb.0: 72; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 73; CHECK-NEXT: v_ashrrev_i32_e32 v0, 31, v0 74; CHECK-NEXT: v_xor_b32_e32 v0, 0x54, v0 75; CHECK-NEXT: s_setpc_b64 s[30:31] 76 %c = icmp sgt i32 %a, -1 77 %s = select i1 %c, i32 84, i32 -85 78 ret i32 %s 79} 80 81define i8 @selecti32i8(i32 %a) { 82; CHECK-LABEL: selecti32i8: 83; CHECK: ; %bb.0: 84; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 85; CHECK-NEXT: v_ashrrev_i32_e32 v0, 31, v0 86; CHECK-NEXT: v_xor_b32_e32 v0, 0x54, v0 87; CHECK-NEXT: s_setpc_b64 s[30:31] 88 %c = icmp sgt i32 %a, -1 89 %s = select i1 %c, i8 84, i8 -85 90 ret i8 %s 91} 92 93define i32 @selecti8i32(i8 %a) { 94; CHECK-LABEL: selecti8i32: 95; CHECK: ; %bb.0: 96; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 97; CHECK-NEXT: v_bfe_i32 v0, v0, 0, 8 98; CHECK-NEXT: v_mov_b32_e32 v1, 0x54 99; CHECK-NEXT: v_ashrrev_i16 v0, 7, v0 100; CHECK-NEXT: v_xor_b32_sdwa v0, sext(v0), v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD 101; CHECK-NEXT: s_setpc_b64 s[30:31] 102 %c = icmp sgt i8 %a, -1 103 %s = select i1 %c, i32 84, i32 -85 104 ret i32 %s 105} 106 107define i32 @icmpasreq(i32 %input, i32 %a, i32 %b) { 108; CHECK-LABEL: icmpasreq: 109; CHECK: ; %bb.0: 110; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 111; CHECK-NEXT: v_cmp_gt_i32_e32 vcc_lo, 0, v0 112; CHECK-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc_lo 113; CHECK-NEXT: s_setpc_b64 s[30:31] 114 %sh = ashr i32 %input, 31 115 %c = icmp eq i32 %sh, -1 116 %s = select i1 %c, i32 %a, i32 %b 117 ret i32 %s 118} 119 120define i32 @icmpasrne(i32 %input, i32 %a, i32 %b) { 121; CHECK-LABEL: icmpasrne: 122; CHECK: ; %bb.0: 123; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 124; CHECK-NEXT: v_cmp_lt_i32_e32 vcc_lo, -1, v0 125; CHECK-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc_lo 126; CHECK-NEXT: s_setpc_b64 s[30:31] 127 %sh = ashr i32 %input, 31 128 %c = icmp ne i32 %sh, -1 129 %s = select i1 %c, i32 %a, i32 %b 130 ret i32 %s 131} 132 133define i32 @oneusecmp(i32 %a, i32 %b, i32 %d) { 134; CHECK-LABEL: oneusecmp: 135; CHECK: ; %bb.0: 136; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 137; CHECK-NEXT: v_cmp_gt_i32_e32 vcc_lo, 0, v0 138; CHECK-NEXT: v_ashrrev_i32_e32 v3, 31, v0 139; CHECK-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo 140; CHECK-NEXT: v_xad_u32 v0, 0x7f, v3, v0 141; CHECK-NEXT: s_setpc_b64 s[30:31] 142 %c = icmp sle i32 %a, -1 143 %s = select i1 %c, i32 -128, i32 127 144 %s2 = select i1 %c, i32 %d, i32 %b 145 %x = add i32 %s, %s2 146 ret i32 %x 147} 148