xref: /llvm-project/llvm/test/CodeGen/AMDGPU/sdag-print-divergence.ll (revision 9843843c88f6cd8fa68c301ba751c001c254cb63)
1; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -O0 -verify-machineinstrs < %s -debug-only=isel 2>&1 | FileCheck --check-prefixes=GCN,GCN-DEFAULT %s
2; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -O0 -verify-machineinstrs < %s -debug-only=isel -dag-dump-verbose 2>&1 | FileCheck --check-prefixes=GCN,GCN-VERBOSE %s
3
4; REQUIRES: asserts
5
6; GCN-LABEL: === test_sdag_dump
7; GCN: Initial selection DAG: %bb.0 'test_sdag_dump:entry'
8; GCN: SelectionDAG has 10 nodes:
9
10; GCN-DEFAULT:  t0: ch,glue = EntryToken
11; GCN-DEFAULT:  t2: f32,ch = CopyFromReg t0, Register:f32 %0
12; GCN-DEFAULT:      t5: f32 = fadd t2, t2
13; GCN-DEFAULT:      t4: f32,ch = CopyFromReg # D:1 t0, Register:f32 %1
14; GCN-DEFAULT:    t6: f32 = fadd # D:1 t5, t4
15; GCN-DEFAULT:  t8: ch,glue = CopyToReg # D:1 t0, Register:f32 $vgpr0, t6
16; GCN-DEFAULT:  t9: ch = RETURN_TO_EPILOG t8, Register:f32 $vgpr0, t8:1
17
18; GCN-VERBOSE:  t0: ch,glue = EntryToken # D:0
19; GCN-VERBOSE:  t2: f32,ch = CopyFromReg [ORD=1] # D:0 t0, Register:f32 %0 # D:0
20; GCN-VERBOSE:      t5: f32 = fadd [ORD=2] # D:0 t2, t2
21; GCN-VERBOSE:      t4: f32,ch = CopyFromReg [ORD=1] # D:1 t0, Register:f32 %1 # D:0
22; GCN-VERBOSE:    t6: f32 = fadd [ORD=3] # D:1 t5, t4
23; GCN-VERBOSE:  t8: ch,glue = CopyToReg [ORD=4] # D:1 t0, Register:f32 $vgpr0 # D:0, t6
24; GCN-VERBOSE:  t9: ch = RETURN_TO_EPILOG [ORD=4] # D:0 t8, Register:f32 $vgpr0 # D:0, t8:1
25
26define amdgpu_ps float @test_sdag_dump(float inreg %scalar, float %vector)  {
27entry:
28  %sadd = fadd float %scalar, %scalar
29  %ret = fadd float %sadd, %vector
30  ret float %ret
31}
32
33declare i32 @llvm.amdgcn.workitem.id.x()
34