xref: /llvm-project/llvm/test/CodeGen/AMDGPU/scalar_to_vector.v8i16.ll (revision 6548b6354d1d990e1c98736f5e7c3de876bedc8e) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -verify-machineinstrs -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX900 %s
3; RUN: llc -verify-machineinstrs -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 < %s | FileCheck -check-prefixes=GFX906 %s
4; RUN: llc -verify-machineinstrs -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 < %s | FileCheck -check-prefixes=GFX908 %s
5; RUN: llc -verify-machineinstrs -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a < %s | FileCheck -check-prefixes=GFX90A %s
6
7define amdgpu_kernel void @scalar_to_vector_v8i16(<2 x i32> %in, ptr %out) #0 {
8; GFX900-LABEL: scalar_to_vector_v8i16:
9; GFX900:       ; %bb.0: ; %entry
10; GFX900-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x0
11; GFX900-NEXT:    v_lshlrev_b32_e32 v4, 4, v0
12; GFX900-NEXT:    s_waitcnt lgkmcnt(0)
13; GFX900-NEXT:    v_mov_b32_e32 v5, s3
14; GFX900-NEXT:    v_add_co_u32_e32 v4, vcc, s2, v4
15; GFX900-NEXT:    v_mov_b32_e32 v0, s0
16; GFX900-NEXT:    v_mov_b32_e32 v1, s1
17; GFX900-NEXT:    v_mov_b32_e32 v2, s0
18; GFX900-NEXT:    v_mov_b32_e32 v3, s0
19; GFX900-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
20; GFX900-NEXT:    flat_store_dwordx4 v[4:5], v[0:3]
21; GFX900-NEXT:    s_endpgm
22;
23; GFX906-LABEL: scalar_to_vector_v8i16:
24; GFX906:       ; %bb.0: ; %entry
25; GFX906-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x0
26; GFX906-NEXT:    v_lshlrev_b32_e32 v4, 4, v0
27; GFX906-NEXT:    s_waitcnt lgkmcnt(0)
28; GFX906-NEXT:    v_mov_b32_e32 v5, s3
29; GFX906-NEXT:    v_add_co_u32_e32 v4, vcc, s2, v4
30; GFX906-NEXT:    v_mov_b32_e32 v0, s0
31; GFX906-NEXT:    v_mov_b32_e32 v1, s1
32; GFX906-NEXT:    v_mov_b32_e32 v2, s0
33; GFX906-NEXT:    v_mov_b32_e32 v3, s0
34; GFX906-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
35; GFX906-NEXT:    flat_store_dwordx4 v[4:5], v[0:3]
36; GFX906-NEXT:    s_endpgm
37;
38; GFX908-LABEL: scalar_to_vector_v8i16:
39; GFX908:       ; %bb.0: ; %entry
40; GFX908-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x0
41; GFX908-NEXT:    v_lshlrev_b32_e32 v4, 4, v0
42; GFX908-NEXT:    s_waitcnt lgkmcnt(0)
43; GFX908-NEXT:    v_mov_b32_e32 v5, s3
44; GFX908-NEXT:    v_add_co_u32_e32 v4, vcc, s2, v4
45; GFX908-NEXT:    v_mov_b32_e32 v0, s0
46; GFX908-NEXT:    v_mov_b32_e32 v1, s1
47; GFX908-NEXT:    v_mov_b32_e32 v2, s0
48; GFX908-NEXT:    v_mov_b32_e32 v3, s0
49; GFX908-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
50; GFX908-NEXT:    flat_store_dwordx4 v[4:5], v[0:3]
51; GFX908-NEXT:    s_endpgm
52;
53; GFX90A-LABEL: scalar_to_vector_v8i16:
54; GFX90A:       ; %bb.0: ; %entry
55; GFX90A-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x0
56; GFX90A-NEXT:    v_and_b32_e32 v4, 0x3ff, v0
57; GFX90A-NEXT:    v_lshlrev_b32_e32 v4, 4, v4
58; GFX90A-NEXT:    s_waitcnt lgkmcnt(0)
59; GFX90A-NEXT:    v_mov_b32_e32 v5, s3
60; GFX90A-NEXT:    v_add_co_u32_e32 v4, vcc, s2, v4
61; GFX90A-NEXT:    v_mov_b32_e32 v0, s0
62; GFX90A-NEXT:    v_mov_b32_e32 v1, s1
63; GFX90A-NEXT:    v_mov_b32_e32 v2, s0
64; GFX90A-NEXT:    v_mov_b32_e32 v3, s0
65; GFX90A-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
66; GFX90A-NEXT:    flat_store_dwordx4 v[4:5], v[0:3]
67; GFX90A-NEXT:    s_endpgm
68entry:
69  %val.1.i32 = extractelement <2 x i32> %in, i64 0
70  %val.2.vec2.i16 = bitcast i32 %val.1.i32 to <2 x i16>
71  %val.3.vec8.i16 = shufflevector <2 x i16> %val.2.vec2.i16, <2 x i16> %val.2.vec2.i16, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
72
73  %val.4.vec4.i32 = shufflevector <2 x i32> %in, <2 x i32> %in, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
74  %val.5.vec8.i16 = bitcast <4 x i32> %val.4.vec4.i32 to <8 x i16>
75
76  %val.6.vec8.i16 = shufflevector <8 x i16> %val.5.vec8.i16, <8 x i16> %val.3.vec8.i16, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 8, i32 9>
77
78  %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
79  %tid.ext = sext i32 %tid to i64
80  %out.gep = getelementptr inbounds <8 x i16>, ptr %out, i64 %tid.ext
81  store <8 x i16> %val.6.vec8.i16, ptr %out.gep, align 16
82
83  ret void
84}
85
86define amdgpu_kernel void @scalar_to_vector_v8f16(<2 x float> %in, ptr %out) #0 {
87; GFX900-LABEL: scalar_to_vector_v8f16:
88; GFX900:       ; %bb.0: ; %entry
89; GFX900-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x0
90; GFX900-NEXT:    v_lshlrev_b32_e32 v4, 4, v0
91; GFX900-NEXT:    s_waitcnt lgkmcnt(0)
92; GFX900-NEXT:    v_mov_b32_e32 v5, s3
93; GFX900-NEXT:    v_add_co_u32_e32 v4, vcc, s2, v4
94; GFX900-NEXT:    v_mov_b32_e32 v0, s0
95; GFX900-NEXT:    v_mov_b32_e32 v1, s1
96; GFX900-NEXT:    v_mov_b32_e32 v3, s0
97; GFX900-NEXT:    v_mov_b32_e32 v2, s0
98; GFX900-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
99; GFX900-NEXT:    flat_store_dwordx4 v[4:5], v[0:3]
100; GFX900-NEXT:    s_endpgm
101;
102; GFX906-LABEL: scalar_to_vector_v8f16:
103; GFX906:       ; %bb.0: ; %entry
104; GFX906-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x0
105; GFX906-NEXT:    v_lshlrev_b32_e32 v4, 4, v0
106; GFX906-NEXT:    s_waitcnt lgkmcnt(0)
107; GFX906-NEXT:    v_mov_b32_e32 v5, s3
108; GFX906-NEXT:    v_add_co_u32_e32 v4, vcc, s2, v4
109; GFX906-NEXT:    v_mov_b32_e32 v0, s0
110; GFX906-NEXT:    v_mov_b32_e32 v1, s1
111; GFX906-NEXT:    v_mov_b32_e32 v3, s0
112; GFX906-NEXT:    v_mov_b32_e32 v2, s0
113; GFX906-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
114; GFX906-NEXT:    flat_store_dwordx4 v[4:5], v[0:3]
115; GFX906-NEXT:    s_endpgm
116;
117; GFX908-LABEL: scalar_to_vector_v8f16:
118; GFX908:       ; %bb.0: ; %entry
119; GFX908-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x0
120; GFX908-NEXT:    v_lshlrev_b32_e32 v4, 4, v0
121; GFX908-NEXT:    s_waitcnt lgkmcnt(0)
122; GFX908-NEXT:    v_mov_b32_e32 v5, s3
123; GFX908-NEXT:    v_add_co_u32_e32 v4, vcc, s2, v4
124; GFX908-NEXT:    v_mov_b32_e32 v0, s0
125; GFX908-NEXT:    v_mov_b32_e32 v1, s1
126; GFX908-NEXT:    v_mov_b32_e32 v3, s0
127; GFX908-NEXT:    v_mov_b32_e32 v2, s0
128; GFX908-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
129; GFX908-NEXT:    flat_store_dwordx4 v[4:5], v[0:3]
130; GFX908-NEXT:    s_endpgm
131;
132; GFX90A-LABEL: scalar_to_vector_v8f16:
133; GFX90A:       ; %bb.0: ; %entry
134; GFX90A-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x0
135; GFX90A-NEXT:    v_and_b32_e32 v4, 0x3ff, v0
136; GFX90A-NEXT:    v_lshlrev_b32_e32 v4, 4, v4
137; GFX90A-NEXT:    s_waitcnt lgkmcnt(0)
138; GFX90A-NEXT:    v_mov_b32_e32 v5, s3
139; GFX90A-NEXT:    v_add_co_u32_e32 v4, vcc, s2, v4
140; GFX90A-NEXT:    v_mov_b32_e32 v0, s0
141; GFX90A-NEXT:    v_mov_b32_e32 v1, s1
142; GFX90A-NEXT:    v_mov_b32_e32 v3, s0
143; GFX90A-NEXT:    v_mov_b32_e32 v2, s0
144; GFX90A-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
145; GFX90A-NEXT:    flat_store_dwordx4 v[4:5], v[0:3]
146; GFX90A-NEXT:    s_endpgm
147entry:
148  %val.1.float = extractelement <2 x float> %in, i64 0
149  %val.2.vec2.half = bitcast float %val.1.float to <2 x half>
150  %val.3.vec8.half = shufflevector <2 x half> %val.2.vec2.half, <2 x half> %val.2.vec2.half, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
151
152  %val.4.vec4.float = shufflevector <2 x float> %in, <2 x float> %in, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
153  %val.5.vec8.half = bitcast <4 x float> %val.4.vec4.float to <8 x half>
154
155  %val.6.vec8.half = shufflevector <8 x half> %val.5.vec8.half, <8 x half> %val.3.vec8.half, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 8, i32 9>
156
157  %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
158  %tid.ext = sext i32 %tid to i64
159  %out.gep = getelementptr inbounds <8 x half>, ptr %out, i64 %tid.ext
160  store <8 x half> %val.6.vec8.half, ptr %out.gep, align 16
161
162  ret void
163}
164
165declare i32 @llvm.amdgcn.workitem.id.x() #1
166
167attributes #0 = { nounwind }
168attributes #1 = { nounwind readnone }
169