xref: /llvm-project/llvm/test/CodeGen/AMDGPU/memcpy-fixed-align.ll (revision 1bf385f10291101163a346c8f075d56e1578351b)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck %s -check-prefix=MUBUF
3; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=+enable-flat-scratch < %s | FileCheck %s -check-prefix=FLATSCR
4
5; Make sure there's no assertion from passing a 0 alignment value
6define void @memcpy_fixed_align(ptr addrspace(5)  %dst, ptr addrspace(1) %src) {
7; MUBUF-LABEL: memcpy_fixed_align:
8; MUBUF:       ; %bb.0:
9; MUBUF-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
10; MUBUF-NEXT:    global_load_dwordx2 v[11:12], v[1:2], off offset:32
11; MUBUF-NEXT:    global_load_dwordx4 v[3:6], v[1:2], off
12; MUBUF-NEXT:    global_load_dwordx4 v[7:10], v[1:2], off offset:16
13; MUBUF-NEXT:    s_lshr_b32 s4, s32, 6
14; MUBUF-NEXT:    s_waitcnt vmcnt(2)
15; MUBUF-NEXT:    buffer_store_dword v11, off, s[0:3], s32 offset:32
16; MUBUF-NEXT:    buffer_store_dword v12, off, s[0:3], s32 offset:36
17; MUBUF-NEXT:    s_waitcnt vmcnt(3)
18; MUBUF-NEXT:    buffer_store_dword v6, off, s[0:3], s32 offset:12
19; MUBUF-NEXT:    buffer_store_dword v5, off, s[0:3], s32 offset:8
20; MUBUF-NEXT:    buffer_store_dword v4, off, s[0:3], s32 offset:4
21; MUBUF-NEXT:    buffer_store_dword v3, off, s[0:3], s32
22; MUBUF-NEXT:    s_waitcnt vmcnt(6)
23; MUBUF-NEXT:    buffer_store_dword v10, off, s[0:3], s32 offset:28
24; MUBUF-NEXT:    buffer_store_dword v9, off, s[0:3], s32 offset:24
25; MUBUF-NEXT:    buffer_store_dword v8, off, s[0:3], s32 offset:20
26; MUBUF-NEXT:    buffer_store_dword v7, off, s[0:3], s32 offset:16
27; MUBUF-NEXT:    ;;#ASMSTART
28; MUBUF-NEXT:    ; use s4
29; MUBUF-NEXT:    ;;#ASMEND
30; MUBUF-NEXT:    s_waitcnt vmcnt(0)
31; MUBUF-NEXT:    s_setpc_b64 s[30:31]
32;
33; FLATSCR-LABEL: memcpy_fixed_align:
34; FLATSCR:       ; %bb.0:
35; FLATSCR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
36; FLATSCR-NEXT:    global_load_dwordx4 v[3:6], v[1:2], off
37; FLATSCR-NEXT:    global_load_dwordx4 v[7:10], v[1:2], off offset:16
38; FLATSCR-NEXT:    global_load_dwordx2 v[11:12], v[1:2], off offset:32
39; FLATSCR-NEXT:    s_mov_b32 s0, s32
40; FLATSCR-NEXT:    s_waitcnt vmcnt(2)
41; FLATSCR-NEXT:    scratch_store_dwordx4 off, v[3:6], s32
42; FLATSCR-NEXT:    s_waitcnt vmcnt(2)
43; FLATSCR-NEXT:    scratch_store_dwordx4 off, v[7:10], s32 offset:16
44; FLATSCR-NEXT:    s_waitcnt vmcnt(2)
45; FLATSCR-NEXT:    scratch_store_dwordx2 off, v[11:12], s32 offset:32
46; FLATSCR-NEXT:    ;;#ASMSTART
47; FLATSCR-NEXT:    ; use s0
48; FLATSCR-NEXT:    ;;#ASMEND
49; FLATSCR-NEXT:    s_waitcnt vmcnt(0)
50; FLATSCR-NEXT:    s_setpc_b64 s[30:31]
51  %alloca = alloca [40 x i8], addrspace(5)
52  call void @llvm.memcpy.p5.p1.i64(ptr addrspace(5) align 4 dereferenceable(40) %alloca, ptr addrspace(1) align 4 dereferenceable(40) %src, i64 40, i1 false)
53  call void asm sideeffect "; use $0", "s"(ptr addrspace(5) %alloca) #0
54  ret void
55}
56
57declare void @llvm.memcpy.p5.p1.i64(ptr addrspace(5) noalias nocapture writeonly, ptr addrspace(1) noalias nocapture readonly, i64, i1 immarg) #0
58
59attributes #0 = { argmemonly nounwind willreturn }
60