1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
2; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1031 < %s | FileCheck %s
3
4; A VGPR loop variable was incorrectly sunk into a flow block, past
5; the si_end_cf reconvergence point.
6
7define void @machinesink_loop_variable_out_of_divergent_loop(i32 %arg, i1 %cmp49280.not, i32 %arg1, i1 %cmp108) {
8; CHECK-LABEL: machinesink_loop_variable_out_of_divergent_loop:
9; CHECK:       ; %bb.0: ; %entry
10; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
11; CHECK-NEXT:    v_and_b32_e32 v1, 1, v1
12; CHECK-NEXT:    v_and_b32_e32 v3, 1, v3
13; CHECK-NEXT:    s_mov_b32 s5, 0
14; CHECK-NEXT:    v_cmp_eq_u32_e64 s4, 1, v1
15; CHECK-NEXT:    v_mov_b32_e32 v1, 0
16; CHECK-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 1, v3
17; CHECK-NEXT:    s_xor_b32 s6, s4, -1
18; CHECK-NEXT:    s_inst_prefetch 0x1
19; CHECK-NEXT:    s_branch .LBB0_3
20; CHECK-NEXT:    .p2align 6
21; CHECK-NEXT:  .LBB0_1: ; %Flow
22; CHECK-NEXT:    ; in Loop: Header=BB0_3 Depth=1
23; CHECK-NEXT:    s_or_b32 exec_lo, exec_lo, s8
24; CHECK-NEXT:    v_add_nc_u32_e32 v4, -4, v4
25; CHECK-NEXT:  .LBB0_2: ; %Flow1
26; CHECK-NEXT:    ; in Loop: Header=BB0_3 Depth=1
27; CHECK-NEXT:    s_or_b32 exec_lo, exec_lo, s7
28; CHECK-NEXT:    v_cmp_ne_u32_e64 s4, 0, v3
29; CHECK-NEXT:    ;;#ASMSTART
30; CHECK-NEXT:    ; j lastloop entry
31; CHECK-NEXT:    ;;#ASMEND
32; CHECK-NEXT:    s_or_b32 s5, s4, s5
33; CHECK-NEXT:    s_andn2_b32 exec_lo, exec_lo, s5
34; CHECK-NEXT:    s_cbranch_execz .LBB0_8
35; CHECK-NEXT:  .LBB0_3: ; %for.body33
36; CHECK-NEXT:    ; =>This Loop Header: Depth=1
37; CHECK-NEXT:    ; Child Loop BB0_6 Depth 2
38; CHECK-NEXT:    v_mov_b32_e32 v4, 0
39; CHECK-NEXT:    v_mov_b32_e32 v3, 0
40; CHECK-NEXT:    s_and_saveexec_b32 s7, s6
41; CHECK-NEXT:    s_cbranch_execz .LBB0_2
42; CHECK-NEXT:  ; %bb.4: ; %for.body51.preheader
43; CHECK-NEXT:    ; in Loop: Header=BB0_3 Depth=1
44; CHECK-NEXT:    s_mov_b32 s8, 0
45; CHECK-NEXT:    s_mov_b32 s9, 0
46; CHECK-NEXT:    s_branch .LBB0_6
47; CHECK-NEXT:    .p2align 6
48; CHECK-NEXT:  .LBB0_5: ; %if.end118
49; CHECK-NEXT:    ; in Loop: Header=BB0_6 Depth=2
50; CHECK-NEXT:    s_or_b32 exec_lo, exec_lo, s4
51; CHECK-NEXT:    s_add_i32 s9, s9, 4
52; CHECK-NEXT:    ;;#ASMSTART
53; CHECK-NEXT:    ; backedge
54; CHECK-NEXT:    ;;#ASMEND
55; CHECK-NEXT:    v_add_nc_u32_e32 v4, s9, v2
56; CHECK-NEXT:    v_cmp_ge_u32_e64 s4, v4, v0
57; CHECK-NEXT:    s_or_b32 s8, s4, s8
58; CHECK-NEXT:    s_andn2_b32 exec_lo, exec_lo, s8
59; CHECK-NEXT:    s_cbranch_execz .LBB0_1
60; CHECK-NEXT:  .LBB0_6: ; %for.body51
61; CHECK-NEXT:    ; Parent Loop BB0_3 Depth=1
62; CHECK-NEXT:    ; => This Inner Loop Header: Depth=2
63; CHECK-NEXT:    v_mov_b32_e32 v3, 1
64; CHECK-NEXT:    s_and_saveexec_b32 s4, vcc_lo
65; CHECK-NEXT:    s_cbranch_execz .LBB0_5
66; CHECK-NEXT:  ; %bb.7: ; %if.then112
67; CHECK-NEXT:    ; in Loop: Header=BB0_6 Depth=2
68; CHECK-NEXT:    s_add_i32 s10, s9, 4
69; CHECK-NEXT:    v_mov_b32_e32 v3, 0
70; CHECK-NEXT:    v_mov_b32_e32 v4, s10
71; CHECK-NEXT:    ds_write_b32 v1, v4
72; CHECK-NEXT:    s_branch .LBB0_5
73; CHECK-NEXT:  .LBB0_8: ; %for.body159.preheader
74; CHECK-NEXT:    s_inst_prefetch 0x2
75; CHECK-NEXT:    s_or_b32 exec_lo, exec_lo, s5
76; CHECK-NEXT:    s_mov_b32 vcc_lo, exec_lo
77; CHECK-NEXT:  .LBB0_9: ; %for.body159
78; CHECK-NEXT:    ; =>This Inner Loop Header: Depth=1
79; CHECK-NEXT:    s_cbranch_vccnz .LBB0_9
80; CHECK-NEXT:  ; %bb.10: ; %DummyReturnBlock
81; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
82; CHECK-NEXT:    s_setpc_b64 s[30:31]
83entry:
84  br label %for.body33
85
86for.body33:                                       ; preds = %for.end121, %entry
87  br i1 %cmp49280.not, label %for.end121, label %for.body51
88
89for.body51:                                       ; preds = %if.end118, %for.body33
90  %add48284 = phi i32 [ %add48, %if.end118 ], [ %arg1, %for.body33 ]
91  %collision.0281 = phi i32 [ %inc119, %if.end118 ], [ 1, %for.body33 ]
92  br i1 %cmp108, label %if.then112, label %if.end118
93
94if.then112:                                       ; preds = %for.body51
95  %inc101 = add i32 %collision.0281, 3
96  store i32 %inc101, ptr addrspace(3) null, align 2147483648
97  br label %if.end118
98
99if.end118:                                        ; preds = %if.then112, %for.body51
100  %thCollNum.5 = phi i32 [ 0, %if.then112 ], [ 1, %for.body51 ]
101  %inc119 = add i32 %collision.0281, 4
102  tail call void asm sideeffect "; backedge", ""()
103  %add48 = add i32 %add48284, 4
104  %cmp49 = icmp ult i32 %add48, %arg
105  br i1 %cmp49, label %for.body51, label %for.end121
106
107for.end121:                                       ; preds = %if.end118, %for.body33
108  %thCollNum.1.lcssa = phi i32 [ 0, %for.body33 ], [ %thCollNum.5, %if.end118 ]
109  %j.0.lcssa = phi i32 [ 0, %for.body33 ], [ %add48284, %if.end118 ]
110  %i5 = tail call i32 asm sideeffect "; j lastloop entry", "=v,0"(i32 %j.0.lcssa)
111  %cmp31 = icmp eq i32 %thCollNum.1.lcssa, 0
112  br i1 %cmp31, label %for.body33, label %for.body159
113
114for.body159:                                      ; preds = %for.body159, %for.end121
115  br label %for.body159
116}
117