1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -run-pass=machine-cse -o - %s | FileCheck %s 3# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -run-pass=machine-cse -o - %s | FileCheck %s 4 5--- | 6 define void @commute_instruction_subreg_target_flag() { ret void } 7 define void @commute_target_flag_frame_index() { ret void } 8 define void @commute_target_flag_global() { ret void } 9 define void @commute_target_flag_global_offset() { ret void } 10 define void @commute_target_flag_global_offset_mismatch() { ret void } 11 12 declare void @func() 13 @gv = external addrspace(1) global i32 14 15... 16 17# Make sure the subreg index is cleared when commuting a register and immediate. 18 19--- 20name: commute_instruction_subreg_target_flag 21tracksRegLiveness: true 22body: | 23 bb.0: 24 liveins: $vgpr0_vgpr1 25 26 ; CHECK-LABEL: name: commute_instruction_subreg_target_flag 27 ; CHECK: liveins: $vgpr0_vgpr1 28 ; CHECK-NEXT: {{ $}} 29 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 30 ; CHECK-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY]].sub1, 64, 0, implicit $exec 31 ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_ADD_U32_e64_]], implicit [[V_ADD_U32_e64_]] 32 %0:vreg_64 = COPY $vgpr0_vgpr1 33 %1:vgpr_32 = V_ADD_U32_e64 %0.sub1, 64, 0, implicit $exec 34 %2:vgpr_32 = V_ADD_U32_e64 64, %0.sub1, 0, implicit $exec 35 S_ENDPGM 0, implicit %1, implicit %2 36 37... 38 39# FIXME: Why doesn't this CSE? 40--- 41name: commute_target_flag_frame_index 42tracksRegLiveness: true 43stack: 44 - { id: 0, type: default, offset: 0, size: 4, alignment: 4 } 45body: | 46 bb.0: 47 liveins: $vgpr0_vgpr1 48 49 ; CHECK-LABEL: name: commute_target_flag_frame_index 50 ; CHECK: liveins: $vgpr0_vgpr1 51 ; CHECK-NEXT: {{ $}} 52 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 53 ; CHECK-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 %stack.0, [[COPY]].sub0, 0, implicit $exec 54 ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_ADD_U32_e64_]], implicit [[V_ADD_U32_e64_]] 55 %0:vreg_64 = COPY $vgpr0_vgpr1 56 %1:vgpr_32 = V_ADD_U32_e64 %0.sub0, %stack.0, 0, implicit $exec 57 %2:vgpr_32 = V_ADD_U32_e64 %stack.0, %0.sub0, 0, implicit $exec 58 S_ENDPGM 0, implicit %1, implicit %2 59 60... 61 62# FIXME: Handle commuting global variables 63--- 64name: commute_target_flag_global 65tracksRegLiveness: true 66body: | 67 bb.0: 68 liveins: $sgpr0_sgpr1 69 70 ; CHECK-LABEL: name: commute_target_flag_global 71 ; CHECK: liveins: $sgpr0_sgpr1 72 ; CHECK-NEXT: {{ $}} 73 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1 74 ; CHECK-NEXT: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY]].sub0, target-flags(amdgpu-rel32-lo) @func, implicit-def dead $scc 75 ; CHECK-NEXT: S_ENDPGM 0, implicit [[S_ADD_U32_]], implicit [[S_ADD_U32_]] 76 %0:sreg_64 = COPY $sgpr0_sgpr1 77 %1:sreg_32 = S_ADD_U32 %0.sub0, target-flags(amdgpu-rel32-lo) @func, implicit-def dead $scc 78 %2:sreg_32 = S_ADD_U32 target-flags(amdgpu-rel32-lo) @func, %0.sub0, implicit-def dead $scc 79 S_ENDPGM 0, implicit %1, implicit %2 80 81... 82 83--- 84name: commute_target_flag_global_offset 85tracksRegLiveness: true 86body: | 87 bb.0: 88 liveins: $sgpr0_sgpr1 89 90 ; CHECK-LABEL: name: commute_target_flag_global_offset 91 ; CHECK: liveins: $sgpr0_sgpr1 92 ; CHECK-NEXT: {{ $}} 93 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1 94 ; CHECK-NEXT: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY]].sub0, target-flags(amdgpu-rel32-lo) @gv + 4, implicit-def dead $scc 95 ; CHECK-NEXT: S_ENDPGM 0, implicit [[S_ADD_U32_]], implicit [[S_ADD_U32_]] 96 %0:sreg_64 = COPY $sgpr0_sgpr1 97 %1:sreg_32 = S_ADD_U32 %0.sub0, target-flags(amdgpu-rel32-lo) @gv + 4, implicit-def dead $scc 98 %2:sreg_32 = S_ADD_U32 target-flags(amdgpu-rel32-lo) @gv + 4, %0.sub0, implicit-def dead $scc 99 S_ENDPGM 0, implicit %1, implicit %2 100 101... 102 103--- 104name: commute_target_flag_global_offset_mismatch 105tracksRegLiveness: true 106body: | 107 bb.0: 108 liveins: $sgpr0_sgpr1 109 110 ; CHECK-LABEL: name: commute_target_flag_global_offset_mismatch 111 ; CHECK: liveins: $sgpr0_sgpr1 112 ; CHECK-NEXT: {{ $}} 113 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1 114 ; CHECK-NEXT: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY]].sub0, target-flags(amdgpu-rel32-lo) @gv + 4, implicit-def dead $scc 115 ; CHECK-NEXT: [[S_ADD_U32_1:%[0-9]+]]:sreg_32 = S_ADD_U32 target-flags(amdgpu-rel32-lo) @gv + 8, [[COPY]].sub0, implicit-def dead $scc 116 ; CHECK-NEXT: S_ENDPGM 0, implicit [[S_ADD_U32_]], implicit [[S_ADD_U32_1]] 117 %0:sreg_64 = COPY $sgpr0_sgpr1 118 %1:sreg_32 = S_ADD_U32 %0.sub0, target-flags(amdgpu-rel32-lo) @gv + 4, implicit-def dead $scc 119 %2:sreg_32 = S_ADD_U32 target-flags(amdgpu-rel32-lo) @gv + 8, %0.sub0, implicit-def dead $scc 120 S_ENDPGM 0, implicit %1, implicit %2 121 122... 123