1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: opt -S -mtriple=amdgcn-- -structurizecfg -si-annotate-control-flow %s | FileCheck -check-prefix=IR %s 3; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck %s 4 5define void @loop_on_argument(i1 %arg) { 6; IR-LABEL: @loop_on_argument( 7; IR-NEXT: entry: 8; IR-NEXT: br label [[LOOP:%.*]] 9; IR: loop: 10; IR-NEXT: [[PHI_BROKEN:%.*]] = phi i64 [ [[TMP0:%.*]], [[LOOP]] ], [ 0, [[ENTRY:%.*]] ] 11; IR-NEXT: [[TMP0]] = call i64 @llvm.amdgcn.if.break.i64(i1 [[ARG:%.*]], i64 [[PHI_BROKEN]]) 12; IR-NEXT: store volatile i32 0, ptr addrspace(1) undef, align 4 13; IR-NEXT: [[TMP1:%.*]] = call i1 @llvm.amdgcn.loop.i64(i64 [[TMP0]]) 14; IR-NEXT: br i1 [[TMP1]], label [[EXIT:%.*]], label [[LOOP]] 15; IR: exit: 16; IR-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 [[TMP0]]) 17; IR-NEXT: ret void 18; 19; CHECK-LABEL: loop_on_argument: 20; CHECK: ; %bb.0: ; %entry 21; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 22; CHECK-NEXT: v_and_b32_e32 v0, 1, v0 23; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0 24; CHECK-NEXT: s_mov_b64 s[4:5], 0 25; CHECK-NEXT: v_mov_b32_e32 v0, 0 26; CHECK-NEXT: .LBB0_1: ; %loop 27; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1 28; CHECK-NEXT: s_and_b64 s[6:7], exec, vcc 29; CHECK-NEXT: s_or_b64 s[4:5], s[6:7], s[4:5] 30; CHECK-NEXT: global_store_dword v[0:1], v0, off 31; CHECK-NEXT: s_waitcnt vmcnt(0) 32; CHECK-NEXT: s_andn2_b64 exec, exec, s[4:5] 33; CHECK-NEXT: s_cbranch_execnz .LBB0_1 34; CHECK-NEXT: ; %bb.2: ; %exit 35; CHECK-NEXT: s_or_b64 exec, exec, s[4:5] 36; CHECK-NEXT: s_setpc_b64 s[30:31] 37entry: 38 br label %loop 39 40loop: 41 store volatile i32 0, ptr addrspace(1) undef 42 br i1 %arg, label %exit, label %loop 43 44exit: 45 ret void 46} 47