1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 2; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck %s -check-prefix=GFX11 3; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck %s -check-prefix=GFX12 4 5define amdgpu_cs void @test_uniform_load_b96(ptr addrspace(1) %ptr, i32 %arg) "amdgpu-flat-work-group-size"="1,1" { 6; GFX11-LABEL: test_uniform_load_b96: 7; GFX11: ; %bb.0: ; %bb 8; GFX11-NEXT: v_mov_b32_e32 v3, 0 9; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) 10; GFX11-NEXT: v_lshlrev_b64 v[2:3], 2, v[2:3] 11; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v0, v2 12; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) 13; GFX11-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, v1, v3, vcc_lo 14; GFX11-NEXT: v_readfirstlane_b32 s0, v2 15; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) 16; GFX11-NEXT: v_readfirstlane_b32 s1, v3 17; GFX11-NEXT: s_clause 0x1 18; GFX11-NEXT: s_load_b64 s[2:3], s[0:1], 0x0 19; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x8 20; GFX11-NEXT: s_waitcnt lgkmcnt(0) 21; GFX11-NEXT: v_mov_b32_e32 v2, s3 22; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) 23; GFX11-NEXT: v_or3_b32 v2, s2, v2, s0 24; GFX11-NEXT: global_store_b32 v[0:1], v2, off 25; GFX11-NEXT: s_endpgm 26; 27; GFX12-LABEL: test_uniform_load_b96: 28; GFX12: ; %bb.0: ; %bb 29; GFX12-NEXT: v_mov_b32_e32 v3, 0 30; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) 31; GFX12-NEXT: v_lshlrev_b64_e32 v[2:3], 2, v[2:3] 32; GFX12-NEXT: v_add_co_u32 v2, vcc_lo, v0, v2 33; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) 34; GFX12-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, v1, v3, vcc_lo 35; GFX12-NEXT: v_readfirstlane_b32 s0, v2 36; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) 37; GFX12-NEXT: v_readfirstlane_b32 s1, v3 38; GFX12-NEXT: s_load_b96 s[0:2], s[0:1], 0x0 39; GFX12-NEXT: s_wait_kmcnt 0x0 40; GFX12-NEXT: v_mov_b32_e32 v2, s0 41; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) 42; GFX12-NEXT: v_or3_b32 v2, v2, s1, s2 43; GFX12-NEXT: global_store_b32 v[0:1], v2, off 44; GFX12-NEXT: s_endpgm 45bb: 46 %i = zext i32 %arg to i64 47 %i1 = getelementptr i32, ptr addrspace(1) %ptr, i64 %i 48 %i2 = load <3 x i32>, ptr addrspace(1) %i1, align 4 49 %i3 = extractelement <3 x i32> %i2, i32 0 50 %i4 = extractelement <3 x i32> %i2, i32 1 51 %i5 = extractelement <3 x i32> %i2, i32 2 52 %i6 = or i32 %i3, %i4 53 %i7 = or i32 %i5, %i6 54 store i32 %i7, ptr addrspace(1) %ptr, align 4 55 ret void 56} 57